MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION
This system is an NTSC system PinP system that accommodates
subscreen composite input and main screen Y/C input. It is a
semiconductor IC circuit having a built-in 96K bit field memory and
an analog circuit, which permits a low-cost and compact system
configuration.
FEATURES
•
•
•
•
•
•
•
APPLICATION
TV
RECOMMENDED OPERATING CONDITION
Supply voltage range........................................................3.1 to 3.5V
Operating frequency.........................................................14.32 MHz
Operating temperature....................................................-10 to 75°C
Input voltage (CMOS interface) "H"........................V DD×0.7 to VDD V
"L".............................0 to VDD×0.3V
Output current (output buffer)........................................ ±4mA (MAX)
Output load capacitance............................................20pF (MAX)
∗1
Circuit current.........................................................................140mA
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS
pins.
∗1 : Include pin capacitance (7pF)
1
AVss3 (vcxo)
1
VCXO out
2
51 Cin
VCXO in
3
50
TESTEN
FILTER
4
49
Yin
BIAS
5
48
TEST9
AVdd3 (vcxo)
6
47
Y-PIP
AVdd2 (m)
7
46
TEST8
Vin (m)
8
45
C-PIP
52
AVssf (ana)
Vrt (m)
9
44
AVdd4 (da)
Vrb (m)
10
43
C-PIPin
AVss2 (m)
11
42
AVss4 (da)
AVdd1 (s)
12
41
Y-PIPin
Vin (s)
13
40
ADJ-Ysub
Vrt (s)
14
39
Yout-sub
Vrb (s)
15
38
ADJ-Csub
AVss1 (s)
16
37
Cout-sub
RESET
17
36
DVss3 (ram)
DVss1
18
35
DVdd3 (ram)
DVdd1
19
34
SWMG/TEST7
BGP(s)/TEST0
20
33
VD/CSYNC/TEST6
SCK
21
32
HD/TEST5
CSYNC(s)/TEST1
22
31
SWM/TEST4
ACK
23
30
MCK
DATA
24
29
fsc/TEST3
CLK
25
28
BGP(m)/TEST2
DVss2
26
27
DVdd2
M65617SP
•
•
Built-in field memory 96K bit for PIP
Built-in luminance signal vertical filter
No. of subscreen displays: 1 (two sizes, 1/9 and 1/16, can be
selected from.)
No. of subscreen samples (1/9 - 1/16 sizes)
No. of quantization bits: 6 for all Y, B-Y and R-Y
No. of horizontal picture elements: 171(Y), 28.5 (B-Y, R-Y)
No. of vertical lines: 69/52
Subscreen frame display ON/OFF
Built-in analog circuits such as sync chip clamp, VCXO, and analog switch
Built-in 2 channels of 8 bit A/D converter
(for main signal burst lock and PIP sub signal)
Built-in two channels of 8 bit D/A converter (luminance and
chroma signals)
I2C bus control
Controls: display ON/OFF, display size selection, setting of
display position, frame ON/OFF, setting of frame level, selection
of frame animation/field still image, setting of Y delay amount,
color level, tint, black level, etc.
PIN CONFIGURATION (TOP VIEW)
Outline 52P4B
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
BLOCK DIAGRAM
CSYNC(s)
/TEST1
SCK
BGP(s)
/TEST0
Yin
Y- PIP
Sync tip
Clamp
Cin
Vdd / Vss
for test
DATA
CLK
ACK
Bias
C- PIP
15
RAM(1H)
3
3
Bias
I2C
I/F
A/D
8bit
Sync tip
Clamp
Vrt(m)
Vrb(m)
6
Y/C SEP
(LPF,BPF)
Vert-filter
Sync
Sep
2
HD
Y
Delay
Luma
Clamp
Y
Vin(s)
Phase
Select
C
Timing Gen
(Decode)
AFC
Demod
Tint
B-Y
6
R-Y
6
2
(I C)
Delay
Encode
D/A
8bit
Yout-sub
D/A
8bit
Cout-sub
Delay
Delay
MIX
SWMG
/TEST7
Y
6 B-Y
LPF
&MPY
fsc
6
6 R-Y
Vin(m)
Bias
A/D
8bit
Timing Gen
(Memory
Cont)
RAM
96Kbits
VD
/CSYNC
/TEST6
HD
/TEST5
FILTER
Lock/Free-run
via I2C
2
RESET
MCK
BGP(m)
/TEST2
fsc
/TEST3
BIAS
4fsc
Phase
Detect
Burst Data
Sampling
Y- PIPin
&
Level
Detect
ADJ-Csub
Vrt(m)
Vrb(m)
4fsc
Back Porch
Clamp
MUX
Y
B-Y
R-Y
Demux
HPLL
ADJ-Ysub
C- PIPin
VCXO
Driver
VCXO
VCXO in
VCXO out
SWM
/TEST4
2
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION OF PIN
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
GND
O
I
O
O
Vdd
Vdd
I
O
O
GND
Vdd
I
O
O
GND
Function
Grounding (analog burst lock PLL section)
Oscillation output signal
Oscillation input signal
Filter
Bias
Power supply (analog burst lock PLL section)
Power supply (analog main signal A/D section)
Main color input signal
Main signal A/D reference voltage output +
Main signal A/D reference voltage output Grounding (analog main signal A/D section)
Power supply (analog sub-signal A/D section)
Sub-composite video input signal
Sub-signal A/D reference voltage output +
Sub-signal A/D reference voltage output Grounding (analog sub-signal A/D section)
Connected to the power supply with
100kΩ, and grounded with 10µF
Grounding (digital section)
Power supply (digital section)
Sub-screen burst gate pulse output
Sub-screen 4fsc clock input
Sub-screen CSYNC input
Open
Grounding
Pulldown 15k Ω
RESET
I
18
19
20
21
22
23
DVss1
DVdd1
ACK
GND
Vdd
(I/)O
I
I(/O)
O
24
DATA
I
I2C bus data input signal
25
CLK
I
26
27
28
29
30
31
32
DVss2
DVdd2
GND
Vdd
(I/)O
I(/O)
I
(I/)O
I(/O)
I2C bus clock input signal
Grounding (digital section)
Power supply (digital section)
For testing
For testing
For testing
For testing
Horizontal sync input signal
I(/O)
Vertical sync input signal
I(/O)
Vdd
GND
O
O
O
O
I
GND
I
Vdd
O
I
O
I
I
I
I
Vss
Sub-screen display authorization input signal
Power supply (digital RAM section)
Grounding (digital RAM section)
Sub-screen color signal D/A output signal
For adjustment of sub-screen color signal D/A
Sub-screen luminance signal D/A output signal
For adjustment of sub-screen luminance signal D/A
Sub-screen luminance signal re-input signal
Grounding (analog D/A and SW sections)
Sub-screen color signal re-input signal
Power supply (analog D/A & SW sections)
PIP color signal output signal
For testing
PIP luminance signal output signal
For testing
Main luminance input signal
For testing
Main color input signal
Grounding (analog section)
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
BGP(s)/TEST0
SCK
CSYNC(s)/TEST1
BGP(m)/TEST2
fsc/TEST3
MCK
SWM/TEST4
HD/TEST5
VD/CSYNC/
TEST6
SWMG/TEST7
DVdd3 (ram)
DVss3 (ram)
Cout-sub
ADJ-Csub
Yout-sub
ADJ-Ysub
Y-PIPin
AVss4 (da)
C-PIPin
AVdd4 (da)
C-PIP
TEST8
Y-PIP
TEST9
Yin
TESTEN
Cin
AVssf (ana)
Remarks
Power-ON reset input signal.
17
33
3
Name
AVss3 (VCXO)
VCXO out
VCXO in
FILTER
BIAS
AVdd3 (VCXO)
AVdd2 (m)
Vin (m)
Vrt (m)
Vrb (m)
AVss2 (m)
AVdd1 (s)
Vin (s)
Vrt (s)
Vrb (s)
AVss1 (s)
I2C bus data/acknowledge output signal
Open
Pulldown 15k Ω
Grounding
Open
Pullup 15k Ω
Pullup 15kΩ
Grounding
Grounding
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
ABSOLUTE MAXIMUM RATINGS (VSS=0V)
Symbol
Limits
Min.
Max.
Parameter
VDD3
VI
VO
Supply voltage (3.3V)
Input voltage
Output voltage
IO
Output current (∗1)
Pd
Topr
Tstg
Power dissipation
Operating temperature
Storage temperature
-0.3
-0.3
-0.3
−
−
−
-10
-50
Unit
4.6
V
V
V
VDD3+0.3
VDD3+0.3
IOL=20
IOH=-26
mA
1400
75
125
mW
°C
°C
∗1: Output current per output terminal. But Pd limits all current.
DC ELECTRICAL CHARACTERISTICS (VSS=0V)
Symbol
Parameter
VIL
VIH
VTV T+
VH
VOL
VOH
IOL
IOH
IIH
IIL
IOZL
IOZH
CI
CO
CIO
IDD
Test conditions
Input voltage
(CMOS interface)
Input voltage schmitt trigger
(CMOS interface)
L level
H level
VDD=2.7V
VDD=3.6V
–
+
VDD=3.3V
Hysteresis
Output voltage
L level
H level
VDD=3.3V, | IO | <1µA
Output current
L level
H level
Input current
L level
H level
Output leakage current
L level
H level
VDD=3.0V, VOL=0.4V
VDD=3.0V, VOH=2.6V
VDD=3.6V, VI=0V
VDD=3.6V, VI=3.6V
VDD=3.6V, VO=0V
VDD=3.6V, VO=3.6V
Input pin capacitance
Output pin capacitance
Bidirectional pin capacitance
Operating current
f=1MHz, VDD=0V
3.3V supply
Min.
0
2.52
0.5
1.4
0.3
−
3.25
4
−
-1
-1
-1
-1
−
−
−
−
Limits
Typ.
−
−
−
−
−
−
−
−
−
−
−
−
−
7
7
7
−
Max.
0.81
3.6
1.65
2.4
1.2
0.05
−
−
-4
1
1
1
1
15
15
15
140
Unit
V
V
V
V
V
V
V
mA
mA
µA
µA
µA
µA
pF
pF
pF
mA
TYPICAL CHARACTERISTICS
THERMAL DERATING (MAXIMUM RATING)
POWER DISSIPATION Pd (mW)
2000
1600
1490
1200
800
400
0
0
25
50
75
100
125
AMBIENT TEMPERATURE Ta (°C)
4
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
SERIAL REGISTER INFORMATION (device address=24h, sub-address=00h to 0Fh)
Registers requiring user selection/adjustment setting are enclosed in rectangles.
Indication method of reference setting column: Thick letters: Fixed setting value
Standard letters: An example as setting for evaluation
∗/∗: 1/9 - 1/16 sizes
Subaddress
00h
01h
02h
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
Reference
setting
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
color (0)
color (1)
color (2)
color (3)
color (4)
color (5)
color (6)
killer
tint (0)
tint (1)
tint (2)
tint (3)
tint (4)
tint (5)
afcoff
7
NB
decode
0
1
2
3
4
5
0
0
0
1
0
0
Bit No.
6
7
0
1
2
3
03h
4
5
6
04h
5
Register name
evenupra
bgcs
extport (0)
extport (1)
adclocksel (0)
adclocksel (1)
1
mode (0)
0
mode (1)
1
crtint (0)
1
crtint (1)
1/0
size-h
0
hpfoff
NB
bgpmsel
1 in case of 03h<7>(rvs)=1 or
03h<6>(rvhs)=1,
0 in other cases
0/1
size
0
rvhs
7
0
0
1
2
3
4
5
6
7
0
0
1
0
0
1
1
NB
rvs
ydl (0)
ydl (1)
ydl (2)
ydl (3)
test acc lvl
wen
grc
stnby=testreset
Function
Color saturation adjustment; min. value [0], max. value[63], 1/step [3Fh setting]
[1 setting]
Color killer; ON [0], OFF [1], [0 setting]
Tint adjustment; setting by complements of 2
0fl to -50fl [00h to 1Fh]
+50fl to 0fl [20h to 3Fh]
[Normally 00h setting]
[0 setting]
Initialization of sub-screen color demodulation; normally [0], initialized [1]
Each time reset is cleared and sub-screen input source changed, operate in a
sequence of 0 - 1 - 0.
Setting of interlace leading line; leading field first/second [1/0], [0 setting]
Forced writing of background level [1 significant, normally 0] [0 setting]
I2C bus expansion port data (optional function); [Set to either of them]
Selection of adc clock delay; [00b setting]
Selection of IC operation mode; [01b setting] 16 bits [0]
Setting of sub-screen tint offset; [11b setting]
Horizontal size
Emphasis of high luminance signal area ON/OFF [0/1] [0 setting]
Selection of PIP-Y output clamping pulse; [0 setting when PIP is displayed]
Vertical size
Addition of sync, burst; OFF/ON [0/1] [Normally 0 setting when PIP is displayed]
Sync operation; Main input is followed [0], self-propelled [1] [0 setting when PIP is
displayed]
Setting of sub-screen Y delay amount
(D/A output phase against color signal); [4 setting]
Min. 280ns [0h], center 0ns [4h], max. +770ns [Fh]
acc reference level setting authorization; [1 significant] [0 setting]
Display of field still screen/display of animation [0/1]
Display of sub-screen frame; NO/YES [0/1]
[0] setting (memory access not operated by [1])
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
SERIAL REGISTER INFORMATION (cont.)
Subaddress
05h
06h
07h
08h
09h
0Ah
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
Reference
setting
1/0
1/0
1/0
0/0
0/0
1/0
1/0
0/0
0
0
0
0
0
0
1
NB
0
0
0
1
0
0
0
1
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
0
0
1
0
0
1
1
1
0
1
0
1
0
0/0
0/0
0/0
0/1
0/0
1/1
0/0
0/0
Bit No.
Register name
hp (0)
hp (1)
hx (0)
hx (1)
hx (2)
hx (3)
hx (4)
hx (5)
contrast (0)
contrast (1)
contrast (2)
contrast (3)
contrast (4)
contrast (5)
contrast (6)
free-run
bgy (2)
bgy (3)
bgy (4)
bgy (5)
ext-sync-sel (0)
ext-sync-sel (1)
lpf-sel (0)
lpf-sel (1)
bgby (0)
bgby (1)
bgby (2)
bgry (0)
bgry (1)
bgry (2)
mvc (0)
mvc (1)
bstby (0)
bstby (1)
bstby (2)
bstby (3)
bstby (4)
bstby (5)
bstby (6)
bstby (7)
vxa (0)
vxa (1)
vxa (2)
vxa (3)
vxa (4)
vxa (5)
vxa (6)
vxa (7)
Function
Sample start position
Fine adjustment; 70ns/step
Sample start position
Rough adjustment;
Formula: {4-hp<1:0>+(3Fh-hx<5:0>)×4}×70ns-2.5us
Luminance signal sub-DAC control;
1V output at 40h, max. 1.8V output
1V output from sync chip to white peak at 40h
Luminance signal level during image period is 100/130 (IRE ratio) x 1V
[40h setting with evaluation board]
vcxo oscillation control; lock loop/self-propelled oscillation [0/1]
Setting of frame and background luminance level; [8h setting in the case of black
frame]
Selection of sub-screen sync input; [Normally 0 setting]
Digital [0 or 1], external pin input [2], internal analog [3]
Selection of sub-screen luminance signal band [2 setting]
2.3 [00b], 2.1 [01b], 1.6 [10b], 1.3 [11b]MHz
Setting of background b-y level; 8 gradations
0(min.)→4(center)→7(max.) (4 setting if colorless)
Setting of background r-y level; 8 gradations
0(min.)→4(center)→7(max.) (4 setting if colorless)
Setting of noise mask gate range for sub-signal sync;
48us [0], 44us [1], 53us [2], OFF [3] [0 setting]
Setting of color signal output burst b-y level; 256 gradations
00h(min.)→80h(center)→FFh(max.)
Setting of display start position (vertical); {vxa<7.0>+17 or 16 (1st field)}line
[20h/28h(1/9 - 1/16 sizes) when displayed at the upper left]
6
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
SERIAL REGISTER INFORMATION (cont.)
Subaddress
0Bh
0Ch
0Dh
0Eh
0Fh
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
Reference
setting
0/1
0/1
1/0
0/0
0/1
0/1
1/0
0/0
0/0
0/0
0/0
1/0
0/1
0/0
0/0
0/0
0/1
0/0
0/0
1/1
1/0
1/1
1
1
0
0
1
0
1
1
1
1
1
0
2
0
dofc
3
1
y-offset (0)
4
5
6
7
1
1
1
0
y-offset (1)
y-offset (2)
y-offset (3)
y-offset (4)
Bit No.
Register name
vya (0)
vya (1)
vya (2)
vya (3)
vya (4)
vya (5)
vya (6)
vya (7)
hxa (0)
hxa (1)
hxa (2)
hxa (3)
hxa (4)
hxa (5)
hxa (6)
hxa (7)
hya (0)
hya (1)
hya (2)
hya (3)
hya (4)
hya (5)
ext-bhsel (0)
ext-bhsel (1)
adj (0)
adj (1)
adj (2)
adj (3)
hadj (0)
hadj (1)
hadj (2)
hadj (3)
disp
bgc
Function
Setting of display period (vertical);
{vya<7:0>} line
[44h/33h (1/9-1/16 sizes)]
Setting of display start position (horizontal);
{hxa0<7:0>×4×70ns+12.8}us
[08h-10h (1/9-1/6 sizes) when displayed at the upper left]
Setting of display period (horizontal);
{(hya0<5:0>-1)×4×70}us
[38h/29h (1/9 - 1/16 sizes)]
Selection of sync input for burst clock;
HD pin [0 or 1], VD pin [2], internal analog [3] [3 setting]
Adjustment of sub-screen display-starting horizontal position; [4h setting]
70ns/step
Min. 280ns [0h], center 0ns [4h], +770ns [Fh]
Adjustment of supplementary BGP position; [Normally Fh setting]
Parameter to adjust PIP Y output signal clamping position to main Y input signal
pedestal (when 03h<4>(bgpmsel) = 1)
5.6us[0h], 6.6us [Fh] (pulse width: 2.6us) from the front end of horizontal sync
Display control; PIP display OFF/ON [0/1] (ineffective at background)
Background display control; OFF/ON [0/1]
Authorization of addition of sync when missing main source is detected; OFF/
ON [0/1]
Setting of luminance signal output DC offset;
Set pedestal level within a range of 32 digits/256 digits (complements of 2, "-16fl
to +15fl" or "0", provides image data bottom values. It serves fine adjustment of
brightness.)
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
SERIAL REGISTER INFORMATION
(device address=24h, subaddress=10h to 1Bh)
(Device adress=25h [output], subaddress=1Ch to 1Fh
Indication method of reading column: 0 or 1.... Register with readings
∗.... Register unused
Subaddress
Bit No.
0
10h
11h
12h
13h
14h
Reference
Register name
setting
0
bg-start (0)
1
2
3
4
5
6
7
0
1
2
3
4
5
1
1
1
0
0
1
0
0
0
0
0
0
0
bg-start (1)
bg-start (2)
bg-start (3)
bg-start (4)
bg-start (5)
swap
set-pd-out
no-bst-level (0)
no-bst-level (1)
bw-level (0)
bw-level (1)
ext-mh-sel (0)
ext-mh-sel (1)
6
0
ext-mv-sel
7
0
1
0
pin28osel
color-set (0)
1
2
3
4
5
6
0
0
0
0
0
1
color-set (1)
color-set (2)
color-set (3)
color-set (4)
color-set (5)
color-set (6)
7
NB
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
0
1
1
1
0
0
0
1
1
1
1
1
1
1
0
test-pip-c-dac-ctrl
bgpx (0)
bgpx (1)
bgpx (2)
bgpx (3)
bgpx (4)
bgpx (5)
test-sel180d
ti-sel180d
color2 (0)
color2 (1)
color2 (2)
color2 (3)
color2 (4)
color2 (5)
dft-wtg
teg-vbrin
Function
Setting of burst gate pulse phase for internal burst lock;
Min.value [0], max.value [63],70ns/step
[0Eh setting]
(4.8us, pulse width 3us from the front end of horizontal sync)
chg, dis output transfer control; default/reversal [0/1], [1 setting]
For testing [0 setting]
For testing [0 setting]
For testing [0 setting]
Selection of main horizontal sync signal input; [normally 0 setting]
HD pin[0 or 1], VD-CSYNC pin[2], internal analog [3]
election of main vertical sync signal input; VD-CSYNC pin/internal analog [0/1]
[Normally 0 setting]
Selection of 28 pin output; BGPM [0], RDOF [1] [Normally 1 setting]
Adjustment of color saturation (main burst tracking in);
Min. value x 0[0], max. value x 2 [127], [1]/step
Output analog voltage value depends upon input burst signal level
[Normally 40h setting]
Main burst level tracking function control; ON [0], OFF [1] [0 setting at PIP]
When there is no main input burst signal at background display, set 1 to clear the
main burst tracking function.
Adjustment of burst gate pulse output phase for sub-screen;
[Normal setting value 1Dh]
For testing [Normally 0 setting]
For testing [Normally 0 setting]
Adjustment of color saturation; min.value [0], max.value [63], 1/step [Normally 3Fh
setting]
15h<5:0>, 16h<7:0> register default gate [Normally 1 setting]
For testing [0 setting]
8
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
SERIAL REGISTER INFORMATION (cont.)
Subaddress
Bit No.
0
1
2
15h
16h
17h
18h
19h
1Ah
9
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Reference
Register name
setting
1/1
vxs (0)
0/1
vxs (1)
0/0
vxs (2)
1/1
0/0
1/1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
1
1
1
0
vxs (3)
vxs (4)
vxs (5)
whms
test-whv
clr-mod (0)
clr-mod (1)
clr-mod (2)
clr-mod (3)
clr-mod (4)
clr-mod (5)
clr-mod (6)
clr-mod (7)
acc-level (0)
acc-level (1)
acc-level (2)
acc-level (3)
acc-level (4)
acc-level (5)
test-clamp
autosel
doutsel (0)
doutsel (1)
clocksis (0)
clocksis (1)
cdaoutsel
testyt
os
test-disp
dstry (0)
dstry (1)
dstry (2)
dstry (3)
dstry (4)
dstry (5)
dstry (6)
dstry (7)
sync (0)
sync (1)
bpfsel (0)
bpfsel (1)
ht (0)
ht (1)
ht (2)
ht (3)
Function
Setting of sub-screen sample start position (vertical):
No setting is necessary when 14h<6> is set to "0".
Adjustment setting value is effective when 14h<6> is set to "1".
[29h/2Bh (1/9 - 1/16 sizes)]
For testing [0 setting]
For testing [0 setting]
For testing [00h setting]
acc reference level: no setting is necessary when 04h<4>=0
[15h setting]
For testing; [0 setting]
For testing; [0 setting]
For testing; [00b setting]
Test clock selection; [00b setting]
For testing; [0 setting]
For testing; [0 setting]
For testing; [0 setting]
For testing; [0 setting]
Setting of color signal output burst r-y level; 256 gradations
00h (min.)→80h (center)→FFh (max.)
Selection of main internal sync separation threshold level; [11b setting]
Selection of BPF function before encoding; [00b setting]
Display information output timing cycle-adjusting parameter;
Adjustment of horizontal display effective data-starting cycle inside ICs
[7h setting]
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
SERIAL REGISTER INFORMATION (cont.)
Subaddress
1Bh
1Ch
read
1Dh
read
1Eh
read
1Fh
read
0
1
2
3
4
Reference
setting
1
1
1
1
1
dft-bl
dft-misc
dft-sg
dft-syncbst
dft-clevel
5
0
pin29osel
6
0
pin29oe
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
∗
0 or 1
0 or 1
dft-clr
imag (0)
imag (1)
imag (2)
imag (3)
iphase (0)
iphase (1)
iphase (2)
iphase (3)
iphase (4)
iphase (5)
iphase (6)
iphase (7)
iphase (8)
for test
for test
rdof
clamp-offset (0)
1
2
3
4
5
6
7
0
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
∗
0 or 1
0 or 1
clamp-offset (1)
clamp-offset (2)
clamp-offset (3)
clamp-offset (4)
clamp-offset (5)
for test
wdof
c-dac-ctrl (0)
1
2
3
4
5
6
7
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
∗
c-dac-ctrl (1)
c-dac-ctrl (2)
c-dac-ctrl (3)
c-dac-ctrl (4)
c-dac-ctrl (5)
c-dac-ctrl (6)
bw
Bit No.
Register name
Function
Register 10h<7:0>, 11h<3.0>default gate; [1 setting]
Register 11h<7:4>default gate; [1 setting]
Register 13h<7:0>, 14h<6>, 17h<7:6>default gate; [1 setting]
Register 19h<7:0>default gate; [1 setting]
Register 12h<7:0>default gate; [1 setting]
Signal selection at 29 pin output mode; fsc/4fsc [0/1] [0 setting]
Operated when adjusting oscillation frequency
29 pin output mode authorization input/output [0/1] [Normally 0 setting]
Operated when adjusting oscillation frequency
Register 16h<7:0>default gate; [1 setting]
For testing
For testing
For testing
Simplified verification of main input loss; input unavailable/available [1/0]
Clamping level information; for verification of internal operation information
Values are shown that are in proportion and corresponding to the depth of subinput information sync.
For testing
Simplified verification of sub-input loss; input unavailable/available [1/0]
Level tracking information; for verification of internal operation information
Values are shown that are in proportion and corresponding to main input burst
amplitude
Unlock information; for verification of internal operation information
10
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
104
470
Ana.
Ana.
150p
360
Ana. 103
Horizontal sync input signal (main-picture)
68p
Vertical sync input signal (main-picture)
Ana.
10µ
104
Sub-picture displaying on/off
PIP Chroma signal output
PIP Luma signal output
Luma signal input (main-picture)
Chroma input signal (main-picture)
APPLICATION EXAMPLE
Dig
Dig
10µ
15k
104
104 103
103
103
15k
103
52
50
45
40
35
30
10µ
27
M65617SP
1
5
10
15
20
26
820k
12p X1 10p
224
10µ
10µ
103
Ana.
100k
Dig5V
103
Dig5V
Ana.
104
10µ
12k
Digital GND
Ana. Analog +3.3V
power supply
103 103
CX 103
47k
Digital +3.3V
power supply
104 103 103
2k
2.2µ
300
154
1.5µ
103
12k
Dig
Digital +5V
power supply
47k
Dig5V
100k
10µ
103
Ana.
Dig
Analog GND
330
Y
C
Separate Y/C signals by using LC-tank circuit or LPF,BPF for Y/C signals level adjust.
And then mix both signals for sub-picture input video signal.
(The above external circuit processing aims at controlling white compression of
sub-screen input luminance signal and strengthening the color playback function of
sub-screen input signal in the case of weak electric field.)
11
100
560
100
10k
100
SCL
Composite video
input signal
(sub-picture)
SYNC SEP
CIRCUIT
(OPTIONAL)
SDA
Ana.5VAnalog +5V
power supply
10k
I2C BUS Clock
input signal
I2C BUS DATA
input/output
signal
Units Resistance : Ω
Capacitance : F
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
PIP TV SYSTEM BLOCK DIAGRAM
(BASIC)
Composite
Y/C
Y
Video Signal
Separation
C
Y
M65617SP
Y
C
Video
Signal
Processing
C
BLPLL
B-LD
Y/C Separated
Y
Video Signal
C
CV
Y
PIP Signal
Processing
Deflection
Unit
Yoke
C
HD
VD
(Driving Method and Operating Specification for
Serial Interface Data)
(1) Completion and start of serial transfer
If DATA (serial signal data) is changed from 'L' to 'H' when CLK
(3) Data transfer byte format (data transfer sequence)
1. Data transfer byte format in setting data to M65617SP will be
(serial clock signal) is 'H', serial transfer is completed to
described:
generate a bus-free status.
Generate a serial transfer start status before sending slave
If DATA is changed from 'H' to 'L' when CLK is 'H', serial transfer
address 24h (00100100b), and then send internal register
is started to stand by for subsequent input of CLK and DATA.
address (1 byte) followed by setting data (in the unit of 1
(2) Serial data transfer
byte). For setting data, a single transfer allows more than 1
Data, which is transferred in the unit of 1 byte, is sent
byte to be transferred. In this case, setting data is read into
sequentially from the MSB-side bit through DATA. Clock
the register that has been address-incremented one by one
waveform necessary for the transfer of 1 byte represents 9
from the internal register address sent first. (However,
times, of which address/data are transferred with the initial 8
times, and acknowledge detection performed with the remaining
address 00h will be returned to, following address 7Fh.)
2. Data transfer byte format in writing data from M65617SP will
one time. (When reading, 'H' is output to ACK at the agreement
be described:
of address in the case of address transfer, and at the completion
Prior to writing data, it is necessary to set the internal
of the 8 bit portion in the case of setting data transfer. When
address of M65617SP by reading and transferring data. Read
writing, 'H' is output to ACK at the agreement of address in the
and transfer data before performing the completion → start of
case of address transfer, and 'L' is output to ACK to detect
serial transfer. Send slave address 25h (00100101b) in
acknowledge input from master after 8 bit data is output.)
succession, and the reversed information of writing data is
DATA needs to be changed when CLK is 'L' if address/data is to
output to ACK thereafter. More than 1 byte of writing data can
be transferred. (Allowing DATA to be changed when CLK is 'H'
also be transferred. In this case as well, setting data is read
or simultaneously with the change of CLK, will cause
into the register that has been address-incremented one by
maloperation since no identification is possible of the
one from the internal register address sent first. (However,
completion and start of serial transfer.
address 00h will be returned to, following address 7FNn.)
There are no restrictions on the number of bytes of data
transferred after the start of serial transfer.
12
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
(The examples of serial byte transmission format)
(1) Reading setting data AAh into internal address 00h of M65617SP:
Transmission
Activation
Confirmation
of bus free?
(DATA='H')
yes
S
24h
A
00h
A
AAh
A D E
no
S : Operation of serial transmission start
A : Acknowledge detection
is applied
on CLK for the
release of
output state
D : Dummy clock feed for the release of
acknowledge output state
E : Operation of serial transmission completion
(2) Reading setting data FFh, 80h and EEh, individually, into internal address 04h to 06h of M65617SP:
Transmission
Activation
Confirmation
of bus free?
(DATA='H')
yes
S
24h
A
04h
A
FFh
A
80h
A
A D E
EEh
no
is applied
on CLK for the
release of
output state
(3) Writing data on internal address 00h of M65617SP [Standard reading sequence version: 46 pin " L " ]:
Transmission
Activation
Confirmation
of bus free?
(DATA='H')
yes
S
24h
A
00h
no
A’ : Bus free operation by the
is applied
on CLK for the
release of
output state
13
master (micro processor)
A D E
S
25h
A
$$h
A’
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
(4) Writing data on internal address 04h to 06h of M65617SP [Standard reading sequence version: 46 pin " H "]:
Transmission
Activation
Confirmation
of bus free?
(DATA='H')
yes
S
24h
A
04h
A D E
S
25h
A
SSh
A’’
SSh
A’’
SSh
A’
no
A’’ : Output ‘L’ operation by the
is applied
on CLK for the
release of
output state
master (micro processor)
(5) Writing data on internal address 00h of M65617SP [Expanded reading sequence version: 46 pin " H"]:
Transmission
Activation
Confirmation
of bus free?
(DATA='H')
yes
S
25h
A
00h
A
$$h
A’
no
A’ : Bus free operation by the
is applied
on CLK for the
release of
output state
master (micro processor)
(6) Writing data on the internal address 04h to 06h of M65617SP [Expanded reading sequence version: 46 pin " H"]:
Transmission
Activation
Confirmation
of bus free?
(DATA='H')
yes
S
25h
A
04h
A
SSh
A’’
SSh
A’’
SSh
A’
no
A’’ : Output ‘L’ operation by the
is applied
on CLK for the
release of
output state
master (micro processor)
14
MITSUBISHI ICs (TV)
M65617SP
PICTURE-IN-PICTURE SIGNAL PROCESSING
TIMING DIAGRAM
1
2
3
4
5
6
8
7
9
1
CLK
DATA
Bit7
(MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit7
(MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
(LSB)
ACK
Detec.
Bit7
(MSB)
ACK
_ Acknowledge
ACK
_ Readout data
15
Bit0
(LSB)
Bit7
(MSB)