MITSUBISHI ICs (TV)
M65667SP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION
The M65667SP is a NTSC PIP (Picture in Picture) signal
processing LSI, whose sub and main-picture inputs are composite
and Y/C separated signals, respectively. The built-in field memory
(96k-bit RAM) ,V-chip data slicer and analog circuitries lead the PIP
system low cost and small size.
FEATURES
•
•
•
•
•
•
Built-in 96k-bit field memory (sub-picture data storage)
Internal V-chip data slicer (for sub-picture)
Pin compatible with M65617SP
Vertical filter for sub-picture (Y signal )
Single sub-picture (selectable picture size : 1/9 , 1/16)
Sub-picture processing sepecification (1/9 size / 1/16 size) :
Quantization bits
Y, B-Y, R-Y : 6bits
Horizontal sampling 171 pixels (Y) , 28.5 pixels (B-Y, R-Y)
Vertical lines
69/ 52 lines
PIN CONFIGURATION (TOP VIEW)
AVss3 (vcxo)
1
VCXO out
2
51 Cin
VCXO in
3
50
TESTEN
FILTER
4
49
Yin
BIAS
5
48
TEST9
AVdd3 (vcxo)
6
47
Y-PIP
AVdd2 (m)
7
46
TEST8
Vin (m)
8
45
C-PIP
52
AVssf (ana)
9
44
AVdd4 (da)
10
43
C-PIPin
AVss2 (m)
11
42
AVss4 (da)
AVdd1 (s)
12
41
Y-PIPin
Vin (s)
13
40
ADJ-Ysub
Vrt (s)
14
39
Yout-sub
Vrb (s)
15
38
ADJ-Csub
AVss1 (s)
16
37
Cout-sub
RESET
17
36
DVss3
DVss1
18
35
DVdd3
DVdd1
19
34
LOCK/TEST7
BGP(s)/TEST0
20
33
VD/CSYNC/TEST6
SCK
21
32
HD/TEST5
CSYNC(s)/TEST1
22
31
SWM/TEST4
ACK
23
30
MCK
Supply voltage range........................................................3.1 to 3.5V
DATA
24
29
fsc/TEST3
Operating frequency.........................................................14.32 MHz
CLK
25
28
BGP(m)/TEST2
Operating temperature....................................................-20 to 75°C
DVss2 (ram)
26
27
DVdd2 (ram)
•
•
•
Frame (sub-picture) on/off
Built-in analog circuits :
Two 8-bit A/D converters (main and sub-picture signals)
Two 8-bit D/A converters (Y and C sub-picture signals)
Sync-tip-clump, VCXO, Analog switch ... etc.
I2C BUS control (parallel/serial control) :
PIP on/off , Sub-picture size(1/9 or 1/16), Frame on/off
(programmable luma level), PIP position (4 corners fixed
position), Picture freeze , Y delay adjustment, Chroma level, Tint,
Black level, Contrast ... etc.
APPLICATION
NTSC color TV
RECOMMENDED OPERATING CONDITION
Input voltage (CMOS interface) "H"........................V DD×0.7 to VDD V
"L".............................0 to VDD×0.3V
M65667SP
Vrt (m)
Vrb (m)
Outline 52P4B
Output current (output buffer)........................................ ±4mA (MAX)
Output load capacitance............................................20pF (MAX)
∗1
Circuit current.........................................................................160mA
NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS
pins.
∗1 : Include pin capacitance (7pF)
1
MITSUBISHI ICs (TV)
M65667SP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
BLOCK DIAGRAM
CSYNC(s)
/TEST1
SCK
BGP(s)
/TEST0
Yin
Y- PIP
Sync tip
Clamp
Cin
Vdd / Vss
for test
DATA
CLK
Bias
RAM(1H)
3
3
V-chip
data slicer
I2C
I/F
ACK
Vin(s)
Bias
A/D
8bit
Vert-filter
Sync
Sep
Phase
Select
C
Timing Gen
(Decode)
AFC
Demod
Tint
B-Y
6
R-Y
6
2
(I C)
Delay
Encode
D/A
8bit
Yout-sub
D/A
8bit
Cout-sub
Delay
Delay
MIX
SWMG
/TEST7
Y
6 B-Y
LPF
&MPY
fsc
6
6 R-Y
Vin(m)
Bias
A/D
8bit
Timing Gen
(Memory
Cont)
RAM
96Kbits
VD
/CSYNC
/TEST6
HD
/TEST5
FILTER
Lock/Free-run
via I2C
2
RESET
MCK
BGP(m)
/TEST2
fsc
/TEST3
BIAS
4fsc
Phase
Detect
Burst Data
Sampling
Y- PIPin
&
Level
Detect
ADJ-Csub
Vrt(m)
Vrb(m)
4fsc
Back Porch
Clamp
MUX
Y
B-Y
R-Y
Demux
HPLL
ADJ-Ysub
C- PIPin
6
Y/C SEP
(LPF,BPF)
2
HD
Y
Delay
Luma
Clamp
Y
Sync tip
Clamp
Vrt(m)
Vrb(m)
C- PIP
15
VCXO
Driver
VCXO
VCXO in
VCXO out
SWM
/TEST4
2
MITSUBISHI ICs (TV)
M65667SP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
DESCRIPTION OF PIN
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
ACK
I/O
GND
O
I
I
O
Vdd
Vdd
I
O
O
GND
Vdd
I
O
O
GND
I
GND
Vdd
(I/)O
I
I(/O)
O
24
DATA
I
I2C bus-data input signal
25
CLK
I
26
27
28
29
30
31
32
DVss2(ram)
DVdd2(ram)
GND
Vdd
(I/)O
I(/O)
I
(I/)O
I(/O)
I2C bus-clock input signal
Connect to digital GND
Connect to digital power supply
For test
For test (pull down to digital GND by resistor 15k Ω)
For test (connect to digital GND)
For test
Horizontal sync input signal (Positive going edge is used)
I(/O)
Vertical sync input signal (active "H")
I(/O)
Vdd
GND
O
I
O
I
I
GND
I
Vdd
O
I
O
I
I
I
I
Vss
Enable input signal to display sub picture ("H" enable)
Connect to digital power supply
Connect to digital GND
D/A output signal (Chroma signal of sub-picture)
D/A adjust for chroma signal (sub-picture)
D/A output signal (Luma signal of sub-picture)
D/A adjust for luma signal (sub-picture)
PIP luma signal re-input
Connects to analog GND
PIP chroma signal re-input
Connect to analog power supply
PIP chroma signal output
For test (connect to analog GND)
PIP luma signal output
For test (connect to analog GND)
Luma input signal (main-picture)
For test (connect to analog GND)
Chroma input signal (main-picture)
Connect to analog GND
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Name
AVss3 (VCXO)
VCXO out
VCXO in
FILTER
BIAS
AVdd3 (VCXO)
AVdd2 (m)
Vin (m)
Vrt (m)
Vrb (m)
AVss2 (m)
AVdd1 (s)
Vin (s)
Vrt (s)
Vrb (s)
AVss1 (s)
RESET
DVss1
DVdd1
BGP(s)/TEST0
SCK
CSYNC(s)/TEST1
BGP(m)/TEST2
fsc/TEST3
MCK
SWM/TEST4
HD/TEST5
VD/CSYNC
/TEST6
SWMG/TEST7
DVdd3
DVss3
Cout-sub
ADJ-Csub
Yout-sub
ADJ-Ysub
Y-PIPin
AVss4 (da)
C-PIPin
AVdd4 (da)
C-PIP
TEST8
Y-PIP
TEST9
Yin
TESTEN
Cin
AVssf (ana)
Function
Connects to analog GND
VCXO output signal
VCXO input signal
Filter
Bias
Connect to analog power supply
Connect to analog power supply
Chroma signal input (main-picture)
A/D Vref+ (main-picture)
A/D Vref- (main-picture)
Connect to analog GND
Connect to analog power supply
Composite video signal input (sub-picture)
A/D Vref+ (sub-picture)
A/D Vref- (sub-picture)
Connect to analog GND
Power on reset input signal ("L" reset)
Connect to digital GND
Connect to digital power supply
For test
For test (connect to digital GND)
For test (connect to digital GND)
Remarks
100kΩ to VDD,10µF to GND
non connect
connect to GND
pull down 15k Ω
I2C bus-data/Acknowledge output signal
non connect
pull down 15kΩ
connect to GND
non connect
pull up 15k Ω
pull up 15k Ω
connect to GND
connect to GND
3
MITSUBISHI ICs (TV)
M65667SP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
ABSOLUTE MAXIMUM RATINGS (VSS=0V)
Symbol
Limits
Min.
Max.
Parameter
VDD3
VI
VO
Supply voltage (3.3V)
Input voltage
Output voltage
IO
Output current (∗1)
Pd
Topr
Tstg
Power dissipation
Operating temperature
Storage temperature
-0.3
-0.3
-0.3
−
−
−
-20
-50
Unit
4.6
V
V
V
VDD3+0.3
VDD3+0.3
IOL=20
IOH=-26
mA
1400
75
125
mW
°C
°C
∗1: Output current per output terminal. But Pd limits all current.
DC CHARACTERISTICS (Ta=25°C, unless otherwise noted, VSS=0V)
Symbol
Parameter
VIL
VIH
VTV T+
VH
VOL
VOH
IOL
IOH
IIH
IIL
IOZL
IOZH
CI
Test conditions
Input voltage
(CMOS interface)
Input voltage schmitt trigger
(CMOS interface)
VDD=2.7V
VDD=3.6V
–
+
VDD=3.3V
Hysteresis
Output voltage
L
H
VDD=3.3V, | IO | <1µA
Output current
L
H
Input current
L
H
Output leakage current
L
H
VDD=3.0V, VOL=0.4V
VDD=3.0V, VOH=2.6V
VDD=3.6V, VI=0V
VDD=3.6V, VI=3.6V
VDD=3.6V, VO=0V
VDD=3.6V, VO=3.6V
Input pin capacitance
Output pin capacitance
Bidirectional pin capacitance
Operating current
CO
CIO
IDD
L
H
f=1MHz, VDD=0V
3.3V supply
Min.
0
2.52
0.5
1.4
0.3
−
3.25
4
−
-1
-1
-1
-1
Limits
Typ.
−
−
−
−
−
−
−
−
−
−
−
−
−
Max.
0.81
3.6
1.65
2.4
1.2
0.05
−
−
-4
1
1
1
1
−
−
−
−
7
7
7
−
15
15
15
140
Unit
V
V
V
V
V
V
V
mA
mA
µA
µA
µA
µA
pF
pF
pF
mA
TYPICAL CHARACTERISTICS
THERMAL DERATING (MAXIMUM RATING)
POWER DISSIPATION Pd (mW)
2000
1600
1490
1200
800
400
0
0
25
50
75
100
125
AMBIENT TEMPERATURE Ta (°C)
4
MITSUBISHI ICs (TV)
M65667SP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
104
470
Ana.
Ana.
150p
360
Ana. 103
Horizontal sync input signal (main-picture)
68p
Vertical sync input signal (main-picture)
Ana.
10µ
104
Sub-picture displaying on/off
PIP Chroma signal output
PIP Luma signal output
Luma signal input (main-picture)
Chroma input signal (main-picture)
APPLICATION EXAMPLE
Dig
Dig
10µ
15k
104
104 103
103
103
15k
103
52
50
45
40
35
30
10µ
27
M65667SP
1
5
10
14p
100k
15
20
26
470k
3.3µ
Digital GND
Ana. Analog +3.3V
power supply
10µ
103
Ana.
100k
Dig5V
103
Dig5V
Ana.
104
103
Ana.
12k
10µ
10µ
47k
330
104
103 103
12k
Digital +3.3V
power supply
104 103 103
2k
103
47k
51
10µ
Dig
Analog GND
100
560
100
10k
100
SCL
330
SDA
Composite video
input signal
(sub-picture)
SYNC SEP
CIRCUIT
(OPTIONAL)
10k
I2C BUS Clock
input signal
I2C BUS DATA
input /output
signal
Separate Y/C signals by using LC-tank circuit or LPF,BPF for Y/C signals level adjust.
And then mix both signals for sub-picture input video signal.
Units Resistance : Ω
Capacitance : F
5
MITSUBISHI ICs (TV)
M65667SP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
PIP TV SYSTEM BLOCK DIAGRAM
(BASIC)
Composite
Y/C
Y
Video Signal
Separation
C
Y
M65667SP
Y
C
Video
Signal
Processing
C
BLPLL
B-LD
Y/C Separated
Y
Video Signal
C
CV
Y
PIP Signal
Processing
Deflection
Unit
Yoke
C
HD
(Driving Method and Operating Specification for
Serial Interface Data)
VD
In right after the forming of serial data transmitting state, the slave
address 24h (00100100b) is transferred. Afterwards, the internal
register address (1 byte) and setting data (by 1 byte unit) are
(1) Serial data transmission completion and start
transferred successively. Several bytes of setting data can be
A low-to-high transition of the DATA (serial data) line while the CLK
handled in the one transmission. In this operation, the setting data
(serial clock) is high, that completes the serial transmission and
are written into the address register whose address is increased
makes the bus free.
one in initially transferred internal register address. (The next
A high-to-low transition of the DATA line while the CLK is high, that
address of 7Fh, it returns to 00h).
starts the serial transmission and waits for the following CLK and
2. The byte format during data reading from M65667SP are shown
DATA inputs.
as follows.
(2) Serial data transmission
Before data reading from M65667SP, whose internal address need
The data are transmitted in the most significant bit (MSB) first by
to be set by the data reading/transmitting. After the data reading/
one-byte unit on the DATA line successively. One-byte data
transmitting, the operation of "serial data transmission completion
transmission is completed by 9 clock cycles, the former 8 cycles are
and start" (described in (1)) is necessary. Continuously, the slave
for address/data and the latter one is for acknowledge detection. (In
address 25h (00100101b) is sent, and then the inverted read out
reading state, ACK is 'H' under these two conditions ; 1) the
data are available on ACK. Several bytes of writing data can be
coincidence of two address data for the address data transmission,
handled in the one transmission, too. In this operation, the setting
2) the completion of 8-bit setting data transfer. In writing state, ACK
data also are written into the address register whose address is
is 'H' with the address coincidence and ACK is 'L' for detecting
increased one in initially transferred internal register address. (The
acknowledge input from the master (micro processor) after sending
next address of 7Fh, it returns to 00h).
8-bit setting data.)
For address/data transmission, DATA must change while CLK is 'L'.
(The data change while CLK is 'H' or the simultaneous change of
CLK and DATA, that will be a false operation because of
undistinguished condition from the completion/start of serial data
transfer).
After the beginning of serial data transmission, the total number of
data bytes that can be transferred are not limited.
(3) The byte format of data transmission (The sequence of data
transmission)
1. The byte format during data setting to M65667SP are shown as
follows.
6
MITSUBISHI ICs (TV)
M65667SP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
(The examples of serial byte transmission format)
(1) The writing operation of the setting data (AAh) into M65667SP internal address of 00h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
yes
S
24h
A
00h
A
AAh
A D E
no
S : Operation of serial transmission start
A : Acknowledge detection
is applied
on CLk for the
release of
output state
D : Dummy clock feed for the release of
acknowledge output state
E : Operation of serial transmission completion
(2) The writing operation of the setting data (FFh, 80h, EEh) into M65667SP internal address of 04h to 06h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
yes
S
24h
A
04h
A
FFh
A
80h
A
A D E
EEh
no
is applied
on CLk for the
release of
output state
(3) The reading operation of the setting data from M65667SP internal address of 00h
Transmission
Activation
Confirmation
of bus free
(DATA='H')
yes
S
24h
A
00h
A D E
S
25h
A
$$h
A’
no
A’ : Bus free operation by the
is applied
on CLk for the
release of
output state
master (micro processor)
7
MITSUBISHI ICs (TV)
M65667SP
PRELIMINARY
Notice:This is not a final specification.
Some parametric limits are subject to change.
PICTURE-IN-PICTURE SIGNAL PROCESSING
(4) The reading operation of the setting data from M65667SP internal address of 04h to 06h
Confirmation
of bus free
(DATA='H')
Transmission
Activation
yes
S
24h
A
04h
A D E
S
25h
A
SSh
A’’
SSh
A’’
SSh
A’
no
A’’ : Output ‘L’ operation by the
is applied
on CLk for the
release of
output state
master (micro processor)
TIMING DIAGRAM
1
2
3
4
5
6
8
7
9
1
CLK
DATA
Bit7
(MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit7
(MSB)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
(LSB)
ACK
Detec.
Bit7
(MSB)
ACK
_ Acknowledge
ACK
_ Readout data
Bit0
(LSB)
Bit7
(MSB)
8