MITSUBISHI DIGITAL TV ICs PRELIMINARY M65669SP/FP Notice ; This is not the final specification. Some of information in this document are subject to changes. PICTURE-IN-PICTURE SIGNAL PROCESSING V3.1 DESCRIPTION APPLICATION The M65669SP/FP is a PIP (Picture in Picture) signal processing LSI, whose sub-picture input is composite signal for NTSC, PAL-M, and PAL-N. The built-in field memory (144k-bit RAM) , V-chip data slicer and analog circuitries lead the high quality PIP system low cost and small size. NTSC, PAL-M, PAL-N color TV RECOMMENDED OPERATING CONDITIONS Supply voltage range ---------------------------------- 3.1 ~ 3.5 V Operating frequency --------------------------------- 14.32 MHz Operating temperature --------------------------------- -10 ~ 70 deg. Input voltage (CMOS interface) "H" ----- VDD x 0.7 ~ VDD V "L" ----0 ~ VDD x 0.3 V Output current ( output buffer ) ------------------- 4 mA ( MAX ) Output load capacitance --------------------------- 20 pF ( MAX ) *1 Circuit current ---------------------------------------- mA FEATURES * Built-in 144k-bit field memory ( sub-picture data storage) * Internal V-chip data slicer (for sub-picture) NOTICE: Connect a 0.1µF or larger capacitor between VDD and VSS pins. * Vertical filter for sub-picture ( Y signal ) *1 : Include pin capacitance ( 7 pF ) * Single sub-picture ( selectable picture size : 1/9 , 1/16 ) * Sub-picture processing specification ( 1/9 , 1/16 size) : Quantization bits Y, B-Y, R-Y : 6 bits Horizontal sampling 229 pixels ( Y ) , 57 pixels ( B-Y, R-Y ) Vertical lines 69/ 52 lines * Frame ( sub-picture ) on/off * Built-in analog circuits : One 8-bit A/D converter ( for sub-picture signal) Three 8-bit D/A converters ( for Y, U and V of sub-picture ) Block diagram & Application examples Sync-tip-clamp, VCXO ... etc.. * IIC BUS control ( parallel/serial control) : Shown next pages PIP on/off , Frame on/off ( programmable luma level), Sub-picture size ( 1/9, 1/16 ), PIP position ( free position ), Picture freeze , Y delay adjustment, Chroma level, Tint, Black level, Contrast ...etc.. PIN CONFIGURATION (TOP VIEW) AVss(ana) SWM 1 42 ACK 2 41 SDATA SCLK 3 40 ADJ_Usub Vdd(da) 4 39 YOUT DVdd DVss 5 38 ADJ_Ysub 6 37 UOUT BGPS SCK 7 36 ADJ_Vsub 8 35 VOUT BGPM FSC TEST5 TEST6 9 34 TESTEN 10 33 11 32 VD HD 12 31 AVss(vcxo) SWMG RESET DVdd 13 30 X'tal(P-N) 14 29 X'tal(P-M) 15 28 DVss 16 27 X'tal(NT) BIAS MCK 17 26 Filter CSYNCS 18 25 AVdd(vcxo) AVss(ad) Vrb 19 24 AVdd(ad) 20 23 Vin(Sync sepa.) Vrt 21 22 Vin(ad) Outline 42 Pin SDIP Package (M65669SP) Outline 0.8mm pitch 42 Pin SOP Package (M65669FP) ( 1 / 15 ) MITSUBISHI DIGITAL TV ICs PRELIMINARY Notice ; This is not the final specification. Some of information in this document are subject to changes. M65669SP/FP V3.1 PICTURE-IN-PICTURE SIGNAL PROCESSING BLOCK DIAGRAM Y OUTPUT U OUTPUT V OUTPUT PIP SW Sub picture Main HD SCL Main VD ( 2 / 15 ) SDA MITSUBISHI DIGITAL TV ICs PRELIMINARY M65669SP/FP Notice ; This is not the final specification. Some of information in this document are subject to changes. PICTURE-IN-PICTURE SIGNAL PROCESSING V3.1 ABSOLUTE MAXIMUM RATINGS Symbol (VSS=0V) Parameter Limits Conditions Min. Unit Max. VDD3 Supply voltage (3.3V) -0.3 4.6 V VI Input voltage -0.3 VDD3+0.3 V VO Output voltage -0.3 VDD3+0.3 V IO Output current (*1) IOH = -4 IOL = 4 mA PD Power dissipation - 1200 mW Topr Operating temperature -10 70 deg. Tstg Storage temperature -50 125 deg. (*1) Output current per output terminal. But Pd limits all current. TYPICAL CHARACTERISTICS THERMAL DERATING (MAXIMUM RATING) 2000 1600 1200 800 400 0 0 25 50 7075 100 125 AMBIENT TEMPERATURE Ta (deg.) ( 3 / 15 ) MITSUBISHI DIGITAL TV ICs PRELIMINARY Notice ; This is not the final specification. Some of information in this document are subject to changes. M65669SP/FP PICTURE-IN-PICTURE SIGNAL PROCESSING V3.1 DC CHARACTERISTICS (VSS=0V) (Ta = 25 deg. unless otherwise noted) Symbol Limits Condition Parameter Unit Min. Typ. Max. VIL Input voltage L VDD = 2.7V 0 - 0.81 VIH (CMOS interface) H VDD = 3.6V 2.52 - 3.6 VT- Input voltage schmitt trigger - 0.5 - 1.65 VT+ (CMOS interface) + 1.4 - 2.4 0.3 - - 1.2 - 0.05 3.25 - - Hysteresis VH VOL L CMOS output voltage VDD = 3.3V, |IO| = 1µA H VOH IOL CMOS output current IOH IIH Input current IIL IOZL VDD = 3.3V L VDD = 3.0V, VOL = 0.4V 4 - - H VDD = 3.0V, VOH = 2.6V - - -4 L VDD = 3.6V, VI = 0V -1 - 1 H VDD = 3.6V, VI = 3.6V -1 - 1 L VDD = 3.6V, VO = 0V -1 - 1 H VDD = 3.6V, VO = 3.6V -1 - 1 - 7 15 - 7 15 15 Output leakage current IOZH CI Input pin capacitance CO Output pin capacitance CIO Bidirectional pin capacitance - 7 IDD Operating current - 180 f = 1MHz, VDD = 0V 3.3V supply ( 4 / 15 ) V V V mA - µA µA pF mA MITSUBISHI DIGITAL TV ICs PRELIMINARY Notice ; This is not the final specification. Some of information in this document are subject to changes. M65669SP/FP V3.1 PICTURE-IN-PICTURE SIGNAL PROCESSING PIN DESCRIPTION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Name I/O Function Remarks CMOS output SWM PIP switch output CMOS output I2C SDA output (for high load SDA line use only) ACK CMOS I/O (5V)*1 I2C SDA input/output SDATA SCLK CMOS input (5V)*1 I2C SCL input DVdd1 Digital Vdd Vdd for digital part DVss1 Digital Vss Vss for digital part BGPS Test output CMOS output Test input SCK connect to GND CMOS input BGPM Test output CMOS output connect to GND FSC CMOS input Test input Test input connect to GND CMOS input TEST5 TEST6 Test input CMOS input connect to GND SWMG CMOS input connect to Vdd Power on reset input RESET CMOS input Digital Vdd DVdd2 Vdd for digital part Digital Vss Vss for digital part DVss2 Test input CMOS input MCK connect to GND Sub picture external C-sync input CSYNCS CMOS input Analog Vss AVss (ADC) Vss for internal ADC Analog Low level reference voltage output of ADC VRB VRT High level reference voltage output of ADC Analog Analog VIN (ADC) Sub picture input of ADC Sub picture input of sync sep. for sub picture VIN (Sync Sep.) Analog Analog Vdd Vdd for internal ADC AVdd (ADC) Vdd for VCXO AVdd (VCXO) Analog Vdd Analog FILTER VCXO filter voltage connection VXCO bias voltage connection Analog BIAS Analog X'tal (NTSC) X'tal of NTSC connection X'tal (PAL-M) Analog X'tal of PAL-M connection Analog X'tal (PAL-N) X'tal of PAL-N connection Vss for VCXO AVss (VCXO) Analog Vss CMOS input (5V)*1 Main picture HD input HD CMOS input (5V)*1 MAIN picture VD input VD connect to GND TESTEN Test input CMOS input Analog Sub picture V or B output VOUT Analog Referece voltage connection of DAC of V ADJ_Vsub Analog Sub picture U or G output UOUT Analog ADJ_Ysub Referece voltage connection of DAC of Y Sub picture Y or R output Analog YOUT Vdd for DAC Analog Vdd AVdd (DAC) Analog Referece voltage connection of DAC of U ADJ_Usub AVss (sub) Analog Vss Vss for substrate *1 ) (5V)means 5V I/F torelant ( 5 / 15 ) MITSUBISHI DIGITAL TV ICs PRELIMINARY M65669SP/FP Notice ; This is not the final specification. Some of information in this document are subject to changes. PICTURE-IN-PICTURE SIGNAL PROCESSING V3.1 Dig. Digital +3.3V power supply BASIC APPLICATION EXAMPLE Digital GND < NTSC only application example > 0.1µ Sub Composite video input Analog GND 22 21 23 20 24 19 25 18 18 pin input when CSYNC of sub picture is fed from external 3.3V 0.033µ 26 17 0V 0.22µ 27 16 0.01µ 0.5V(max) Ana . 0.01µ Analog +3.3V power supply 1V(max) 0.22µ 2K 820K 0.01µ X1 X1 : 14.31818MHz 28 15 29 14 30 13 31 12 Main HD input 32 11 Main VD input 33 10 34 9 35 8 36 7 37 6 38 5 39 4 40 3 41 2 42 1 12~36p 5V (3.3V recommended) 0V 5V (3.3V recommended) 0V 1K 330 Ana. 10µ 360 PIP V or B output Ana. 0.7V (typ) PIP U or G output 360 0.01µ Ana. 0.7V (typ) PIP Y or R output 360 0.01µ 0.01µ 3.3V IIC BUS Clock input IIC BUS DATA input /output PIP SW output 0V < NTSC / PAL-M / PAL-N application example > 560p 0.01µ 0.1µ Sub Composite video input 22 21 23 20 24 19 25 18 18 pin input when CSYNC of sub picture is fed from external 3.3V 26 17 0V 27 16 28 15 29 14 30 13 31 12 Main HD input 32 11 Main VD input 33 10 34 9 35 8 36 7 37 6 38 5 39 4 IIC BUS Clock input 40 3 IIC BUS DATA input /output 41 2 42 1 0.5V(max) 1M 1V(max) 0.01µ 2K 0.22µ 2K 820K 0.033µ 0.22µ X1 : 14.31818MHz X2 : 14.30244MHz X3 : 14.328MHz 5V (3.3V recommended) 0V 5V (3.3V recommended) 0V X1 12~36p X2 330 12~36p X3 330 12~36p PIP V or B output 330 0.01µ 1K 10µ Ana. 360 Ana. 0.7V (typ) PIP U or G output 360 0.01µ Ana. 0.7V (typ) PIP Y or R output 360 0.01µ 0.01µ 3.3V 0V PIP SW output ( 6 / 15 ) MITSUBISHI DIGITAL TV ICs PRELIMINARY M65669SP/FP Notice ; This is not the final specification. Some of information in this document are subject to changes. PICTURE-IN-PICTURE SIGNAL PROCESSING V3.1 M65662FP TV SYSTEM BLOCK DIARGRAM <BASIC > Composite Video Signal Y Y Y/C Separation C C R Y Video Signal Processing U Matrix B V M65669SP/FP CV Y C Y/C Separated Video Signal Y PIP Signal U Processing V G Deflection Unit HD Yoke VD SWM Y Y/C Separation C Composite Video Signal Y R C Video Signal Processing M65669SP/FP Y/C Separated Video Signal Y C CV R G PIP Signal Processing B SWM ( 7 / 15 ) G B Deflection Unit HD VD Yoke MITSUBISHI DIGITAL TV ICs PRELIMINARY Notice ; This is not the final specification. Some of information in this document are subject to changes. M65669SP/FP V3.1 PICTURE-IN-PICTURE SIGNAL PROCESSING Internal register information (preliminary) address bit 00h <7> <6> <5> <4> <3> <2> <1> <0> 01h <7:0> 02h <7:0> 03h <7> <6:0> 04h <7> <6:0> 05h <7> <6> <5:0> 06h <7:6> 07h 08h 09h 0Ah 0Bh <5:4> <3:0> <7:6> <5:0> <7:4> <3:0> <7:5> <4:0> <7> <6:4> <3:0> <7:4> <3:0> 0Ch <7> <6> <5:4> <3> <2> <1> <0> 0Dh <7:6> <5:4> <3> <2:0> 0Eh <7> <6> <5:0> 0Fh <7> <6> <5> <4> <3> <2> <1> <0> symbol DISP SIZE_V SIZE_H WEN BGC BGCS FREE_RUN RVS VXA<7:0> HXA<7:0> DECODE CONTRAST<6:0> KILLER U_DAC<6:0> GRC YUVN_RGB_SEL TINT<5:0> EXT_SC_SEL<1:0> remarks 0 1 Sub picture display : [0] off, [1] on 0 0 Sub picture vertical size : [0] 1/9, [1] 1/16 0 0 Sub picture horizontal size : [0] 1/9, [1] 1/16 0 1 Sub picture : [0] Still, [1] Moving 0 0 Back ground display : [0] off, [1] on 0 0 Sub picture mute : [0] off, [1] on 1 0 VCXO ocsilation : [0] Lock, [1] Free run 0 HD / VD input synchronous mode selection : [0] sync., [1] async. 0 FFh 20h Sub picture vertical position FFh 20h Sub picture horizontal position 0 0 Sub picture color decoder reset : [1] reset 33h 32h Sub picture Y or R DAC output amplitude control 0 0 Sub picture color killer : [0] enable, [1] disable 33h 32h Sub picture U or G DAC output amplitude control 1 1 Frame display : [0] off, [1] on 0 0 PIP output mode selection : [0] YUV, [1] RGB 00h 00h Sub picture tint control 0h 0h Sub picture C-Sync sep. input selection : [0] Digital, [1] 23 pin input, [2] external (18 pin input), [3] Int. analog Sub picture digital sync sep.threshold setting 0 0 3h Ah Sub picture display timing adjust 2h Ext. port setting (7 pin) : [0or1] Sub BGP, [2]"0" output, [3]"1" output 2h 0Eh 0Eh Sub picture BGP position setting 2h 2h Main/Sub switch delay control 7h Fh Sub picture Y/C delay adjust 0h 0h Back ground U level setting 0Fh 0Fh Sub picture Y bright control 0 0 V-chip decode mode : [0] off, [1] on 0h 0h Back ground V level setting Ch Ch Back ground Y level setting 0h 0h Sub picture V pedestal level (2's comp) 0h 0h Sub picture U pedestal level (2's comp) Reset val.1/9 ex. DCONT<1:0> HT<3:0> EXPORT<1:0> BG_START<5:0> ADJ<3:0> YDL<3:0> BGBY<2:0> Y_OFFSET<4:0> VCHIP_ONLY BGRY<2:0> BGY<3:0> PEDESTV<3:0> PEDESTU<3:0> UV_FILTER_OFF 0 SET_ACC 0 SYSTEM_MODE<1:0> 0h SET_SIZE 0 SET_VCHIP 0 INV_UV 0 CROSS_SEL 0 SYNC_DELAY<1:0> 0h MVP_SEL<1:0> 0h C_GAIN_SEL 0 INVLEVEL<2:0> 0h BITSEL 0 AFCBITSEL 0 ACC_LEVEL<5:0> 15h AUTO_ENABLE 0 BURST_CLOCK_MODE 0 PALN_ENABLE 0 INV_WFF 0 INV_RFF 0 ERRSEL 0 RFF_FIX 0 AUTO_RFF_FIX 0 0 0 0h 0 0 0 0 Sub picture U, V output filter : [0]on, [1]off Address 0Dh, 0Eh setting mode : [0]default, [1] enable to set System : [0]NTSC , [1]PAL-M, [2]PAL-N, [3] N.A. Address 11h, 12h, 13h, 14h setting mode : [0]default, [1] enable to set Address 15h, 16h, 17h setting mode : [0]default , [1] enable to set Invert U, V output value : [0] normal, [1] invert Sub picture read mode : [0] pixel based, [1] H based Sub picture sync.delay control Sub picture decoder macro vision mode selection Sub picture chroma : [0] x1, [1] x2 Sub picture decoder macro vision mode threshold Sub picture Y clamp time constant : [0] x2, [1] x1 Sub picture AFC time constant : [0] x2, [1] x1 Sub picture color decoder amplitude System automatic judgment : [0] off, [1] on VCXO mode selection : [0] 1H based, [1] 2H based Main picture PAL-N : [0] enable, [1] disable Invert sub picture field definition : [0] normal, [1] invert Invert main picture field definition : [0] normal, [1] invert for test : 0 set only Main picture field fix : [0] not fix, [1]fix Automatic 50/60Hz Judgement : [0] enable, [1] disable ( 8 / 15 ) MITSUBISHI DIGITAL TV ICs PRELIMINARY M65669SP/FP Notice ; This is not the final specification. Some of information in this document are subject to changes. V3.1 PICTURE-IN-PICTURE SIGNAL PROCESSING Internal register information (continuing) (preliminary) address bit 10h <7> <6> <5:0> 11h <7> <6:0> 12h <7:0> 13h <7:2> <1:0> 14h <7:6> symbol INVDECODE AVERAGE PALRY<5:0> WDOF_KILLER_ON HYA<6:0> VYA<7:0> HX<5:0> HP<1:0> MVC<1:0> <5:0> 15h <7> <6> <5> <4:0> 16h <7:0> VXS<5:0> PLUS LINE_NUM<4:0> STB_DLY<7:0> remarks Sub picture decoder mode : [0] NTSC, [1] PAL 0 0 Sub picture decoder mode : [0] 1H based, [1] 2H based 0 0 00h 00h Threshold control of ident judgment of sub picture decoder Sub picture killer on when its vert. sync lost : [0] on, [1] off 0 Sub picture horizontal display pixel 37h Sub picture vertical display line number 44h Sub picture horizontal capture position (coarse) 1Eh Sub picture horizontal capture position (fine) 0h Sub picture C-sync input mask period : 0h 0] 48us, [1] 44us, [2] 53us, [3] off Sub picture sample start line 29h for test : 0 set only 0 for test : 0 set only 0 for test : 0 set only 0 Data slicer line selection 11h Data slicer start bit detection parameter 40h Reset val. 1/9 ex. 17h <7:0> L_LEVEL<7:0> 82h Data slicer data slice parameter 18h <7> <6:4> <3:0> 19h <7:5> 0 0h Ch Frame data independent control : [0] disable, [1] enable Frame data independent B-Y data setting Frame data independent Y data setting Frame data independent R-Y data setting EDGE_ON BGBY_EDGE<2:0> BGY_EDGE<3:0> BGRY_EDGE<2:0> <4> HPFOFF <3:0> FREE_RUN_ADJ<3:0> 1Ah <7:0> SUB_PALM_JDGE<7:0> 1Bh <7:6> NO_BST_LEVEL <5:4> BW_DET_LEVEL <3:0> HADJ<3:0> 1Ch <7> PINOE <6:0> V_DAC<6:0> 1Dh <7:0> PINOE<7:0> 1Eh <7:0> 1Fh <7:6> <5> <4> <3> <2> <1> <0> 20h <7:6> <5> <4> <3> <2> <1> <0> 21h <7:0> 22h <7:0> 23h <7:0> SYSTEM_STATE<1:0> MAIN_PALN SUB_UNLOCK SUB_PALN RDOF MAIN_BW WDOF NOISE<1:0> -WDOF EDS_ACK2 EDS_ACK1 SIGNAL_OK READ_REQB READ_REQA PDB<15:8> PDB<7:0> PDA<15:8> 24h <7:0> PDA<7:0> 0h 0 0h 0h 0h 0h 0h 0 0h FFh Sub picture Y output HPF : [0]on, [1]off Frequency adjustment control when free run mode (2's comp) Parameter setting for PAL-M judgment for test for test Parameter setting for PAL-M judgment for test Sub picture V or B DAC output amplitude control for test No assignment System state : [0] NTSC, [1] PAL-M, [2] PAL-N, [3]N.A. (Read only) Main is : [0] not PAL-N, [1] PAL-N (Read only) VCXO is : [0] Lock, [1] Unlock (Read only) Sub is : [0] not PAL-N, [1] PAL-N (Read only) Main picture vertical sync is : [0] present, [1] not present (Read only) Test use (Read only) Sub picture vertical sync is : [0] present, [1] not present (Read only) Test use (Read only) Sub picture vertical sync detection (Read only) EDS data flag of even field : [0] no EDS, [1] EDS (Read only) EDS data flag of odd field : [0] no EDS, [1] EDS (Read only) Test use (Read only) Read request of even field : [0] no, [1] requesting (Read only) Read request of odd field : [0] no, [1] requesting (Read only) Even field Sliced data upper 8 bit (Read only) Even field Sliced data lower 8 bit (Read only) Odd field Sliced data upper 8 bit (Read only) Odd field Sliced data lower 8 bit (Read only) ( 9 / 15 ) MITSUBISHI DIGITAL TV ICs PRELIMINARY Notice ; This is not the final specification. Some of information in this document are subject to changes. M65669SP/FP V3.1 PICTURE-IN-PICTURE SIGNAL PROCESSING <Driving Method and Operating Specification for Serial Interface Data> (1) Serial data transmission completion and start A low-to-high transition of the DATA (serial data) line while the CLK (serial clock) is high, that completes the serial transmission and makes the bus free. A high-to-low transition of the DATA line while the CLK is high, that starts the serial transmission and waits for the following CLK and DATA inputs. (2) Serial data transmission The data are transmitted in the most significant bit (MSB) first by one-byte unit on the DATA line successively. One-byte data transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter one is for acknowledge detection. (In reading state, ACK is 'H' under these two conditions ; 1) the coincidence of two address data for the address data transmission, 2) the completion of 8-bit setting data transfer. In writing state, ACK is 'H' with the address coincidence and ACK is 'L' for detecting acknowledge input from the master (micro processor) after sending 8-bit setting data.) For address/data transmission, DATA must change while CLK is 'L'. (The data change while CLK is 'H' or the simultaneous change of CLK and DATA, that will be a false operation because of undistinguished condition from the completion/start of serial data transfer). After the beginning of serial data transmission, the total number of data bytes that can be transferred are not limited. (3) The byte format of data transmission (The sequence of data transmission) a. The byte format during data setting to M65669FP are shown as follows. In right after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred. Afterwards, the internal register address (1 byte) and setting data (by 1 byte unit) are transferred successively. Several bytes of setting data can be handled in the one transmission. In this operation, the setting data are written into the address register whose address is increased one in initially transferred internal register address. b. The byte format during data reading from M65669FP are shown as follows. Before data reading from M65669FP, whose internal address need to be set by the data reading/transmitting. After the data reading/transmitting, the operation of "serial data transmission completion and start" (described in (1)) is necessary. Continuously, the slave address 25h (00100101b) is sent, and then the inverted read out data are available on ACK. Several bytes of writing data can be handled in the one transmission, too. In this operation, the setting data also are written into the address register whose address is increased one in initially transferred internal register address. ( 10 / 15 ) MITSUBISHI DIGITAL TV ICs PRELIMINARY M65669SP/FP Notice ; This is not the final specification. Some of information in this document are subject to changes. V3.1 PICTURE-IN-PICTURE SIGNAL PROCESSING <The examples of serial byte transmission format> (1) The writing operation of the setting data (AAh) into M65669FP internal address of 00h Transmission Activation Confirmation of bus free (DATA='H') yes S 24h A 00h A AAh A D E no S : Operation of serial transmission start A : Acknowledge detection D : Dummy clock feed for the release of acknowledge output state E : Operation of serial transmission completion is applied on CLk for the release of output state (2) The writing operation of the setting data (FFh, 80h, EEh) into M65669FP internal address of 04h ~ 06h Transmission Activation Confirmation of bus free (DATA='H') yes S 24h A 04h A FFh A 80h A EEh A D E no is applied on CLk for the release of output state (3) The reading operation of the setting data from M65669FP internal address of 00h Transmission Activation Confirmation of bus free (DATA='H') yes S 24h A 00h A D E S 25h A $$h A' no is applied on CLk for the release of output state A' : Bus free operation by the master (micro processor) ( 11 / 15 ) MITSUBISHI DIGITAL TV ICs PRELIMINARY M65669SP/FP Notice ; This is not the final specification. Some of information in this document are subject to changes. PICTURE-IN-PICTURE SIGNAL PROCESSING V3.1 (4) The reading operation of the setting data from M65669FP internal address of 04h ~ 06h Transmission Activation Confirmation of bus free (DATA='H') yes S 24h A 04h A D E S 25h A $$h A" $$h A" $$h A' no is applied on CLk for the release of output state A" : Output 'L' operation by the master (micro processor) <Timing Diagram> 1 2 3 4 5 6 7 8 9 1 Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) ACK Detec. Bit7 (MSB) Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) Bit7 (MSB) Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) Bit7 (MSB) SCL (4 pin) SDA (3 pin) SDA (Read data) (3 pin) ACK (2 pin) ACK (Read data) (2 pin) (12 / 15 ) MITSUBISHI DIGITAL TV ICs PRELIMINARY Notice ; This is not the final specification. Some of information in this document are subject to changes. M65669SP/FP V3.1 PICTURE-IN-PICTURE SIGNAL PROCESSING Internal register information (preliminary : functional reference only, address and bit definition NOT fixed) 00h <7> <6> <5> <4> <3> <2> <1> <0> 01h <7:0> 02h <7:0> 03h <7> <6:0> 04h <7> <6:0> 05h <7> <6> <5:0> 06h <7:6> 07h 08h 09h 0Ah 0Bh <5:4> <3:0> <7:6> <5:0> <7:4> <3:0> <7:5> <4:0> <7> <6:4> <3:0> <7:4> <3:0> 0Ch <7> <6> <5:4> <3> <2> <1> <0> 0Dh <7:6> <5:4> <3> <2:0> 0Eh <7> <6> <5:0> 0Fh <7> <6> <5> <4> <3> <2> <1:0> symbol DISP SIZE_V SIZE_H WEN BGC BGCS FREE_RUN RVS VXA<7:0> HXA<7:0> DECODE CONTRAST<6:0> KILLER COLOR_SAT<6:0> GRC YUVN_RGB_SEL TINT<5:0> EXT_SC_SEL<1:0> remarks Sub picture display : [0] off , [1] on Sub picture vertical size : [0] 1/9, [1] 1/16 Sub picture horizontal size : [0] 1/9, [1] 1/16 Sub picture : [0] Still, [1] Moving Back ground display : [0] off, [1] on Sub picture mute : [0] off, [1] on VCXO ocsilation : [0] Lock, [1] Free run HD / VD input synchronous mode selection : [0] sync., [1] async. Sub picture vertical position Sub picture horizontal position Sub picture color decoder reset : [1] reset Sub picture Y DAC output amplitude control Sub picture color killer : [0] enable, [1] disable Sub picture U and V DAC output amplitude control Frame display : [0] off , [1] on PIP output mode selection : [0] YUV , [1] RGB Sub picture tint control Sub picture C-Sync sep. input selection : [0] Digital, [1] 23 pin input, [2] external, [3] Int. analog DCONT<1:0> HT<3:0> EXPORT<1:0> BG_START<5:0> ADJ<3:0> YDL<3:0> BGBY<2:0> Y_OFFSET<4:0> VCHIP_ONLY BGRY<2:0> BGY<3:0> pedestu<3:0> pedestv<3:0> SIZE_Q SET_ACC SYSTEM_MODE<1:0> SET_SIZE SET_VCHIP INV_UV CROSS_SEL SYNC_DELAY<1:0> MVP_SEL<1:0> C_GAIN_SEL INVLEVEL<2:0> BITSEL AFCBITSEL ACC_LEVEL<5:0> AUTO_ENABLE BURST_CLOCK_MODE EVENUPRA INV_WFF INV_RFF RVHS - Sub picture digital sync sep.threshold setting Sub picture display timing adjust Ext. port setting (7 pin) : [0or1]—, [2]"0" output, [3]"1" output Sub picture BGP position setting Main/Sub switch delay control Sub picture Y/C delay adjust Back ground U level setting Sub picture Y bright control V-chip decode mode : [0] on , [1] off Back ground V level setting Back ground Y level setting Sub picture U pedestal level Sub picture V pedestal level Sub picture vertical size : [0] 1/9 or 1/16, [1] 1/4 Address 0Dh, 0Ch setting mode : [0]defualt , [1] enable set System : [0]NTSC, [1]NTSC/PAL-M, [2]NTSC/PAL-N, [3]All Address 11h, 12h, 13h setting mode : [0]defualt , [1] enable set Address 15h, 16h, 17h setting mode : [0]defualt , [1] enable set Invert U, V outtput value : [0] off, [1] on Sub picture read mode : [0] pixel based, [1] H based Sub picture sync.delay control Sub picture decoder macro vision mode selection Sub picture chroma : [0] x1, [1] x2 Sub picture decoder macro vision mode threshold Sub picture Y clamp time constant : [0] x2, [1] x1 Sub picture AFC time constant : [0] x2, [1] x1 Sub picture color decoder amplitude System automatic judgement : [0] off , [1] on VCXO mode selection : [0] 1H based, [1] 2H based Invert sub picture display beginnig line field : [0] normal, [1] invert Invert sub picture field definition : [0] normal, [1] invert Invert main picture field definition : [0] normal, [1] invert for test : [0] off, [1] on No assgnment ( 13 / 15 ) MITSUBISHI DIGITAL TV ICs PRELIMINARY Notice ; This is not the final specification. Some of information in this document are subject to changes. M65669SP/FP V3.1 PICTURE-IN-PICTURE SIGNAL PROCESSING Internal register information (preliminary : functional reference only, address and bit definition NOT fixed) 10h <7> <6> <5:0> 11h <7> <6:0> 12h <7:0> 13h <7:2> <1:0> 14h <7:6> INVDECODE AVERAGE PALRY<5:0> WDOF_KILLER_ON HYA<6:0> VYA<7:0> HX<5:0> HP<1:0> MVC<1:0> <5:0> 15h <7> <6> <5> <4:0> 16h <7:0> VXS<5:0> PLUS SW_TESTEN LINE_NUM<4:0> STB_DLY<7:0> 17h <7:0> L_LEVEL<7:0> 18h <7> <6:4> <3:0> 19h <7:5> EDGE_ON BGBY_EDGE<2:0> BGY_EDGE<3:0> BGRY_EDGE<2:0> <4> HPFOFF <3:0> FREE_RUN_ADJ<3:0> 0 0 0 11h 40h Sub picture decoder mode : [0] NTSC, [1] PAL Sub picture decoder mode : [0] 1H based , [1] 2H based Threshold contorol of ident judgement of sub picture decoder Sub picture killer on when its vert. sync lost : [0] on, [1] off Sub picture horizontal display pixel Sub picture vertical display line number Sub picture horizontal capture position Sub picture horizontal capture position Sub picture C-sync input mask period : [0] 48us, [1] 44us, [2] 53us, [3] off Sub picture sample start line Test use Test use Test use Data slicer line selection Data slicer start bit detection parameter 82h Data slicer data slice parameter 38h/29h 44h/33h Frame data independent control : [0] disable, [1] enable Frame data independent B-Y data setting Frame data independent Y data setting Frame data independent R-Y data setting Sub picture Y output HPF : [0]on, [1]off Frequency adjustment control when free run mode 1Ah <7:0> SUB_PALM_JUDGE<7:0> 1Bh <7:6> NO_BST_LEVEL <5:4> BW_DET_LEVEL <3:0> HADJ<3:0> 1Ch <7> PINOE <6> BGP_M_SEL <5:0> BST_BY<3:0> 1Dh <7:0> PINOE<7:0> 1Eh <7:0> - Parameter setting for PAL-M judgement for test for test for test for test for test for test for test No assgnment 1Fh <7:6> <5> <4> <3> <2> <1> <0> 20h <7:6> <5> <4> <3> <2> <1> <0> 21h <7:0> 22h <7:0> 23h <7:0> System state : [0] NTSC, [1] NTSC, [2] PAL-N, [3]N.A. (Read only) Main is : [0] not PAL-N , [1] PAL-N(Read only) VCXO is : [0] Lock , [1] un-Lock(Read only) Sub is : [0] not PAL-N , [1] PAL-N(Read only) Main picture vertical sync is : [0] not present , [1] present(Read only) Test use (Read only) Sub picture vertical sync is : [0] not present , [1] present (Read only) Test use (Read only) Sub picture vertical sync detection (Read only) EDS data flag of even field (Read only) : [0] no EDS, [1] EDS EDS data flag of odd field (Read only) : [0] no EDS, [1] EDS Test use (Read only) Read request of even field (Read only) : [0] no, [1] request Read request of odd field (Read only) : [0] no, [1] request Even field Sliced data upper 8 bit (Read only) Even field Sliced data lower 8 bit (Read only) Odd field Sliced data upper 8 bit (Read only) SYSTEM_STATE<1:0> MAIN_PALN SUB_UNLOCK SUB_PALN RDOF MAIN_BW WDOF NOISE<1:0> WDOF EDS_ACK2 EDS_ACK1 SIGNAL_OK READ_REQB READ_REQA PDB<15:8> PDB<7:0> PDA<15:8> 24h <7:0> PDA<7:0> Odd field Sliced data lower 8 bit (Read only) ( 14 / 15 ) MITSUBISHI DIGITAL TV ICs PRELIMINARY Notice ; This is not the final specification. Some of information in this document are subject to changes. M65669SP/FP PICTURE-IN-PICTURE SIGNAL PROCESSING V3.1 Internal register information (preliminary : functional reference only, address and bit definition NOT fixed) symbol 25h <7:0> FREQ_DIFF_TERM<7:0> 30h <7:6> WPROC<2:1> TEST_WHV <5> TI_DELAY90 <4> TI_VFSC <3> <2> TI_KVFLT <1> TI_YPROC SWAP <0> ACK_OUT_SEL 31h <7> SEL_PD_OUT <6> DOFC <5> TI_ZEC <4> TI_SPRF <3> <2> TEST_YT <1> TI_CPROCS TI_MCSEQ <0> TEST_SPRF96K 32h <7> C_DAC_CTRL <6> YDAOUTSEL <5> DISADCLK <4> INV_PROBE_MSB <3> <2> DISLOGICCLK <1> CDAOUTSEL TEST_RH <0> 33h <7:0> MAN_SEL<7:0> 34h <7:6> ADCCLKSEL<1:0> RHMS <5> OUT_SEL <4> TEST_C27 <3> <2> TEST_DGATE <1> TEST_MSL TEST_SGATE <0> 35h <7:6> DOUT_SEL<1:0> PROBESEL <5> <4:0> TMON<4:0> 36h <7> VCXO_TEST<7> <6> VCXO_TEST<6> <5> VCXO_TEST<5> VCXO_TEST<4> <4> VCXO_TEST<3> <3> VCXO_TEST<2> <2> VCXO_TEST<1> <1> <0> VCXO_TEST<0> remarks MCK Comp Filter X'tal ‹ì“® CNT2 X'tal ‹ì“® CNT1 Šî•€ˆÊ‘Š CNT4 Šî•€ˆÊ‘Š CNT3 Šî•€ˆÊ‘Š CNT2 Šî•€ˆÊ‘Š CNT1 ƒoƒbƒNƒAƒbƒv‰ñ˜H•Ø‘Ö‚¦ ( 15 / 15 )