19-2342; Rev 0; 02/02 KIT EVALUATION AVAILABLE 2.7Gbps Post Amp with Automatic Gain Control This amplifier has a small-signal bandwidth of 3.4GHz and an input-referred noise of 0.26mVRMS. Over an input signal range of 6mVP-P to 1200mVP-P (46dB), the MAX3861 delivers a constant output amplitude that is adjustable from 400mVP-P to 920mVP-P. Variation in output swing is controlled within 0.2dB over a 16dB input range. The MAX3861 provides a received-signalstrength indicator (RSSI) that is linear, within 2.5%, for input signal levels up to 100mVP-P and an input signal detect (SD) with programmable threshold. Features ♦ Single 3.3V Power Supply ♦ 72mA Supply Current ♦ 3.4GHz Small-Signal Bandwidth ♦ 0.26mVRMS Input-Referred Noise ♦ 6mVP-P to 1200mVP-P Input Range (46dB) ♦ Input Signal Detect with Programmable Threshold ♦ RSSI (Linear Up to 100mVP-P) ♦ Adjustable Output Amplitude ♦ 0.2dB Output Voltage Variation (Over 16dB Input Signal Variation) Applications OC-48/STM-16 Transmission Systems Ordering Information TEMP RANGE PIN-PACKAGE WDM Optical Receivers MAX3861EGG -40°C to +85°C 24 QFN* Long Reach Optical Receivers MAX3861E/D -40°C to +85°C Dice** PART Continuous Rate Receivers Typical Application Circuit *EP = Exposed Pad **Dice are designed to operate over a -40°C to +120°C junction temperature (TJ) range, but are tested and guaranteed at TA = +25°C. CCD 0.1µF 50Ω 0.1µF 50Ω IN- MAX3861 OUT- 50Ω MAXIM MAX3873 CDR 0.1µF RTH 1.8kΩ TH OSM SD VREF RSSI RRSSI 50kΩ CONTROLLED IMPEDANCE LINE EN SC ROSM 50kΩ GND CD+ CD- RSSI 22 21 20 19 TH 1 18 SD VCC 2 17 VCC IN+ 3 16 OUT+ IN- 4 15 OUT- VCC 5 14 VCC EN 6 13 OSM MAX3861 7 8 9 10 11 12 GND OUT+ 23 CG- CG- IN+ 24 CG+ CZ- CCG 2200pF GND CG+ SC MAXIM 2.7Gbps TIA 50Ω CD- CD+ VREF CZ+ CCZ 0.22µF CZ- TOP VIEW CZ+ Pin Configuration QFN-EP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3861 General Description The MAX3861 is a low-power amplifier with automatic gain control (AGC), designed for WDM transmission systems employing optical amplifiers and requiring a vertical threshold adjustment after the post amp. Operating from a single 3.3V supply, this AGC amplifier linearly amplifies/attenuates the input signal while maintaining a fixed output-voltage swing at data rates up to 2.7Gbps. Both the input and output are on-chip terminated to match 50Ω interfaces. MAX3861 2.7Gbps Post Amp with Automatic Gain Control ABSOLUTE MAXIMUM RATINGS CML Input Current at IN+, IN-.............................................25mA CML Output Current at OUT+, OUT- ..................................25mA Storage Temperature Range .............................-55°C to +150°C Operating Junction Temperature Range ...........-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Processing Temperature (Die).........................................+400°C Supply Voltage ......................................................-0.5V to +4.0V Voltage at IN+, IN- ..........................(VCC - 1.5V) to (VCC + 0.5V) Voltage at CZ+, CZ-, CG+, CG-, CD+, CD- ............................(VCC - 3.5V) to (VCC + 0.5V) Voltage at SC, SD, EN, TH, OSM, VREF, and RSSI............................-0.5V to (VCC + 0.5V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Supply Current Power-Supply Noise Rejection SYMBOL ICC PSNR CONDITIONS TYP MAX RSSI and SD enabled (Notes 2, 3) At minimum gain MIN 72 86 At maximum gain 94 112 RSSI and SD disabled (Notes 2, 3) At minimum gain 57 69 At maximum gain 78 94 VNOISE = 100mVP-P, fNOISE ≤ 10MHz, VSC = 2V (Note 4) VIN = 1000mVP-P 35 VIN = 10mVP-P 25 2.7 RIN Input Return Loss Single ended to VCC 40 Input Voltage Range 21 2.7GHz to 4.0GHz 15 VCC 0.3 Up to 6GHz at max gain, CCZ = 0.1µF VIN Maximum Differential Input Voltage for Linear Operation Output Resistance Output Return Loss Output Common-Mode Level Differential 0.9 ≤ linearity ≤ 1.1 ROUT 0.26 6 VSC = 0 700 VSC = 2V 650 Single ended to VCC 40 50 ≤2.7GHz 16 2.7GHz to 4.0GHz 11 VSC = 0 VCC 0.13 VSC = 2V VCC 0.28 RL = 50Ω to VCC VSC = 0, RL = 50Ω to VCC (Note 5) Maximum Differential Output Offset VSC = 2V, RL = 50Ω to VCC (Note 5) 2 50 ≤2.7GHz Input Common-Mode Level Input-Referred Noise mA dB Input Data Rate Input Resistance UNITS 6mVP-P ≤ VIN ≤ 700mVP-P ±3 700mVP-P ≤ VIN ≤ 1200mVP-P ±8 Gbps 60 Ω dB VCC V 0.35 mVRMS 1200 mVP-P mVP-P 60 Ω dB V ±14 mV 6mVP-P ≤ VIN ≤ 700mVP-P ±5.5 700mVP-P ≤ VIN ≤ 1200mVP-P ±11 _______________________________________________________________________________________ ±28 2.7Gbps Post Amp with Automatic Gain Control (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Differential Output Amplitude Output Amplitude Variation SYMBOL VOUT ∆VOUT CONDITIONS VSC = 0 RL = 50Ω to VCC (Note 6) VSC = 2V MIN TYP 300 760 400 500 920 1050 VIN ≥ 6mVP-P, RL = 50Ω to VCC (Notes 6, 7) MAX 0.2 1.0 At minimum gain 2.5 3.4 5.5 At maximum gain 2.2 CCZ = 0.1µF 2.9 7.6 4.3 13 Deterministic Jitter (Note 8) 15 50 Output Signal Monitor Voltage ROSM ≥ 2kΩ (Note 6) Small Signal Bandwidth BW Low-Frequency Cutoff VOSM (Note 3) VOUT = 920mVP-P 2.0 VOUT = 400mVP-P 0.9 Output Signal Monitor Linearity 0V ≤ VSC ≤ 2V (Note 6) SC Input Range (Note 9) AGC Loop Constant Without external capacitor CCG, VSC = 0 (Note 10) RSSI Output Voltage RSSI RSSI Linearity RRSSI ≥ 2kΩ, VSC = 0 (Note 6) ±12 ±2.5 ±8 2 Maximum SD Assert Input 100 SD Assert Time 10 SD Deassert Time CG+ and CG- are open (Note 11) SD Accuracy (Note 12) 10mVP-P ≤ VIN ≤ 100mVP-P 10 2.8 % mVP-P mVP-P 70 µs 44 µs ±10 2mVP-P ≤ VIN ≤ 10mVP-P (Note 13) Sourcing 20µA current V 1800 ±2.5 Sinking 2mA current psP-P mV VIN = 100mVP-P 2mVP-P ≤ VIN ≤ 100mVP-P (Note 14) SD Output Low Voltage kHz µs 6mVP-P ≤ VIN ≤ 100mVP-P SD Output High Voltage GHz 55 Minimum SD Assert Input SD Hysteresis dB % 2.0 16 VIN = 2mVP-P mVP-P V ±10 0 UNITS 4.5 % 6.3 4.5 2.4 dB V 0.44 V 0.8 V EN Input Low Voltage VIL EN Input High Voltage VIH EN Input Low Current IIL VIL = 0 10 µA EN Input High Current IIH VIH = 2.0V 10 µA VREF Output Voltage Note 1: Note 2: Note 3: Note 4: 2.0 RVREF ≥ 40kΩ V 2.0 V Electrical characteristics are measured or characterized using a 223 - 1PRBS at 2.7Gbps with input edge speeds ≤200ps, unless otherwise noted. Dice are tested at TA = +25°C only. All AC specifications are guaranteed by design and characterization, unless otherwise noted. Supply current measurement is taken with AC-coupled inputs and excludes output currents into 50Ω loads. Minimum gain is defined as VIN = 1200mVP-P and VOUT = 400mVP-P. Maximum gain is defined as VIN = 6mVP-P and VOUT = 920mVP-P. Reference gain is measured at 100MHz. Power-supply noise rejection is characterized with a 2.7Gbps 1100 pattern on the input. It is calculated by the equation PSNR = 20log(∆VCC / (∆VOUT)), where ∆VOUT is the change in differential output voltage because of power-supply noise. See Power Supply Noise Rejection vs. Frequency in the Typical Operating Characteristics. _______________________________________________________________________________________ 3 MAX3861 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1) Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: See Distribution of Differential Output Offset (Worst-Case Conditions) in the Typical Operating Characteristics. Characterized with a 675Mbps 1-0 pattern. Measurements are taken over an input signal range of 16dB. Deterministic jitter is defined as the arithmetic sum of PWD (pulse-width distortion) and PDJ (pattern-dependent jitter). Deterministic jitter is the difference of total jitter and random jitter, with system jitter calibrated out. It is measured with a 27 - 1PRBS, and 80CIDs with DC-coupled outputs. Typical input resistance of SC pin is 40kΩ. AGC loop time constant is measured with a 20dB change in the input and VSC held constant. With an external capacitor CCG of 0.022µF connected between CG+ and CG-, a typical AGC loop time constant of 760µs is achieved. SD deassert time depends on the AGC loop time constant set by CCG. SD accuracy is defined as the part-to-part variation of the SD threshold at a fixed RTH value. See Distribution of SD Hysteresis (Worst-Case Conditions) in the Typical Operating Characteristics. Measurements are taken over an input signal range of 20dB. Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) 700 600 500 VSC = GND 300 15 10 5 400 600 800 1000 1200 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 SD HYSTERESIS (dB) SUPPLY CURRENT vs. TEMPERATURE EYE DIAGRAM, MINIMUM INPUT 90 85 80 VIN = 6mVP-P 223 - 1 PRBS 75 70 MAX3861 toc03 12 10 8 6 4 1 10 100 VIN = 1200mVP-P 223 - 1 PRBS 60 55 EN = GND 50 -40 -10 20 50 80 76ps/div 76ps/div TEMPERATURE (°C) 4 10,000 EYE DIAGRAM, MAXIMUM INPUT EN = VCC 65 1000 INPUT AMPLITUDE (mVP-P) MAX3861 toc05 EXCLUDES OUTPUT LOAD CURRENTS VIN = 1200mVP-P VSC = 0 95 MAX3861 toc04 INPUT AMPLITUDE (mVP-P) 100 14 0 0 200 16 2 223 - 1PRBS AT 2.7Gbps 100 0 18 MAX3861 toc06 200 20 DETERMINISTIC JITTER (psP-P) 20 PERCENT OF UNITS (%) OUTPUT AMPLITUDE (mVP-P) 800 VCC = 3.0V VSC = 2.0V VIN = 2mVP-P TA = -40°C MEAN = 4.52dB σ = 0.79dB MAX3861 toc02 VSC = 2.0V 400 25 MAX3861 toc01 1000 900 DETERMINISTIC JITTER VS. INPUT AMPLITUDE DISTRIBUTION OF SD HYSTERESIS (WORST-CASE CONDITIONS) OUTPUT AMPLITUDE vs. INPUT AMPLITUDE SUPPLY CURRENT (mA) MAX3861 2.7Gbps Post Amp with Automatic Gain Control _______________________________________________________________________________________ 2.7Gbps Post Amp with Automatic Gain Control POWER-SUPPLY NOISE REJECTION vs. FREQUENCY -10 -20 -25 30 20 -30 VIN = 10mVP-P MEASURED ON EVALUATION BOARD -35 10 1 -40 0 10k 100k 1M 50M 10M 100M FREQUENCY (Hz) |S11| vs. FREQUENCY OUTPUT SIGNAL AMPLITUDE vs. SC PIN VOLTAGE (VIN = 1.0VP-P) 1000 MAX3861 toc10 -5 900 800 700 600 3.0 500 MEASURED ON EVALUATION BOARD 100M 1.5 223 - 1PRBS 0 0 10G 1G 0.5 1.0 1.5 2.0 0 50 VSC (V) FREQUENCY (Hz) VCC = 3.6V VSC = 0V VIN = 700mVP-P TA = -40°C 20 150 200 250 300 DISTRIBUTION OF DIFFERENTIAL OUTPUT OFFSET (VSC = 2V) 15 10 10 VCC = 3.6V VSC = 2.0V VIN = 700mVP-P TA = -40°C 9 8 PERCENT OF UNITS (%) 25 100 INPUT AMPLITUDE (mVP-P) DISTRIBUTION OF DIFFERENTIAL OUTPUT OFFSET (VSS = 0V) MAX3861 toctoc13 50M 2.0 0.5 400 -40 2.5 1.0 -30 -35 100,000 RSSI OUTPUT vs. INPUT AMPLITUDE RSSI OUTPUT (V) VOUT (mVP-P) -25 PERCENT OF UNITS (%) |S11| (dB) -20 10,000 3.5 -10 -15 1000 RTH (Ω) FREQUENCY (Hz) 0 100 10G 1G MAX3861 toc11 5k 10 MAX3861 toc12 VIN = 1000mVP-P 40 -15 |S22| (dB) 50 7 MAX3861 toc14 60 MAX3861 toc09 -5 100 SD ASSERT THRESHOLD (mVP-P) MAX3861 toc08 70 SIGNAL DETECT THRESHOLD vs. RTH |S22| vs. FREQUENCY 0 MAX3861 toc07 POWER-SUPPLY NOISE REJECTION (dB) 80 6 5 4 3 2 5 1 0 0 -10 -8 -6 -4 -2 0 2 4 6 DIFFERENTIAL OUTPUT OFFSET (mV) 8 10 -16 -12 -8 -4 0 4 8 12 16 DIFFERENTIAL OUTPUT OFFSET (mV) _______________________________________________________________________________________ 5 MAX3861 Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) 2.7Gbps Post Amp with Automatic Gain Control MAX3861 Pin Description 6 PIN NAME FUNCTION 1 TH Input Signal Detect Threshold Programming Pin. Attach a resistor between this pin and ground to program the input signal detect assert threshold. Leaving this pin open sets the signal detect threshold to its absolute minimum value (<2mVP-P). See the Design Procedure section. 2, 5, 14, 17 VCC Supply Voltage Connection. Connect all VCC pins to the board VCC plane. 3 IN+ Positive CML Signal Input with On-Chip Termination Resistor 4 IN- Negative CML Signal Input with On-Chip Termination Resistor 6 EN Signal Detect Enable. Set high (≥2.0V) or leave open to enable the input signal detection (RSSI and SD) circuitry. Set low (≤0.4V) to power-down the input signal detection circuitry. 7 VREF Reference Voltage Output (2.0V). Connect this pin to the SC pin for maximum output signal swing. 8 SC Output Amplitude External Control. Ground SC for minimum output amplitude. Apply 2.0V to SC or connect SC directly to VREF for maximum output amplitude. 9, 12, 22 GND Ground. Connect all GND pins to the board ground plane. 10 CG+ Connection for AGC Loop Capacitor. A capacitor connected between CG+ and CG- sets the AGC loop time constant. 11 CG- Connection for AGC Loop Capacitor. A capacitor connected between CG+ and CG- sets the AGC loop time constant. 13 OSM Output Signal Monitor. This DC signal is linearly proportional to the output signal amplitude. 15 OUT- Negative CML Data Output with On-Chip Back-Termination Resistor 16 OUT+ Positive CML Data Output with On-Chip Back-Termination Resistor 18 SD Input Signal Detect. Asserts logic low when the input signal level drops below the programmed threshold. 19 RSSI Received Signal Strength Indicator. Outputs a DC signal that is linearly proportional to the input signal amplitude. 20 CD- Connection for Signal Detect Capacitor. A capacitor connected between CD+ and CD- sets the offset-cancellation loop time constant of the input signal detection. See the Detailed Description section. 21 CD+ Connection for Signal Detect Capacitor. A capacitor connected between CD+ and CD- sets the offset-cancellation loop time constant of the input signal detection. See the Detailed Description section. 23 CZ- Connection for Offset-Cancellation Loop Capacitor. A capacitor connected between CZ+ and CZsets the offset-cancellation loop time constant of the main signal path. See the Detailed Description section. 24 CZ+ Connection for Offset-Cancellation Loop Capacitor. A capacitor connected between CZ+ and CZsets the offset-cancellation loop time constant of the main signal path. See the Detailed Description section. EP Exposed Pad Maxim recommends connecting the exposed pad to board ground. _______________________________________________________________________________________ 2.7Gbps Post Amp with Automatic Gain Control VCC CZ+ CZ- OUT+ IN+ MAIN SIGNAL PATH Main Signal Path IN- The main signal path consists of variable gain amplifiers with CML output levels and an offset cancellation loop. This configuration allows for overall gains ranging from -9.5dB to 43.5dB. OUT- INPUT SIGNAL DETECT OSM Offset-Cancellation Loop The offset-cancellation loop partially reduces additional offset at the input. In communications systems using NRZ data with a 50% duty cycle, pulse-width distortion present in the signal or generated by the transimpedance amplifier appears as input offset and is partially removed by the offset cancellation loop. An external capacitor is required between CZ+ and CZ- to compensate the offset cancellation loop and determine the lower 3dB frequency of the signal path. MAX3861 Detailed Description Figure 1 is a functional diagram of the MAX3861 automatic gain-control amplifier. The MAX3861 is divided into three sections: main signal path, input signal detection, and output signal detection. CD+ CD- CONTROL BLOCK AND OUTPUT SIGNAL DETECT MAX3861 SC VREF CG+ CG- RSSI SD SD CIRCUITRY EN TH RTH GND Input Signal Detection and SD Circuitry The input signal detection circuitry consists of variable gain amplifiers and threshold voltages. Input signal detection information is compared to an internal reference and creates the RSSI voltage and an internal reference signal. The signal detect (SD) circuitry indicates when the input signal is below the programmed threshold by comparing a voltage proportional to the RSSI signal with internally generated control voltages. The SD threshold is set by a control voltage developed across the external TH resistor (RTH). Two control voltages, V ASSERT and V DEASSERT , define the signal detect assert and deassert levels. To prevent SD chatter in the region of the programmed threshold, 2.8dB to 6.3dB of hysteresis is built into the SD assert/deassert function and thus, once asserted, SD is not deasserted until sufficient gain is retained. When input signal detection (SD and RSSI) is not required, tie EN to a TTL low to power-down this circuitry. Figure 1. Functional Diagram Output Signal Monitor and Amplitude Control Output amplitude typically can be adjusted from 400mVP-P to 920mVP-P by applying a control voltage (0V to 2.0V) to the SC pin. See Output Signal Amplitude vs. SC Pin Voltage in the Typical Operating Characteristics. Connect the VREF pin (2.0V) to the SC pin for maximum output amplitude. The output signal monitor pin provides a DC voltage that is linearly proportional to the output signal. Design Procedure Program the SD Threshold The SD threshold is programmed by an external resistor, RTH, between the range of 2mVP-P to 100mVP-P. The circuit is designed to have approximately 4.5dB of hysteresis over the full range. See Signal Detect Threshold vs. R TH graph in the Typical Operating Characteristics for proper sizing. _______________________________________________________________________________________ 7 MAX3861 2.7Gbps Post Amp with Automatic Gain Control Select the Coupling Capacitors When AC-coupling is desired, coupling capacitors CIN and COUT should be selected to minimize the receiver’s deterministic jitter. Jitter is decreased as the input low-frequency cutoff (fIN) is decreased. fIN = [ 1 ] 2π(50)(CIN ) For ATM/SONET or other applications using scrambled NRZ data, select (CIN, COUT) ≥ 0.1µF, which provides fIN < 32kHz. For Fibre Channel, Gigabit Ethernet, or other applications using 8B/10B data coding, select (CIN, COUT) ≥ 0.01µF, which provides fIN <320kHz. Setting the Offset-Cancellation Loop Time Constant for Input Signal Detection Circuitry (Selecting CCD) The capacitor between CD+ and CD- determines the time constant of the input signal detection DC offsetcancellation loop. A value of 0.1µF for CCD provides a low-frequency cutoff (fC) below 10kHz. If a lower cutoff frequency is desired, 0.22µF gives fC = 4.5kHz and 0.47µF gives fC = 2.1kHz. To guarantee stable operation, a capacitor of less than 0.01µF should not be used. Setting the Automatic Gain-Control Loop Time Constant (Selecting CCG) The automatic gain-control loop time constant is determined by the external capacitor connected between CG+ and CG-. A value of at least 0.0022µF is recommended Programming the Output Amplitude (Programming the SC Pin) Output amplitude can be programmed from 400mVP-P to 920mVP-P by applying a voltage to the SC pin. See Output Signal Amplitude vs SC Pin Voltage in the Typical Operating Characteristics. Applications Information Wire Bonding Die For high current density and reliable operation, the MAX3861 uses gold metallization. Make connections to the dice with gold wire only, and use ball-bonding techniques (wedge bonding is not recommended). The MAX3861 has two types of bond pads: the dimensions for square bondpads are 94.4 microns by 94.4 microns; the dimensions for the octagonal bondpads are 33.6 microns per side. Die thickness is 12mils (0.305mm). Setting the Offset-Cancellation Loop Time Constant for the Main Signal Path (Selecting CCZ) The capacitor between CZ+ and CZ- determines the time constant of the signal path DC offset-cancellation loop. To maintain stability, it is important to keep a onedecade separation between fIN and the low-frequency cutoff (fOC) associated with the DC offset-cancellation circuit. For SONET applications, f IN < 32kHz, so f OCMAX < 3.2kHz. Therefore, C CZ = 0.22µF (f OC = 2.99kHz), CCZ = 0.47µF (fOC = 1.4kHz), or a greater value may be used.To guarantee stable operation, a capacitor of less than 0.01µF should not be used. 8 _______________________________________________________________________________________ 2.7Gbps Post Amp with Automatic Gain Control VCC 50Ω 50Ω MAX3861 VCC 50Ω 50Ω OUT+ IN+ OUT- IN- Figure 2. Input Interface Figure 3. Output Interface VCC VCC 180kΩ VCC CG+ TH 200Ω RTH 200kΩ CG- 180kΩ Figure 4. TH Interface Figure 5. CG Interface _______________________________________________________________________________________ 9 MAX3861 2.7Gbps Post Amp with Automatic Gain Control Pad Coordinates VCC PAD PAD NAME COORDINATES (µm) 1 N.C. 47, 47 2 EN 44, 264 3 N.C. 44, 419 4 VCC 47, 582 5 IN- 43, 776 6 IN+ 43, 927 7 VCC 45, 1123 8 TH 44, 1452 9 GND 47, 1672 10 CZ+ 306, 1672 11 CZ- 432, 1672 12 GND 593, 1671 13 N.C. 908, 1672 14 N.C. 1034, 1672 15 CD+ 1181, 1672 16 CD- 1307, 1672 17 RSSI 1461, 1672 18 GND 1662, 1671 19 SD 1669,1458 20 VCC 1668, 1126 21 OUT+ 1671, 927 22 OUT- 1671, 776 23 VCC 1668, 577 24 OSM 1669, 272 25 GND 1661, 47 26. N.C. 1356, 47 27 CG- 1207, 45 28 CG+ 1081, 45 29 GND 670, 47 30 SC 513, 45 31 N.C. 355, 45 32 VREF 199, 45 56.2kΩ CD+ 2kΩ CD- 2kΩ 56.2kΩ Figure 6. CD Interface VCC 56.2kΩ CZ+ 2kΩ CZ- 2kΩ 56.2kΩ Coordinates are for the center of the pad. Coordinate 0, 0 is the lower left corner of the passivation opening for pad 1. Figure 7. CZ Interface 10 ______________________________________________________________________________________ 2.7Gbps Post Amp with Automatic Gain Control CZ(PAD 11) CZ+ (PAD 10) N.C. (PAD 13) GND (PAD 12) RSSI (PAD 17) CD+ (PAD 15) N.C. (PAD 14) CD(PAD 16) GND (PAD 9) GND (PAD 18) TH (PAD 8) SD (PAD 19) VCC (PAD 7) VCC (PAD 20) IN+ (PAD 6) OUT+ (PAD 21) IN(PAD 5) OUT(PAD 22) VCC (PAD 4) VCC (PAD 23) 0.081" (2.06mm) N.C. (PAD 3) EN (PAD 2) OSM (PAD 24) N.C. (PAD 1) VREF (PAD 32) SC (PAD 30) N.C. (PAD 31) CG+ (PAD 28) GND (PAD 29) N.C. (PAD 26) GND (PAD 25) CG(PAD 27) 0.081" (2.06mm) TRANSISTOR COUNT: 952 Insulated SiGe Bipolar PROCESS: Bipolar F60 DIE SIZE: 2.06mm ✕ 2.06mm ______________________________________________________________________________________ 11 MAX3861 Chip Topography 2.7Gbps Post Amp with Automatic Gain Control 12,16,20, 24L QFN.EPS MAX3861 Package Information 12 ______________________________________________________________________________________ 2.7Gbps Post Amp with Automatic Gain Control Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX3861 Package Information (continued)