AvnetCore: Datasheet Version 1.0, July 2006 UTOPIA Level 3 Link Intended Use: — Cell Processors — Switch Fabrics — Networking — Telecommunications top_master.vhd Features: top_egr_master.vhd — Function compatible with ATM Forum wr_enb rd_enb txclk wr_data wr_flag rd_data rd_flag tx_data txenb_n wr_clk fifo_16.vhd/fifo_8.vhd egr_utopia_master.vhd — 8/16/32 bit interfaces supported tx_soc — Simple system side FIFO interface reset_n rd_clk — Flow control and polling integrated Targeted Devices: top_ing_master.vhd — Axcelerator Family wr_enb wr_data rd_flag — Up to 256 phys supported txclav txprty tx_addr rd_enb rd_data — Asynchronous/synchronous FIFO using RAM rxclk rxdata wr_flag fifo_16.vhd/fifo_8.vhd ing_utopia_master.vhd increment rxenb_n rx_clav rx_prty rx_soc rx_addr Core Deliverables: — Netlist Version > Netlist compatible with the Actel Designer place and route tool > Compiled RTL simulation model, compliant with the Actel Libero® environment — RTL Version > VHDL Source Code — All Block Diagram > User Guide > Test Bench Synthesis and Simulation Support: UTOPIA (Universal Test and Operations PHY Interface for ATM) level 3 defines the interface between the ATM or LINK layer and a Physical Layer (PHY) device. The UTOPIA level 3 standard defines a full duplex interface with a Master/Slave format. The Slave or LINK layer device responds to the requests from the PHY or Master device. The Master performs PHY arbitration and initiates data transfers to and from the Slave. The ATM forum has defined the UTOPIA Level 3 as either 8 or 32 bits in width, at up to 104 MHz, supporting an OC48 channel at 2.5 Gbps. — Synthesis: Synplicity® — Simulation: ModelSim® — Other tools supported upon request Verification: — Test Bench — Test Vectors Functional Description This core conforms to the appropriate standard(s). In general, standards do not define the internal user interface, only the external interfaces and protocols. Therefore, Avnet Memec has created a simple FIFO interface to this core for easy user connectivity. This document describes this Avnet Memec created interface. Please consult the appropriate standards document for all external signaling. TOP_MASTER This is the top level of the core. Its only purpose is to serve as a container to instantiate the Ingress and Egress modules. Egress Master The egress master is responsible for polling the PHYs and internal queues in order to send cells to the slave device. Ingress/Egress FIFO The FIFO contains the RAM FIFO and the pointer processing blocks. The FIFO operates in synchronous and asynchronous systems. The FIFO contains additional logic to implement a SOC-SOC pointer reset. There is one FIFO per PHY polled. Ingress Master The Ingress master is responsible for polling the PHYs and internal queues in order to accept cells from the slave device. wr_enb wr_data wr_flag wr_clk txclk tx_data txenb_n txclav tx_soc txprty tx_addr fifo_16/fifo_8 top_egr_master egr_utopia_mast er top_egr_master reset_n fifo_16/fifo_8 top_ing_master rxclk rx_data rxenb_n rx_clav rx_prty rx_soc rx_addr rd_enb rd_data rd_flag rd_clk MDS8074a Figure 1: Logic Symbol ing_utopia_master top_ing_master Device Requirements Family Device Utilization Performance COMB SEQ Tiles Axcelerator AX250 38% 76% n/a 104 MHz ProASIC3 A3PE600 n/a n/a 20% 97 MHz ProASICPLUS APA150 n/a n/a 53% 85 MHz Table 1: Device Utilization and Performance Verification and Compliance The testbench is self-checking, which means that if there is an error detected in the start word, end word, or payload the testbench will assert one or both of two error signals. The test checks for errors at two stages in the testbench: when the cells (packets) are looped back through the PHY device (SIG_LOOP_ERROR_OUT), and upon reading out of the link device (SIG_ERROR_OUT). This core has also been used successfully in customer designs. Signal Descriptions The following signal descriptions define the IO signals. Signal Width Direction WR_ENB N Input Write enable signal for FIFO WR_DATA N*8/16/32 Input Write data bus for FIFO WR_FLAG N Output WR_CLK N Input Write clock for the FIFO RESET_N 1 Input Reset signal from user logic RD_ENB N Input Read enable signal for the FIFO RD_DATA N*8/16/32 Output Read data bus for the FIFO RD_FLAG N Output FIFO read flag indicating that a cell is ready to be read from the ports FIFO RD_CLK N Input Read clock for the FIFO Tx utopia clock TXCLK TX_DATA TXENB_N Description Write flag indicating if FIFO can accept another cell 1 Input 8/16/32 Output Tx utopia data bus Tx utopia enable signal 1 Output TXCLAV 1/N<4 Input TX_SOC 1 Output Tx utopia start of cell signal TXPRTY 1 Output Tx utopia parity signal TX_ADDR 8 Output Tx utopia polling address bus RXCLK 1 Input Ingress utopia clock RXDATA Ingress utopia data bus Tx utopia cell available signal(s) 8/16/32 Input RXENB_N 1 Output RX_CLAV 1/ N<4 Input Ingress utopia cell available signal(s) RX_PRTY 1 Input Ingress utopia parity signal RX_SOC 1 Input Ingress utopia start of cell signal RX_ADDR 8 Output Ingress utopia enable signal Ingress utopia address bus Table 2: Core I/O Signals Timing Since the ATM Forum specification fully defines the line side of the UTOPIA Level 3 interface, timing for that is not replicated here. Instead, only user (FIFO) interface timing information is presented here. The figure below shows the functional timing for FIFO reads and writes. RD_CLK RD_ADDR A0 A1 A2 D0 D1 D2 A0 A1 ... A52 A53 D0 D1 ... D52 D53 RD_ENB RD_DATA WR_CLK WR_ADDR WR_ENB WR_DATA Figure 3: FIFO Timing Recommended Design Experience For the source version, users should be familiar with HDL entry and Actel design flows. Users should be familiar with Actel Libero Integrated Design Environment (IDE) and preferably with Synplify and ModelSim. Ordering Information The CORE is provided under license from Avnet Memec for use in Actel programmable logic devices. Please contact Avnet Memec for pricing and more information. Information furnished by Avnet Memec is believed to be accurate and reliable. Avnet Memec reserves the right to change specifications detailed in this data sheet at any time without notice, in order to improve reliability, function or design, and assumes no responsibility for any errors within this document. Avnet Memec does not make any commitment to update this information. Avnet Memec assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction, if such be made, nor does the Company assume responsibility for the functioning of undescribed features or parameters. Avnet Memec will not assume any liability for the accuracy or correctness of any support or assistance provided to a user. Avnet Memec does not represent that products described herein are free from patent infringement or from any other third-party right. No license is granted by implication or otherwise under any patent or patent rights of Avnet Memec. AvnetCore products are not intended for use in life support appliances, devices, or systems. Use of a AvnetCore product in such application without the written consent of the appropriate Avnet Design officer is prohibited. All trademarks, registered trademarks, or service marks are property of their respective owners. Contact Information: North America 10805 Rancho Bernardo Road Suite 100 San Diego, California 92127 United States of America TEL: +1 858 385 7500 FAX: +1 858 385 7770 Europe, Middle East & Africa Mattenstrasse 6a CH-2555 Brügg BE Switzerland TEL: +41 0 32 374 32 00 FAX: +41 0 32 374 32 01 Ordering Information: Part Number MC-ACT-UL3LINK-NET MC-ACT-UL3LINK-VHDL Hardware Actel UL3LINK Netlist Actel UL3LINK VHDL Resale Contact for pricing Contact for pricing www.em.avnet.com/actel Copyright © 2006 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are the property of their respective owners. AEM-MC-ACT-UL3LINK-DS v.1.0-July 2006