SEMICONDUCTOR TECHNICAL DATA The MC10E/100E196 is a programmable delay chip (PDC) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the logic symbol. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps. These two elements provide the E196 with a digitally-selectable resolution of approximately 20 ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on chip by a high signal on the latch enable (LEN) control. The FTUNE input takes an analog voltage and applies it to an internal linear ramp for reducing the 20 ps resolution still further. The FTUNE input is what differentiates the E196 from the E195. An eighth latched input, D7, is provided for cascading multiple PDC’s for increased programmable range. The cascade logic allows full control of multiple PDC’s, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating. • • • • • • • PROGRAMMABLE DELAY CHIP 2.0ns Worst Case Delay Range ≈20ps/Delay Step Resolution Linear Input for Tighter Resolution >1.0GHz Bandwidth On Chip Cascade Circuitry Extended 100E VEE Range of –4.2 to –5.46V 75KΩ Input Pulldown Resistors FN SUFFIX PLASTIC PACKAGE CASE 776-02 PIN NAMES Pin Function IN/IN EN D[0:7] Q/Q LEN SET MIN SET MAX CASCADE FTUNE Signal Input Input Enable Mux Select Inputs Signal Output Latch Enable Min Delay Set Max Delay Set Cascade Signal Linear Voltage Input LOGIC DIAGRAM – SIMPLIFIED VBB FTUNE 11 IN IN EN * 1.25 0 0 1 1 0 1 1 0 1 1 4 GATES 1 0 8 GATES 1 0 16 GATES 1 0 1 * 1.5 0 1 CASCADE LEN LEN SET MIN SET MAX D0 * DELAYS ARE 25% OR 50% LONGER THAN * STANDARD (STANDARD ≈ 80 PS) 7 BIT LATCH D1 D2 D3 D5 D6 D7 12/93 Motorola, Inc. 1996 2–1 LINEAR RAMP Q LATCH D D4 Q Q 1 REV 2 CASCADE CASCADE MC10E196 MC100E196 Pinout: 28-Lead PLCC (Top View) D2 D3 D4 D5 D6 D7 NC 25 24 23 22 21 20 19 18 FTUNE D0 27 17 NC LEN 28 16 VCC VEE 1 15 VCCO IN 2 14 Q IN 3 13 Q VBB 4 12 VCCO 7 8 9 NC NC EN 10 11 CASCADE 6 CASCADE 5 SET MAX 26 SET MIN D1 DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0°C Symbol Characteristic IIH Input HIGH Current IEE Power Supply Current 10E 100E Min Typ 25°C Max Min Typ 150 85°C Max Min Typ 150 Max 150 Unit Condition µA mA 130 130 156 156 130 130 156 156 130 150 156 179 AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0°C Symbol 25°C 85°C Characteristic Min Typ Max Min Typ Max Min Typ Max tPLH tPHL Propagation Delay IN to Q; Tap = 0 IN to Q; Tap = 127 EN to Q; Tap = 0 D7 to CASCADE 1210 3320 1250 300 1360 3570 1450 450 1510 3820 1650 700 1240 3380 1275 300 1390 3630 1475 450 1540 3880 1675 700 1440 3920 1350 300 1590 4270 1650 450 1765 4720 1950 700 tRANGE Programmable Range tPD (max) – tPD (min) 2000 2175 2050 2240 2375 2580 55 115 250 505 1000 17 34 68 136 272 544 1088 55 115 250 515 1030 17.5 35 70 140 280 560 1120 65 140 305 620 1240 21 42 84 168 336 672 1344 D1 D0 D1 D0 D1 D0 ∆t Step Delay D0 High D1 High D2 High D3 High D4 High D5 High D6 High Lin Linearity tSKEW Duty Cycle Skew tPHL–tPLH MOTOROLA Unit Notes ps ps ps 105 180 325 620 1190 105 180 325 620 1220 6 120 205 380 740 1450 7 ps ±30 ±30 2–2 ±30 1 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E196 MC100E196 AC CHARACTERISTICS (continued) (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0°C Symbol ts th tR Characteristic Min Typ Setup Time D to LEN D to IN EN to IN 200 800 200 0 Hold Time LEN to D IN to EN 500 0 250 Release Time EN to IN SET MAX to LEN SET MIN to LEN 300 800 800 25°C Max Min Typ 200 800 200 0 500 0 250 85°C Max Min Typ 200 800 200 0 500 0 250 Max Unit Notes ps 2 3 ps tjit Jitter tr tf Output Rise/Fall Time 20–80% (Q) 20–80% (CASCADE) 4 ps 300 800 800 <5.0 300 800 800 <5.0 5 <5.0 ps 8 ps 125 300 225 450 325 650 125 300 225 450 325 650 125 300 225 450 325 650 1. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 2. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 3. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than ±75 mV to that IN/IN transition. 4. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than ±75 mV to that IN/IN transition. 5. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and transition times. 6. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range. 7. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for increasing binary counts on the control inputs Dn). Typically the device will be monotonic to the D0 input, however under worst case conditions and process variation, delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the LSB the device is guaranteed to be monotonic over all specified environmental conditions and process variation. 8. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques. ANALOG INPUT CHARACTERISTICS Ftune = VCC to VEE 140 100 90 PROPAGATION DELAY (ps) PROPAGATION DELAY (ps) 120 100 80 60 40 80 70 60 50 40 30 20 20 0 –4.5 10 –3.5 –2.5 –1.5 0 –5 –0.5 FTUNE VOLTAGE (V) –3 –2 –1 0 FTUNE VOLTAGE (V) Propagation Delay versus Ftune Voltage (100E196) ECLinPS and ECLinPS Lite DL140 — Rev 4 –4 Propagation Delay versus Ftune Voltage (10E196) 2–3 MOTOROLA MC10E196 MC100E196 USING THE FTUNE ANALOG INPUT expanded for larger E195 chains. The D7 input of the E195 is the cascade control pin. With the interconnect scheme of Figure 1 when D7 is asserted it signals the need for a larger programmable range than is achievable with a single device. The analog FTUNE pin on the E196 device is intended to enhance the 20 ps resolution capabilities of the fully digital E195. The level of resolution obtained is dependent on the number of increments applied to the appropriate range on the FTUNE pin. An expansion of the latch section of the block diagram is pictured below. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D7 of chip #1 above is low the cascade output will also be low while the cascade bar output will be a logical high. In this condition the SET MIN pin of chip #2 will be asserted and thus all of the latches of chip #2 will be reset and the device will be set at its minimum delay. Since the RESET and SET inputs of the latches are overriding any changes on the A0–A6 address bus will not affect the operation of chip #2. To provide another level of resolution the FTUNE pin must be capable of adjusting the delay by greater than the 20 ps digital resolution. From the provided graphs one sees that this requirement is easily achieved as over the entire FTUNE voltage range a 100 ps delay can be achieved. This extra analog range ensures that the FTUNE pin will be capable even under worst case conditions of covering the digital resolution.Typically the analog input will be driven by an external DAC to provide a digital control with very fine analog output steps. The final resolution of the device will be dependent on the width of the DAC chosen. Chip #1 on the other hand will have both SET MIN and SET MAX de-asserted so that its delay will be controlled entirely by the address bus A0–A6. If the delay needed is greater than can be achieved with 31.75 gate delays (1111111 on the A0–A6 address bus) D7 will be asserted to signal the need to cascade the delay to the next E195 device. When D7 is asserted the SET MIN pin of chip #2 will be de-asserted and the delay will be controlled by the A0–A6 address bus. Chip #1 on the other hand will have its SET MAX pin asserted resulting in the device delay to be independent of the A0–A6 address bus. To determine the voltage range necessary for the FTUNE input, the graphs provided should be used. As an example if a range of 40 ps is selected to cover worst case conditions and ensure coverage of the digital range, from the 100E196 graph a voltage range of –3.25 V to –4.0 V would be necessary on the FTUNE pin. Obviously there are numerous voltage ranges which can be used to cover a given delay range, users are given the flexibility to determine which one best fits their designs. When the SET MAX pin of chip #1 is asserted the D0 and D1 latches will be reset while the rest of the latches will be set. In addition, to maintain monotonicity an additional gate delay is selected in the cascade circuitry. As a result when D7 of chip #1 is asserted the delay increases from 31.75 gates to 32 gates. A 32 gate delay is the maximum delay setting for the E195. Cascading Multiple E196’s To increase the programmable range of the E195 internal cascade circuitry has been included. This circuitry allows for the cascading of multiple E195’s without the need for any external gating. Furthermore this capability requires only one more address line per added E195. Obviously cascading multiple PDC’s will result in a larger programmable range, however, this increase is at the expense of a longer minimum delay. When cascading multiple PDC’s it will prove more cost effective to use a single E196 for the MSB of the chain while using E195 for the lower order bits. This is due to the fact that only one fine tune input is needed to further reduce the delay step resolution. Figure 1 illustrates the interconnect scheme for cascading two E195’s. As can be seen, this scheme can easily be ADDRESS BUS (A0–A6) LINEAR INPUT CASCADE EN VBB CASCADE IN SET MIN INPUT SET MAX VEE IN LEN Q VEE IN Q IN VCC0 D7 D6 D5 D3 D4 E196 Chip #2 VCC VCC0 Q VBB CASCADE VCC VCC0 CASCADE E196 Chip #1 SET MAX D0 EN LEN FTUNE D1 SET MIN FTUNE D1 D0 D2 D7 D6 D5 D4 D3 D2 A7 Q OUTPUT VCC0 Figure 1. Cascading Interconnect Architecture MOTOROLA 2–4 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E196 MC100E196 TO SELECT MULTIPLEXERS BIT 0 D0 BIT 1 Q0 D1 BIT 2 Q1 D2 BIT 3 Q2 D3 BIT 4 Q3 D4 BIT 5 Q4 D5 BIT 6 Q5 BIT 7 CASCADE D6 Q6 LEN LEN LEN LEN LEN LEN LEN Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset D7 Q7 CASCADE LEN Reset Reset SET MIN SET MAX Figure 2. Expansion of the Latch Section of the E195 Block Diagram ECLinPS and ECLinPS Lite DL140 — Rev 4 2–5 MOTOROLA MC10E196 MC100E196 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B Y BRK -N- T L –M M U 0.007 (0.180) X G1 M S N T L –M S S N S D Z -L- -M- D W 28 V 1 C A 0.007 (0.180) M R 0.007 (0.180) M T L –M S T L –M S N S N S H S N S 0.007 (0.180) M T L –M N S S 0.004 (0.100) G J -T- K SEATING PLANE F VIEW S G1 T L –M S N 0.007 (0.180) M T L –M S N S VIEW S S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MOTOROLA T L –M K1 E S S VIEW D-D Z 0.010 (0.250) 0.010 (0.250) 2–6 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 — 0.025 — 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 — 0.020 2° 10° 0.410 0.430 0.040 — MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 — 0.64 — 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 — 0.50 2° 10° 10.42 10.92 1.02 — ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E196 MC100E196 Motorola reserves the right to make changes without further notice to any products herein. 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