Order this document by MC1391/D
The MC1391 provides low–level horizontal sections including phase
detector, oscillator and pre–driver. This device was designed for use in all
types of television receivers.
• Internal Shunt Regulator
•
•
•
•
•
•
•
•
TV HORIZONTAL
PROCESSOR
Preset Hold Control Capability
SEMICONDUCTOR
TECHNICAL DATA
±300 Hz Typical Pull–In
Linear Balanced Phase Detector
Variable Output Duty Cycle for Driving Tube or Transistor
Low Thermal Frequency Drift
Small Static Phase Error
8
Adjustable DC Loop Gain
1
Positive Flyback Inputs
P SUFFIX
PLASTIC PACKAGE
CASE 626
ORDERING INFORMATION
RA
RB
470
470
Package
MC1391P
TA = 0° to +70°C
Plastic DIP
+
+150V
RD
2.7k
3k
Hold
RC
Rx
3.3k
12k
Ry
0.0068
µF
RE
2.4k
RF
Operating
Temperature Range
Figure 1. Simplified Application
Vnonreg
+ 30V
CA
100µF
Device
150k
CB
8
2.2k
7
6
0.005
µF
CC
1µF
To
High
Voltage
Tripler
4k
10W
+
5
MJ105 or Equiv
15k
MC1391P
1
2
3
39k
RZ{
82k
0.001
µF
15.3:1
4
0.1µF
5.0µF
1.5
MRD
1140
or
Equiv
MPS–U04
or Equiv
0.003
µF
–20V Sync
Y
O
K
E
0.01
µF
0.2
µF
0.1µF
{ RZ = 6.8 k per 100 V of flyback amplitude.
This circuit has an oscillator pull–in range of ±300 Hz, a noise bandwidth of 320 Hz, and a damping factor of 0.8.
Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
Rev 2
1
MC1391
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)
Value
Unit
Supply Current
40
mAdc
Output Voltage
40
Vdc
Output Current
30
mAdc
Sync Input Voltage (Pin 3)
5.0
Vpp
Flyback Input Voltage (Pin 4)
5.0
Vpp
Power Dissipation (Package Limitation)
Plastic Package
Derate above TA = +25°C
625
5.0
mW
mW/°C
0 to +70
°C
–65 to +150
°C
Rating
Operating Temperature Range (Ambient)
Storage Temperature Range
ELECTRICAL CHARACTERISTICS (TA = +25°C, unless otherwise noted. See Test Circuit of Figure 2, all switches in position 1.)
Min
Typ
Max
Unit
8.0
8.6
9.4
Vdc
Supply Current (Pin 6)
–
20
–
mAdc
Collector–Emitter Saturation Voltage (Output Transistor Q1 in Figure 6)
(IC = 20 mA, Pin 1 ) Vdc
–
0.15
0.25
Voltage (Pin 4)
–
2.0
–
Vdc
Oscillator Pull–in Range (Adjust RH in Figure 2)
–
±300
–
Hz
Oscillator Hold–in Range (Adjust RH in Figure 2)
–
±900
–
Hz
Static Phase Error
(∆f = 300 Hz)
–
0.5
–
Free–running Frequency Supply Dependance
(S1 in position 2)
–
±3.0
–
Phase Detector Leakage (Pin 5)
(All switches in position 2)
–
–
±1.0
Sync Input Voltage (Pin 3)
2.0
–
5.0
Vpp
Sawtooth Input Voltage (Pin 4)
1.0
–
3.0
Vpp
Characteristics
Regulated Voltage (Pin 6)
Vdc
µs
Hz/Vdc
µA
Figure 2. Test Circuit
0.1µF
+
3.3k
+
–
µA
+4.0V
RH
5
2
S1
6
12k
2
2
7
6800pF
8
Output
Pulse
+30V
1
1.0k
VCC +30V
3.3k
S2
1
2
3
MC1391P
150k
VM
(See Figure 5)
2
0.1µF
0.1µF
1
3.0k
1.0k
4
S3
39k
0.003 1
µF
Pulse Generator
Sync Pulse =
–20 V, 5.0 µs,
fO = 15.750 Hz
Pulse Generator
Output = +50 V
12 µs
2.0k
MOTOROLA ANALOG IC DEVICE DATA
MC1391
Figure 3. Frequency versus Temperature
Figure 4. Frequency Drift versus Warm–Up Time
40
30
20
f, FREQUENCY (Hz)
∆ f, FREQUENCY DRIFT (Hz)
Reference Frequency
= 15.750 Hz
10
0
–10
–20
–30
S3 in Position 2
–40
–50
30
20
Reference Frequency
= 15.750Hz
10
–60
0
–70
0
10
20
30
40
50
60
TA, AMBIENT TEMPERATURE (°C)
70
80
0
30
60
t, TIME (s)
90
120
Figure 5. Mark Space Ratio
4.75
4.5
fO = 15,750 Hz
t = 63.5 µs
VM , VOLTAGE (V)
4.25
4.0
3.75
3.5
3.25
3.0
2.75
0
10
20
30
POSITIVE PULSE WIDTH (µs)
40
50
Figure 6. Representative Schematic Diagram
Oscillator
Timing
Pre–Driver
7
VCC
Regulator
6
Oscillator
Phase Detector
R17 R22
10k 2.15
k
R14
330
R1
R8
2.4k
R6
3.3k
2.6k
R11
3.0k
Q4
R4 430
Q3
Output
1
Q2
R3
R2
7.5k
R5 2.4k
Q14
R15
3.3k
7.5k
7.5k
R
16
6.8k
Q12 R20
470
R13
240
2
Ground
Q16
4
Q17
Sawtooth
Input
510
D3
R7
Q15
R19
Q9
6.8k
MOTOROLA ANALOG IC DEVICE DATA
R12
820
Q10 R10
3.6k
Q5
Q1
Z1
Phase
Detector
Output
Q13
R
18
Q11
D2
Q7 Q8
R9
1.2k
5
Q18
D1
Q6
Mark–Space
Ratio 8
Z2
R23
2k
D4
R21
910
3
Sync Input
3
MC1391
CIRCUIT OPERATION
The MC1391P contains the oscillator, phase detector and
predriver sections needed for a television horizontal APC loop.
The oscillator is an RC type with one pin (Pin 7) used to
control the timing. The basic operation can be explained
easily. If it is assumed that Q7 is initially off, then the capacitor
connected from Pin 7 to ground will be charged by an
external resistor (RC) connected to Pin 6. As soon as the
voltage at Pin 7 exceeds the potential set at the base of Q8
by resistors R8 and R10, Q7 will turn on and Q6 will supply
base current to Q5 and Q10. Transistor Q10 will set a new,
lower potential at the base of Q8 determined by R8, R9 and
R10. At the same time, transistor Q5 will discharge the
capacitor through R4 until the base bias of Q7 falls below that
of Q8, at which time Q7 will turn off and the cycle repeats.
The sawtooth generated at the base of Q4 will appear
across R3 and turn off Q3 whenever it exceeds the bias
set on Pin 8. By adjusting the potential at Pin 8, the duty
cycle (MSR) at the predriver output pin (Pin 1) can be
changed to accommodate either tube or transistor horizontal
output stages.
The phase detector is isolated from the remainder of the
circuit by R14 and Z2. The phase detector consists of the
comparator Q15, Q16 and the gated current source Q17.
Negative going sync pulses at Pin 3 turn off Q12 and the
current division between Q15 and Q16 will be determined by
the phase relationship of the sync and the sawtooth
waveform at Pin 4, which is derived from the horizontal
flyback pulse. If there is no phase difference between the
sync and sawtooth, equal currents will flow in the collectors of
Q15 and Q16 each of half the sync pulse period. The current
in Q15 is turned around by Q18 so that there is no net output
current at Pin 5 for balanced conditions. When a phase offset
occurs, current will flow either in or out of Pin 5. This pin is
connected via an external low–pass filter to Pin 7, thus
controlling the oscillator.
Shunt regulation for the circuit is obtained with a zero
temperature coefficient from the series combination of D1,
D2 and Z1.
APPLICATION INFORMATION
Although it is an integrated circuit, the MC1391P has all
the flexibility of a conventional discrete component horizontal
APC loop. The internal temperature compensated voltage
regulator allows a wide supply voltage variation to be
tolerated, enabling operation from nonregulated power
supplies. A minimum value for supply current into Pin 6 to
maintain zener regulation is about 18 mA. Allowing 2.0 mA for
the external dividers
RA + RB =
Vnonreg(min)–8.8
20 x 10–3
Components RA, RB and CA are used for ripple rejection. If
the supply voltage ripple is expected to be less than 100 mV
(for a 30 V supply) then RA and RB can be combined and
CA omitted.
The output pulse width can be varied from 6.0 µs to 48 µs
by changing the voltage at Pin 8 (see Figure 5). However,
care should be taken to keep the lead lengths to Pin 8 as
short as possible at Pin 1. The parallel impedance of RD and
RE should be close to 1.0 kΩ to ensure stable pulse widths.
For 15 mA drive at saturation
RF =
Vnonreg –0.3
15 x 10–3
The oscillator free–running frequency is set by RC and CB
connected to Pin 7. For values of RC ≥ Rdischarge (R4 in
Figure 6), a useful approximation for the free–running
frequency is
1
fO =
0.6 RCCB
Proper choice of RC and CB will give a wide range of
oscillator frequencies – operation at 31.5 kHz for countdown
circuits is possible for example. As long as the product RCCB
≈ 10–4 many combinations of values of RC and CB will satisfy
the free–running frequency requirement of 15.734 kHz.
However, the sensitivity of the oscillator (β) to control–current
from the phase detector is directly dependent on the
magnitude of RC, and this provides a convenient method of
adjusting the dc loop gain (fc).
4
For a given phase detector sensitivity (µ) = 1.60 x 10–4 A/rad
fc = µβ and β = 3.15 x RC Hz/mA
Increasing RC will raise the dc loop gain and reduce the static
phase error (S.P.E.) for a given frequency offset. Secondary
effects are to increase the natural resonant frequency of the
loop (ωn) and give a wider pull–in range from an out–of–lock
condition. The loop will also tend to be underdamped with fast
pull–in times, producing good airplane flutter performance.
However, as the loop becomes more underdamped impulse
noise can cause shock excitation of the loop. Unlimited
increase in the dc loop gain will also raise the noise bandwidth
excessively causing horizontal jitter with thermal noise. Once
the dc loop gain has been selected for adequate SPE
performance, the loop filter can be used to produce the balance
between other desirable characteristics. Damping of the loop is
achieved most directly by changing the resistor RX with respect
to RY which modifies the ac/dc gain ration (m) of the loop.
Lowering this ratio will reduce the pull–in range and noise
bandwidth (fnn). (Note: very large values of RY will limit the
control capability of the phase detector with a corresponding
reduction in hold–in range.)
Static phasing can be adjusted simply by adding a small
resistor between the flyback pulse integrating capacitor and
ground. The sync coupling capacitor should not be too small
or it can charge during the vertical pulse and this may result in
picture bends at the top of the CRT.
Note: In adjusting the loop parameters, the following
equations may prove useful:
1 x χ2 TωC
χ = RX
fnn =
RY
4χT
wn =
ωC
√ (1 + c )T
ωC = 2 π fc
T = Ry CC
2
Tω
χ
C
K=
4
where: K = loop damping coeffecient
MOTOROLA ANALOG IC DEVICE DATA
MC1391
OUTLINE DIMENSIONS
8
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
5
–B–
1
4
F
–A–
NOTE 2
L
C
J
–T–
N
SEATING
PLANE
D
H
M
K
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
–––
10_
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
–––
10_
0.030
0.040
G
0.13 (0.005)
M
T A
MOTOROLA ANALOG IC DEVICE DATA
M
B
M
5
MC1391
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6
◊
*MC1391/D*
MOTOROLA ANALOG IC DEVICE
DATA
MC1391/D