Order this document by MC144112/D SEMICONDUCTOR TECHNICAL DATA Advance Information D SUFFIX SOG PACKAGE CASE 751A 14 1 CMOS ORDERING INFORMATION The MC144112 contains four independent DACs which are controlled through a common serial data port. When all DACs are utilized, there are 24 bits in the serial data stream. However, if not all DACs are utilized, the bit stream length may be reduced by up to six bits per unused DAC. For new designs, the MC144112 is preferred over the MC144110 and MC144111. The newer MC144112 offers a wider operating temperature range, lower operating supply voltage, and lower supply current. MC144112D SOG Package Plastic DIP availability dependent on market demand. • Operating Supply Voltage Range: 2.7 to 5.5 V * • Maximum Supply Current (per Package) — All DAC Outputs = Zero: 1.25 mA @ 2.7 V 2.1 mA @ 4.5 V All DAC Outputs = Full Scale: 30 µA @ 5.5 V • Integral Nonlinearity: – 1 1/4 to 1/4 LSB • Operating Temperature Range: – 40 to 85°C • Direct R–2R Network Outputs • Direct Interface to Motorola SPI Serial Data Port • Digital Data Output Permits Cascading PIN ASSIGNMENT Din 1 14 VDD NC 2 13 Dout R1 Out 3 12 R4 Out NC 4 11 NC R2 Out 5 10 R3 Out ENB 6 9 NC VSS 7 8 CLK BLOCK DIAGRAM NC = NO CONNECTION R1 OUT 3 R2 OUT R3 OUT R4 OUT 10 12 5 R–2R LADDER NETWORKS 6 6 6 6 R4 OUT INVERTING BUFFERS VDD 6 6 6 6 2R ENB CLK 6 8 Din 6 D ** C Q 1 LATCHES LOAD 6 6 2R 6 CLOCK 24–BIT SHIFT REGISTER DATA R R R R R 2R 2R 2R 2R 2R R–2R DETAIL 13 Dout * This product is being evaluated for operation at supply voltages less than 2.7 V. Contact your Motorola representative for further information. ** Transparent Latch This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 3 2/98 TN98030200 Motorola, Inc. 1998 MOTOROLA MC144112 1 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ MAXIMUM RATINGS* (Voltages referenced to VSS) Parameter Symbol Value Unit VDD – 0.5 to + 5.5 V Vin – 0.5 to VDD + 0.5 V I ± 10 mA DC Supply Voltage Input Voltage, All Inputs DC Input Current, per Pin Power Dissipation (Per Output) TA = 70°C TA = 85°C POH mW 50 20 Power Dissipation (Per Package) TA = 70°C TA = 85°C PD Storage Temperature Range Tstg mW 150 50 – 65 to + 150 This device contains protection circuitry to guard against damage due to high static voltages or electric fields; however, it is advised that precautions be taken to avoid application of voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout) ≤VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). °C * Maximum Ratings are those values beyond which damage to the device may occur. ELECTRICAL CHARACTERISTICS (Voltages referenced to VSS, VDD = 2.7 to 5.5 V, TA = – 40 to 85°C unless otherwise indicated) Parameter Symbol Test Conditions VDD Min Max Unit VIH High–Level Input Voltage (Din, ENB, CLK) 2.7 4.5 5.5 2.03 3.15 3.85 — — — V VIL Low–Level Input Voltage (Din, ENB, CLK) 2.7 4.5 5.5 — — — 0.67 1.35 1.65 V IOH High–Level Output Current (Dout) Vout = VDD – 0.5 V 2.7 4.5 0.3 1.1 — — mA IOL Low–Level Output Current (Dout) Vout = 0.5 V 2.7 4.5 1.0 1.8 — — mA ISS Quiescent Supply Current (per Package) Iout = 0 µA, All DAC Outputs = Zero 2.7 4.5 5.5 — — — 1.25 2.10 2.50 mA Iout = 0 µA, All DAC Outputs = Full Scale 5.5 — 30 µA Input Leakage Current (Din, ENB, CLK) Vin = VDD or 0 V 5.5 — 1 µA Vnonl Integral Nonlinearity (Rn Out) See Figure 1 — – 1 1/4 1/4 LSB Vstep Differential Nonlinearity (Rn Out) See Figure 2 — – 3/4 3/4 LSB — 1/4 1 3/4 LSB Iin Voffset Offset from VSS Din = $00, See Figure 1 SWITCHING CHARACTERISTICS (VDD = 2.7 to 5.5 V, Voltages referenced to VSS, TA = – 40 to 85°C, CL = 50 pF, Input tr = tf = 20 ns unless otherwise indicated) Symbol Parameter Min Max Unit twH Positive Pulse Width, CLK (Figures 3 and 4) 166 — ns twL Negative Pulse Width, CLK (Figures 3 and 4) 166 — ns tsu Setup Time, ENB to CLK (Figures 3 and 4) 135 — ns tsu Setup Time, Din to CLK (Figures 3 and 4) 55 — ns th Hold Time, CLK to ENB (Figures 3 and 4) 135 — ns th Hold Time, CLK to Din (Figures 3 and 4) 55 — ns tr, tf Input Rise and Fall Times, CLK — 100 µs Cin Input Capacitance — 10 pF fclk Serial Data Clock Frequency (Refer to twH and twL Above) (Figures 3 and 4) dc 3 MHz MC144112 2 MOTOROLA OUTPUT VOLTAGE @ Rn Out, % (VDD – VSS ) 100 75 Vnonl ACTUAL 50 IDEAL 25 Voffset 0 0 $00 15 $0F 31 $1F 47 $2F 63 $3F PROGRAM STEP LINEARITY ERROR (integral nonlinearity). A measure of how straight a device’s transfer function is, it indicates the worst–case deviation of linearity of the actual transfer function from the best– fit straight line. It is normally specified in parts of an LSB. Figure 1. D/A Transfer Function VRn OUT Vstep Vstep = VDD ± 0.75 VDD 64 64 (For any adjacent pair of digital numbers) DIGITAL NUMBER Figure 2. Definition of Step Size Variance (Differential Nonlinearity) MOTOROLA MC144112 3 ENB 50% tsu CLK th 1 / fclk 50% C1 C2 twH twL D1 – MSB Din CN D2 DN th tsu Figure 3. Serial Input, Positive Clock ENB tsu CLK C1 twL Din th 1 / fclk C2 CN twH D2 D1 – MSB tsu DN th Figure 4. Serial Input, Negative Clock MC144112 4 MOTOROLA R1 Out through R4 Out Resistor Network Outputs PIN DESCRIPTIONS INPUTS Din Data Input Four 6–bit words are entered serially, MSB first, into the digital data input, Din. The last 6–bit word shifted in determines the output level of pin R1 Out. The next–to–last 6–bit word affects pin R2 Out, etc. ENB Negative Logic Enable These are the R–2R resistor network outputs. These outputs may be fed to high–impedance loads. The R value of the resistor network ranges from 7 to 15 kΩ . If not used, an output should be floated. SUPPLY PINS VSS Negative Supply Voltage This pin is usually ground. The ENB pin must be low (active) during the serial load. On the low–to–high transition of ENB, data contained in the shift register is loaded into the latch. VDD Positive Supply Voltage CLK Shift Register Clock The voltage applied to this pin determines the analog output swing. The DAC output voltage range is from approximately VSS to VDD. Data is shifted into the register on the high–to–low transition of CLK. CLK is fed into the D–input of a transparent latch, which is used for inhibiting the clocking of the shift register when ENB is high. The MC144112 usually uses 24 CLK cycles. See Table 1 for additional information. OUTPUTS Dout Data Output The digital data output is primarily used for cascading the DACs and may be fed into Din of the next stage. If not used, the output should be floated. APPLICATIONS INFORMATION For those applications where supply current is critical, any unused DAC channels should be programmed for full–scale output. The unused outputs are floated (no connects). For example, with a 4.5 V supply, the worst case current when all DACs are programmed for zero output is 2.1 mA. This is 2.1 mA for the package; each DAC is drawing 1/4 of this, or 525 µA. If only two channels are needed, minimum supply current is achieved by programming the two unused channels to full–scale output (all ones). In this case, the worst case supply current is approximately two times 525 µA, or 1.05 mA. Table 1. Number of Channels vs Clocks Required Number of Channels Required Minimum Number of Clock Cycles* 1 6 R1 Out 2 12 R1 Out, R2 Out 3 18 R1 Out, R2 Out, R3 Out 4 24 R1 Out, R2 Out, R3 Out, R4 Out Outputs Used * Additional clock cycles can be used, with the leading extra bits being don’t cares. For example, eight clocks can be used if one channel is needed. The first two bits are don’t cares; the last six bits determine the DAC output. MOTOROLA MC144112 5 PACKAGE DIMENSIONS D SUFFIX SOG (SMALL OUTLINE GULL–WING) PACKAGE CASE 751A–03 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A14 8 -B- 0.25 (0.010) P 1 B M 7 G M K D 14 PL 0.25 (0.010) M T B F R X 45° C SEATING PLANE M 7 PL S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0° 7° 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0° 7° 0.299 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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