MOTOROLA MC54HCT241AJ

SEMICONDUCTOR TECHNICAL DATA
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20
1
High–Performance Silicon–Gate CMOS
The MC54/74HCT241A is identical in pinout to the LS241. This device
may be used as a level converter for interfacing TTL or NMOS outputs to
High–Speed CMOS inputs. The HCT241A is an octal noninverting buffer/line
driver/line receiver designed to be used with 3–state memory address
drivers, clock drivers, and other bus–oriented systems. The device has
non–inverted outputs and two output enables. Enable A is active–low and
Enable B is active–high.
The HCT241A is similar in function to the HCT244. See also HCT240.
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
20
1
1
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS–Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1 µA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 118 FETs or 29.5 Equivalent Gates
ORDERING INFORMATION
MC54HCTXXXAJ
MC74HCTXXXAN
MC74HCTXXXADW
A2
A3
A4
2
18
4
16
6
14
8
12
ENABLE A
1
20
VCC
A1
2
19
ENABLE B
YB4
3
18
YA1
A2
4
17
B4
YB3
5
16
YA2
A3
6
15
B3
YB2
7
14
YA3
YA1
YA2
YA3
YA4
DATA INPUTS
B1
B2
B3
B4
11
9
13
7
15
5
17
1
OUTPUT ENABLE A
ENABLES ENABLE B 19
3
YB1
NONINVERTING
OUTPUTS
A4
8
13
B2
YB1
9
12
YA4
GND
10
11
B1
YB2
FUNCTION TABLE
YB3
Inputs
Enable A
YB4
L
L
H
PIN 20 = VCC
PIN 10 = GND
Output
A
YA
L
H
X
L
H
Z
Inputs
Enable B
H
H
L
Output
B
YB
L
H
X
L
H
Z
Z = high impedance
X = don’t care
10/95
 Motorola, Inc. 1995
Ceramic
Plastic
SOIC
PIN ASSIGNMENT
LOGIC DIAGRAM
A1
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
1
REV 6
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MC54/74HCT241A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iin
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
v
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
4.5
5.5
2
2
2
2
2
2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL
|Iout|
6 mA
Vin = VIH or VIL
|Iout|
20 µA
4.5
5.5
0.8
0.8
0.8
0.8
08
0.8
V
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
4.5
3.98
3.84
3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
VOH
Minimum High–Level Output
Voltage
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
6 mA
Iin
IOZ
Maximum Three–State
Leakage Current
Vin = VCC or GND
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
MOTOROLA
Maximum Input Leakage Current
2
V
4.5
0.26
0.33
0.4
5.5
± 0.1
± 1.0
± 1.0
µA
5.5
± 0.5
± 5.0
± 10
µA
5.5
4
40
160
µA
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC54/74HCT241A
∆ICC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 µA
5.5
≥ –55_C
25_C to 125_C
2.9
2.4
mA
NOTES:
1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + Σ∆ICC.
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
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MC54/74HCT241A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
– 55 to
25_C
85_C
125_C
tPLH,
tPHL
Maximum Propagation Delay, A to YA or B to YB
(Figures 1 and 3)
23
29
35
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)
30
38
45
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)
26
33
39
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
12
15
18
ns
Maximum Input Capacitance
10
10
10
pF
Maximum Three–State Output Capacitance (Output in High–Impedance
State)
15
15
15
pF
Symbol
Parameter
Cin
Cout
Unit
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Enabled Output)*
pF
55
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
3V
ENABLE A
1.3 V
GND
3V
tr
tf
INPUT
A OR B
ENABLE B
GND
3V
2.7 V
1.3 V
0.3 V
tPZL
OUTPUT Y
tPHL
90%
1.3 V
10%
tTHL
OUTPUT Y
10%
VOL
90%
VOH
HIGH
IMPEDANCE
tPHZ
1.3 V
Figure 1.
Figure 2.
TEST POINT
TEST POINT
OUTPUT
OUTPUT
DEVICE
UNDER
TEST
CL*
* Includes all probe and jig capacitance
1 kΩ
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
* Includes all probe and jig capacitance
Figure 3. Test Circuit
MOTOROLA
HIGH
IMPEDANCE
1.3 V
tPZH
tTLH
DEVICE
UNDER
TEST
tPLZ
GND
tPLH
OUTPUT
YA OR YB
1.3 V
Figure 4. Test Circuit
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HCT241A
LOGIC DETAIL
TO THREE OTHER
“A” BUFFERS
TO THREE OTHER
“B” BUFFERS
TWO OF 8 BUFFERS
VCC
INPUT
A
YA
VCC
INPUT
B
YB
ENABLE A
OUTPUT
ENABLES
ENABLE B
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
MC54/74HCT241A
OUTLINE DIMENSIONS
20
11
1
10
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
A
L
C
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
N
H
G
D
J
K
M
MILLIMETERS
MIN
MAX
23.88
25.15
6.60
7.49
3.81
5.08
0.38
0.56
1.40
1.65
2.54 BSC
0.51
1.27
0.20
0.30
3.18
4.06
7.62 BSC
0_
15 _
0.25
1.02
INCHES
MIN
MAX
0.940
0.990
0.260
0.295
0.150
0.200
0.015
0.022
0.055
0.065
0.100 BSC
0.020
0.050
0.008
0.012
0.125
0.160
0.300 BSC
0_
15_
0.010
0.040
SEATING
PLANE
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
–T–
K
SEATING
PLANE
M
N
E
G
F
J
D
M
T A
11
–B–
10X
P
0.010 (0.25)
1
M
B
M
10
20X
D
0.010 (0.25)
M
T A
B
S
J
S
F
R
C
–T–
18X
G
K
SEATING
PLANE
M
T B
M
M
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
–A–
20
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
MOTOROLA
DIM
A
B
C
D
E
F
G
J
K
L
M
N
X 45 _
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65
12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.499
0.510
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
M
6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HCT241A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
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associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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High–Speed CMOS Logic Data
DL129 — Rev 6
◊
CODELINE
*MC54/74HCT241A/D*
7
MC54/74HCT241A/D
MOTOROLA