MOTOROLA MC74HC85N

SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
The MC74HC85 is identical in pinout and function to the LS85. This device
is similar in function to the MM74C85 and L85, but has a different pinout. The
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This 4–Bit Magnitude Comparator compares two 4–bit nibbles and gives a
high voltage level on either the A > Bout, A = Bout, or A < Bout output, leaving
the other two at a low voltage level. This device also has A > Bin, A = Bin, and
A < Bin inputs, eliminating the need for external gates when cascading.
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
16
1
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
16
1
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 248 FETs or 62 Equivalent Gates
ORDERING INFORMATION
MC74HCXXN
MC74HCXXDT
PIN ASSIGNMENT
B3
A
LOGIC DIAGRAM
t Bin
A = Bin
u Bin
A u Bout
A
A0
A1
A2
DATA
INPUTS
A3
12
A = Bout
13
A
15
5
B0
B1
B2
B3
A > Bin
CASCADING
INPUTS
10
A = Bin
A < Bin
9
6
11
7
14
A > Bout
A = Bout
t Bout
GND
COMPARISON
OUTPUTS
A < Bout
1
4
3
2
PIN 16 = VCC
PIN 8 = GND
10/95
 Motorola, Inc. 1995
1
Plastic
TSSOP
REV 6
1
16
VCC
2
15
A3
3
14
B2
4
13
A2
5
12
A1
6
11
B1
7
10
A0
8
9
B0
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MC74HC85
MAXIMUM RATINGS*
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
Value
Unit
– 0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
Iin
TL
Plastic DIP†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
_C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or TSSOP)
260
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
DC Supply Voltage (Referenced to GND)
Max
Unit
2.0
6.0
V
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
85_C
125_C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
VOH
Vin = VIH or VIL |Iout|
|Iout|
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
20 µA
Vin = VIH or VIL |Iout|
|Iout|
Iin
ICC
4.0 mA
5.2 mA
4.0 mA
5.2 mA
V
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
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MC74HC85
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
– 55 to
25_C
tPLH,
tPHL
Maximum Propagation Delay, Inputs A or B to Outputs A> B
or A < B
(Figures 1 and 2)
2.0
4.5
6.0
tPLH,
tPHL
Maximum Propagation Delay, Inputs A or B to Output A = B
(Figures 1 and 2)
tPLH,
tPHL
85_C
125_C
230
46
39
290
58
49
345
69
59
ns
2.0
4.5
6.0
200
40
34
250
50
43
300
60
51
ns
Maximum Propagation Delay, Inputs A < B or A = B to Output A > B
(Figures 1 and 2)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLH,
tPHL
Maximum Propagation Delay, Inputs A > B or A = B to Output A < B
(Figures 1 and 2)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLH,
tPHL
Maximum Propagation Delay, Input A = B to Output A = B
(Figures 1 and 2)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Maximum Input Capacitance
—
10
10
10
pF
Symbol
Parameter
Cin
Unit
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Package)*
pF
50
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
tr
INPUTS
tf
10%
VCC
90%
50%
GND
tPHL
tPLH
TEST POINT
50%
OUTPUTS
OUTPUT
tPHL
DEVICE
UNDER
TEST
tPLH
90%
50%
10%
OUTPUTS
tTHL
tTLH
* Includes all probe and jig capacitance
Figure 1. Switching Waveforms
High–Speed CMOS Logic Data
DL129 — Rev 6
CL*
Figure 2. Test Circuit
3
MOTOROLA
MC74HC85
PIN DESCRIPTIONS
INPUTS
outputs should be tied to A < B in , A = B in, and A > B in, respectively, of the succeeding stage.
A0, A1, A2, A3 (Pins 10, 12, 13, 15)
OUTPUTS
Data Nibble A Inputs. The data nibble present at these inputs is compared to Data Nibble B. A3 is the most significant
bit and A0 is the least significant bit.
A > Bout (Pin 5)
A–Greater–Than–B Output. This output is at a high voltage level when Nibble A is greater than Nibble B, regardless
of the data present at the cascading inputs. This output is
also high when Nibble A equals Nibble B and the A > B in input is high (A < B in and A = B in are at a low voltage level).
B0, B1, B2, B3 (Pins 9, 11, 14, 1)
Data Nibble B Inputs. The data nibble present at these inputs is compared to Data Nibble A. B3 is the most significant
bit and B0 is the least significant bit.
A = Bout (Pin 6)
A–Equals–B Output. This output is high when Nibble A
equals Nibble B and the A = B in input is high. A < B in and
A > Bin have no effect when the comparator is in this condition and A = B in is at a high voltage level.
CONTROLS
A > B in , A = B in , A < B in (Pins 4, 3, 2)
Cascading Inputs. These inputs determine the states of
the outputs only when Data Nibble A equals Data Nibble B.
The A = B in input overrides both the A > B in and A < B in
inputs.
For single stage operation or for the least significant stage
in cascaded operation, the A < B in and A > B in inputs should
be tied to ground and the A = Bin input tied to V CC. Between
cascaded comparators, the A < B out, A = B out , and A > B out
A < Bout (Pin 7)
A–Less–Than–B Output. This output is at a high voltage
level when Nibble A is less than Nibble B, regardless of data
present at the cascading inputs. This output is also high
when Nibble A equals Nibble B and the A < B in input is high
(A > B in and A = B in are at a low voltage level).
FUNCTION TABLE
Data Inputs
Cascading Inputs
Output
A3, B3
A2, B2
A1, B1
A0, B0
A > Bin
A = Bin
A < Bin
A > Bout
A = Bout
A < Bout
A3 > B3
A3 < B3
A3 = B3
A3 = B3
X
X
A2 > B2
A2 < B2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
L
L
L
L
H
L
H
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A1 > B1
A1 < B1
A1 = B1
A1 = B1
X
X
A0 > B0
A0 < B0
X
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
L
L
L
L
H
L
H
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A3 = B3
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A2 = B2
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A1 = B1
A0 = B0
A0 = B0
A0 = B0
A0 = B0
A0 = B0
L
L
H
H
X
L
L
L
L
H
L
H
L
H
X
H
L
H
L
L
L
L
L
L
H
H
H
L
L
L
X = Don’t Care
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC85
EXPANDED LOGIC PROGRAM
1
B3
15
A3
5
A > Bout
B2 14
A2
13
B1 11
A1 12
7
B0
A < Bout
9
A0
A < Bin 2
6
A = Bin
3
A > Bin
4
High–Speed CMOS Logic Data
DL129 — Rev 6
5
A = Bout
MOTOROLA
MC74HC85
TYPICAL APPLICATION
CASCADING COMPARATORS
GND
A > Bin
VCC
GND
A = Bin
A < Bin
A0
A1
A2
LEAST–
SIGNIFICANT
4–BIT
NIBBLES
HC85
A3
B0
B1
B2
B3
A > Bout
A > Bin
A = Bout
A = Bin
A < Bout
A < Bin
A4
A5
HC85
A6
A7
B4
B5
B6
A > Bout
A > Bin
A = Bout
A < Bout
A = Bin
A < Bin
B7
A8
A9
HC85
A10
MOST–
SIGNIFICANT
4–BIT
NIBBLES
A11
B8
A > Bout
B9
A = Bout
B10
A < Bout
OUTPUTS
B11
MOTOROLA
6
High–Speed CMOS Logic Data
DL129 — Rev 6
MC74HC85
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A
–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
DIM
A
B
C
D
F
G
H
J
K
L
M
S
L
S
–T
–
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
M
J
G
T A
M
INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0°
0°
10°
10°
0.020 0.040
0.51
1.01
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
S
S
K
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH OR
GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED AT
DATUM PLANE –W–.
M
N
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
H
D
High–Speed CMOS Logic Data
DL129 — Rev 6
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
G
7
MOTOROLA
MC74HC85
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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◊
CODELINE
8
*MC74HC85/D*
MC74HC85/D
High–Speed CMOS Logic Data
DL129 — Rev 6