MP3274 Fault Protected 32 Channel, 12-Bit Data Acquisition Subsystem FEATURES • Complete 32-Channel 12-Bit A/D Converter with Sample & Hold, Reference, Clock and 3-State Outputs • Fast Conversion, less than 15µS • Microprocessor Bus Interface • Parallel or Serial Data Output Modes • 65 ns Bus Access Time • Remote Analog Ground Sensing • Overvoltage Protected Input (50 V over the Supply Voltages) • Precision Reference for Long Term Stability and Low Gain T.C. • Guaranteed Linearity Over Temperature • Guaranteed Performance at +12/–5 V, ±12 & ±15 V • Low Power (3 mW per Channel Typical) • 16 Channel Version: MP3276 & MP3275 GENERAL DESCRIPTION The MP3274 is a complete 32-channel, 12-bit Data Acquisition Subsystem with 3-state output buffers for direct interfacing to 16-bit microprocessor buses. Implemented using an advanced BiCMOS process, the converter combines a 32-channel passive overvoltage protected multiplexer instrumentation amp, a sample & hold, a SAR, a 12-bit decoded D/A, a comparator, a precision reference and the control logic to achieve an accurate, repeated conversion in less than 15µs, and a mux/instrumentation amp settling period of less than 10µs. condition can exist on unselected channels without disrupting the measured channel or operation of the MP3274! The internal 4 V reference has sufficient output current to provide other system reference needs. Precision thin film scaling and offset resistors are laser trimmed to provide for less than 2 LSB INL for +10 V inputs on all channels. In addition, the MP3274 will output either full scale (0111 ....) for overrange and – full scale (1000....) for underrange conditions. This greatly simplifies microprocessor software development. A unique input design provides input overvoltage protection to 50 V over the supply voltages. Therefore, an overvoltage SIMPLIFIED BLOCK DIAGRAM GND REF. AB0-4 (5 pins) 5 AIN0-31 (32 pins) 32 Ch. MUX VDD VCC AGND – + Comp REF IN /2 32 AGND2 VREF REF IN REF OUT VDAC 4V REF 12 CLK SAR 12 AGND3 Control Logic Latch/ Shift Register 3-State Drivers DGND VEE AGND WR RD CS DB0-DB11 ADEN STL STS Rev. 4.00 1 PXS MP3274 ORDERING INFORMATION DNL (LSB) Package Type Temperature Range PGA –40 to +85°C MP3274AG –55 to +125°C 2 2 PGA MP3274SG* 2 PLCC –40 to +85°C 2 MP3274AP 2 2 Part No. INL (LSB) *Contact factory for non-compliant military processing PIN CONFIGURATIONS 1 See the following page for pin numbers and descriptions and page 11 for package dimensions and connection table See the following page for pin numbers and descriptions Index Mark 68 Pin PGA G68 68 Pin PLCC P68 Rev. 4.00 2 MP3274 PIN OUT DEFINITIONS PLCC PIN NO. PGA PADS NAME PLCC PIN NO. DESCRIPTION PGA PADS NAME DESCRIPTION 61 1 VEE Negative Analog Supply 27 35 ADEN Address Enable 62 2 AIN24 Analog Input 24 28 36 AB4 Channel Address 4 63 3 AIN25 Analog Input 25 29 37 AB3 Channel Address 3 64 4 AIN26 Analog Input 26 30 38 AB2 Channel Address 2 65 5 AIN27 Analog Input 27 31 39 AB1 Channel Address 1 66 6 AIN28 Analog Input 28 32 40 AB0 Channel Address 0 67 7 AIN29 Analog Input 29 33 41 VDD Positive Digital Supply 68 8 AIN30 Analog Input 30 34 42 VCC Positive Analog Supply 1 9 AIN31 Analog Input 31 35 43 AIN0 Analog Input 0 2 10 GND Ref. Input Ground Reference 36 44 AIN1 Analog Input 1 3 11 AGND ADC Analog Ground 37 45 AIN2 Analog Input 2 4 12 Ref In Reference Input 38 46 AIN3 Analog Input 3 5 13 Ref Out Reference Output 39 47 AIN4 Analog Input 4 6 14 AGND3 Reference Analog Ground 40 48 AIN5 Analog Input 5 7 15 DGND Digital Ground 41 49 AIN6 Analog Input 6 8 16 DB0/SDC Data Output Bit 0/Serial Data Clock 42 50 AIN7 Analog Input 7 43 51 N/C No Connection 9 17 N/C No Connection 44 52 18 DB1 Data Output Bit 1 AIN8 Analog Input 8 10 45 53 19 DB2 Data Output Bit 2 AIN9 Analog Input 9 11 46 54 20 DB3 Data Output Bit 3 AIN10 Analog Input 10 12 47 55 21 DB4 Data Output Bit 4 AIN11 Analog Input 11 13 48 56 22 DB5 Data Output Bit 5 AIN12 Analog Input 12 14 49 57 23 DB6 Data Output Bit 6 AIN13 Analog Input 13 15 50 58 24 DB7 Data Output Bit 7 AIN14 Analog Input 14 16 51 59 25 DB8 Data Output Bit 8 AIN15 Analog Input 15 17 52 60 AGND2 Analog Ground Mux Return 18 26 DB9 Data Output Bit 9 53 61 27 DB10 Data Output Bit 10 AIN16 Analog Input 16 19 54 62 28 DB11/SDO Data Output Bit 11/Serial Data Out AIN17 Analog Input 17 20 55 63 AIN18 Analog Input 18 21 29 STS Conversion Status 56 64 AIN19 Analog Input 19 22 30 STL Mux Settling Status 57 65 AIN20 Analog Input 20 23 31 PXS Parallel/XSerial 58 66 AIN21 Analog Input 21 24 32 RD Read Enable 59 67 AIN22 Analog Input 22 25 33 CS Chip Select 60 68 AIN23 Analog Input 23 26 34 WR Write Enable Rev. 4.00 3 MP3274 ELECTRICAL CHARACTERISTICS TABLE Unless Otherwise Specified: VDD = 5 V, VCC = 15 V, VEE = –15 V, GNDRef = 0 V, TA = 25°C, VREFIN = Ref Out Parameter Resolution (All Grades) Symbol Min N 12 25°C Typ Max Tmin to Tmax Min Max Units 12 Test Conditions/Comments Bits KEY FEATURES Resolution Conversion Time, Per Channel 12 tCONVR 15 12 15 Bits µs ACCURACY (A, S Grade)1 Differential Non-Linearity Integral Non-Linearity DNL INL 3/4 1 2 2 2 2 LSB LSB Zero Code Error Full Scale Error EZS EFS 2 5 0.1 0.35 10 0.5 LSB % POWER SUPPLY REJECTION Best Fit Line (Max INL – Min INL)/2 fff to 000 [hex] transition VREFIN = 4.000 V Max change in Full Scale Calibration VCC = 15 V 1.5 V or 12 V 0.6 V VDD = 5 V 0.25 V VEE = –15 V 1.5 V or –12 V 0.6 V or –5 V 0.25 V 1 2 1 2.5 LSB LSB 1 1 LSB REFERENCE VOLTAGES Ref. Voltage Input Ref. Voltage Output Ref. Source Current Ref. Sink Current Ref In Ref Out 3.6 3.975 3.0 4.4 4.025 4.0 20 V 3.0 RIN 5KΩ; VDD = 5 V mA µA ANALOG INPUT2 Input Voltage Range5 Ground Reference CM Range CM RR Input Resistance Input Capacitance Aperture Delay VIN GND Ref. –10 –3 RIN CIN tAP 100 Channel-to-Channel Isolation2 10 –10 10 3 –3 3 TBD 130 5 180 –80 100 –70 V V LSB/V kΩ pF ns dB From WR low to high after STL high to low DC DIGITAL INPUTS CS, WR, RD AB0-AB4, ADEN Logical “1” Voltage Logical “0” Voltage Leakage Currents6 Input Capacitance2 VIH VIL IIN 2.4 –0.5 –5 5.5 0.8 5 5 Rev. 4.00 4 2.4 –0.5 –10 5.5 0.8 10 V V µA pF VIN=GND to VDD MP3274 ELECTRICAL CHARACTERISTICS TABLE (CONT’D) Description Symbol Min 25°C Typ Max Tmin to Tmax Min Max Units COUT=15 pF DIGITAL OUTPUTS (Data Format 2’s Complement) DB0/SDC–DB11/SDO, STS, STL Logical “1” Voltage Logical “0” Voltage Tristate Leakage Conditions VOH VOL IOZ 4.0 2.4 –5 0.4 5 –5 0.4 5 +4.5 +11.4 –4.75 +5.5 +16.5 –16.5 +4.5 +11.4 –4.75 +5.5 +16.5 –16.5 V V µA ISOURCE = 0.5 mA ISINK = 1.6 mA VOUT=GND to VDD V V V Tested at –11.4 and –16.5 only POWER SUPPLIES Operating Range VDD VCC VEE Operating Current IDD ICC IEE Power Dissipation 2 5 1.5 110 7 8 3 200 7 8 3 200 mA mA mA mW NOTES 1 Tester measures code transitions by dithering the voltage of the analog input (VIN). The difference between the measured and the ideal code width is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage 2 Guaranteed. Not tested. 3 Specified values guarantee functionality. Refer to other parameters for accuracy. 4 Input bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within the specified bandwidth. 5 All channel input pins and ground reference pin have protection which becomes active above 60 V. 6 All digital inputs have diodes to VDD and AGND. Input DC currents will not exceed specified limits for any input voltage between GND and VDD. Specifications are subject to change without notice ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2 VCC to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +16.5 V VEE to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to –16.5 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 V Digital Inputs/Outputs to DGND . . . . . . . . . . . . . . . . . . . . . –0.5 V to VLOGIC +0.5 V Analog Inputs (AIN0 – AIN31, GND REF) to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60 V REF OUT . . . . . . . . . . . . . . . . . . . Indefinite short to DGND, Momentary short to VCC Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C Package Power Dissipation Rating to 75°C PGA, PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1800 mW Derates above 75°C . . . . . . . . . . . . . . . . . . . . . 25 mW/°C Lead Temperature, Soldering . . . . . . . . . . . . 300°C, 10 Sec Storage Temperature (Ceramic) . . . . . . . . –65°C to +150°C NOTES: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All logic inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100µs. 1 Rev. 4.00 5 MP3274 PRODUCT INFORMATION Basic Description The MP3274 is a fault protected data acquisition subsystem available in monolithic form. This product contains all of the circuitry necessary to acquire 32 channels of differential or singleended analog signals at 10 V input range and 15kHz bandwidth. Connections to power, the analog input signals and the digital system are all that is required. The MP3274’s input circuitry is protected against active input signals present with the MP3274 power off. This is also the case for any channel exceed- ing the MP3274 analog input dynamic range without interfering with the channel being digitized. The channel address and channel conversion can be managed in two ways: random channel conversion or same channel conversion. Circuitry on the chip adds a MUX/instrumentation amp settling delay, when a new channel is selected (ADEN = 1). Conversion start is initiated without delay for the single-channel case (ADEN = 0). Data is available in either parallel or serial format. TIMING Control and Timing Considerations – Parallel Mode (PXS = 1) The MP3274 can be operated in the stand-alone mode, with one line for control and everything else hard-wired; or under microprocessor control, where changes can be made dynamically. There are 4 control lines: ADEN, CS, WR, and RD with their functions described in Table 1. CS WR RD ADEN Data STL PXS is the control pin for formatting data for serial or parallel control. STS Comments ADC Channel Select and Start Convert (See Figure 1. and Table 2.) 1 0 0 0 0 0 0 X ↓ ↓ 0 ↑ 1 1 X 1 1 1 1 1 1 X 0 1 X X X X –– Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 ↑ 1 0 ↓ 0 0 0 0 0 ↑ ↑ ↓ No operation No operation if ADEN = 0 Input MUX channel selected, STL set on WR falling edge MUX select disabled Start convert on WR rising edge Start convert on STL falling edge STS goes low at end of conversion Read ADC Data – Parallel Output Mode (PXS = 1) (See Figure 2. and Table 3.) 0 0 0 0 0 0 0 1 X X 1 X ↓ 0 ↑ X 0 0 X X X X X 0 –– ADC Hi-Z Hi-Z Last ADC Hi-Z 0 0 0 0 1 0 0 0 0 1 0 ↑ 0 X ADC 0 ↓ Data outputs enabled Data from previous conversion on data bus Data outputs disabled Data/RD disabled while STS high Data from last conversion on data bus STL, MUX select disabled with ADEN = 0, data outputs disabled on STS rising edge New data appears on data bus on falling edge of STS Note 1: If RD = 1, data outputs remain high impedance. It is recommended that RD will not change during a conversion in order to reduce noise. It is further recommended that RD = 1 during conversion to reject any noise present on the data bus. Table 1. Logic Truth Table for PXS = 1 (Parallel Mode) Rev. 4.00 6 MP3274 2. ADEN = 0. At the falling edge of WR the data present at the address is ignored and the channel selected during the previous conversion remains selected. In this case the track and hold settling time is omitted and STL never goes high. At the rising edge of WR the input signal is sampled, and conversion is started. The MP3274 is easily interfaced to a wide variety of microprocessors and other digital systems. Discussion of the timing requirements of the MP3274 control signals will provide the system designer with useful insight into the operation of the device. Figure 1. shows a complete timing diagram for the MP3274 convert start operation. There are two possible states that the data outputs could be in during a conversion. Either WR or CS may be used to initiate a conversion. We recommend using WR as used in Figure 1. It is quieter and has less propagation delay than CS. If CS is used to trigger the conversion the specified set-up times will be longer. 1. If RD is held high during a conversion the outputs would remain high impedance throughout the conversion. This is the preferred method of operation as any noise present on the data bus is rejected. A conversion is started by taking WR low, then high again (conversion is enabled on the rising edge of WR). There are two possible conditions that will affect conversion timing. 2. If RD and CS are held low during a conversion, the data present will be from the previous conversion until the present conversion is completed when STS returns low. The data from the new conversion will appear on the outputs. The state of RD or CS should not change during a conversion. 1. ADEN = 1. At the falling edge of WR, the input channel is determined by the data present on the address bits. The track and hold begins to settle after which STL returns low, indicating that the multiplexer and the buffer amp have settled to less than 1/2 LSB of final value. If the rising edge of WR returns high prior to STL going low, conversion will begin on the falling edge of STL. If the rising edge of WR is delayed until after STL returns low, the input signal is sampled and the conversion is started at the rising edge of WR giving the user better control of the sampling time. ADC Write Timing Time Interval 25°C Once a conversion is started and the STL or STS line goes high, convert start commands will be ignored until the conversion cycle is completed. The output data buffers cannot be enabled during conversion. In addition, all inputs and outputs which change during conversion can introduce noise, and should be avoided when possible. Tmin to Tmax Limits Comments/Test Conditions ADC Control Timing CS to WR Set-Up Time CS to WR Hold Time Address to WR Set-Up Time Address to WR Hold Time WR Pulse Width ADEN to WR Set-Up Time t1 t2 t3 t4 t5 t6 0 0 0 0 80 0 0 0 0 80 0 ns min ns min ns min ns min ns min ns min WR to STL Delay t7 150 150 ns max STL High (mux/amp settle) STL to STS Low (Converting) WR to STS High (ADEN = 0) WR to STS Low (ADEN = 1) STS High to Bus Relinquish Time STS Low to Data Valid (RD = 0) t8 t9 t12 t10 t13 t14 10 15 200 15 150 50 15 20 250 20 150 50 µs max µs max ns max µs max ns max ns max ADC Conversion Timing Table 2. ADC Write Timing (See Figure 1.) Rev. 4.00 7 Load ckt of Figure 5, CL = 20 pF, ADEN = 1 Load ckt of Figure 5, CL = 20 pF Load ckt of Figure 5, CL = 20 pF STL = 0 when ADEN = 0 Load ckt of Figure 4 Load ckt of Figure 3, CL = 20 pF MP3274 t2 t1 CS WR t5 t3 t4 ADDRESS ADEN t6 STL t7 t8 t9 t 14 t 12 STS t 10 t 11 DB0-DB11 RD = 0 Previous ADC Data New ADC Data t 13 DB0-DB11 RD = 1 HIGH Z Figure 1. Timing for ADC Channel Select Start Conversion ADC Read Timing Time Interval 25°C CS to RD Set-Up Time CS to RD Hold Time RD to Data Valid Delay t15 t16 t17 Bus Relinquish Time after RD High RD Pulse Width t18 0 0 100 150 100 t19 100 Tmin to Tmax Limits 0 0 150 200 150 ns min ns min ns max ns max ns max 150 ns min Table 3. ADC Read Timing (See Figure 2.) CS t 15 t 19 t 16 RD DATA Valid t 17 t 18 Figure 2. Timing for ADC Read Rev. 4.00 8 Comments/Test Conditions Load ckt of Figure 3., CL = 20 pF Load ckt of Figure 3., CL = 100 pF Load ckt of Figure 4. MP3274 +5 V +5 V 3k DB N 3k DB N DB N 3k CL 3k CL a. High-Z to VON 10pF a. VON to High-Z b. High-Z to VOL DB N 10pF b. VOL to High-Z Figure 4. Load Circuit for Bus Relinquish Time Test Figure 3. Load Circuit for Data Access Time Test STL, STS CL DGND Figure 5. Load Circuit for WR to STS Delay Serial Data Output Mode (PXS = 0) The MP3274 output data is available in serial form when PXS = 0 prior to the RD high-to-low transition. When PXS = 0, the DB11/SDO pin functions as the serial data output. The DB0/SDC pin functions as the serial clock input and all other data outputs are 3-stated. The control pin functions (ADEN, CS, WR, and RD) are the same as the parallel mode of operation. Further information regarding serial control and timing is shown in Figure 6., Table 4. and Table 5. For a minimum interconnect serial environment, the channel address state can be generated in at least two ways, using an address counter, or using an address serial to parallel converter. WR can then be used as the counter clock or shift register load signal as well as the A/D converter start convert signal on the rising edge. (Note that the falling edge loads the address present at the address port.) The serial data output sequence is MSB (DB11) first to LSB (DB0) last. The MSB (DB11) data bit appears at DB11/SDO when STS goes low. The second most significant bit appears at DB11/SDO on the next DB0/SDC high-to-low transition. The LSB (DB0) is present at DB11/SDO on the 11th SDC high-to-low transition. STS ÇÇÇÇÇ ÇÇÇÇÇ t21 t22 See Table 4 SDC t20 DB11/SDO DB11 (MSB) DB10 SDC should be in a high state during the STS high period. SDC can make the first high to low transition after t21. In normal use it is assumed that PXS is hardwired low. However, if the mode of operation is changed, PXS must go low prior to RD going low. Figure 6. Serial Data Mode Timing Rev. 4.00 9 MP3274 Serial Data Output Timing Time Interval 25°C Tmin to Tmax t20 50 50 ns max Load Ckt 4 of Figure 3. t21 t22 50 150 ns 200 ns 80 200 250 ns max ns max ns max Load ckt of Figure 3., CL = 20pF Load ckt of Figure 3., CL = 100pF STS low to SDO (DB11) Valid, RD = 0 Minimum clock high pulse width SDC low to data valid delay Limits Comments/Test Conditions Table 4. Serial Data Output Mode Timing (See Figure 6.) CS PXS WR RD ADEN Data STL STS DB0/SDC Comments ADC Channel Select and Start Convert 1 0 0 0 X ↓ 0 0 X X ↓ ↓ X 1 1 1 X X 0 1 –– Hi-Z Hi-Z Hi-Z 0 0 0 ↑ 0 0 0 0 X X X X 0 0 0 0 0 0 0 0 0 ↑ 1 1 1 1 1 1 X X X X Hi-Z Hi-Z Hi-Z Hi-Z 1 0 ↓ 0 0 ↑ ↑ ↓ X X X X No Operation Serial mode enabled (1) No operation if ADEN = 0 Input MUX channel selected, STL set on falling edge of WR MUX select disabled Start convert on WR rising edge Start convert on STL falling edge STS goes low at end of conversion Read ADC Data (See Table 4. and Figure 6.) 0 0 1 ↓ X –– 0 0 1 0 0 0 0 X X X 0 X X MSB (DB11) DB10 0 0 0 0 1 ↓ 0 0 0 0 0 0 X X X 0 0 0 X X X DB10 DB10 DB9 0 0 0 0 0 0 0 ↑ ↓ 0 0 0 X X 1 ↑ X X X Hi-Z Hi-Z 0 0 0 1 X X 0 X 0 0 Hi-Z 0 ↑ 1 0 0 0 X MSB (DB11) 0 ↓ 1 Serial output (DB11/SDO) and serial clock input (DB0/SDC) enabled MSB data available at DB11/SDO Next significant bit shifted out to DB11/SDO No Operation No Operation Next significant bit shifted out to DB11/SDO Data outputs/SDC input disabled Data outputs/RD disabled when STS = 1 STL, MUX select disabled when ADEN = 0 New data appears at DB11/SDO on falling edge of STS Note 1: If RD = 1, data outputs remain high impedance. It is recommended that RD will not change during a conversion in order to reduce noise. It is further recommended that RD = 1 during conversion to reject any noise present on the data bus. Table 5. Logic Truth Table – Serial Data Output Mode 2’s Complement Output Code (Hexidecimal) 0111 0000 1111 1000 1111 0000 1111 0000 1110 (7fe) to 0000 (000) to 1111 (fff) to 0000(800) to 0111 0000 0000 1000 1111 0000 0000 0000 1111 (7ff) 0001 (001) 0000 (000) 0001 (801) Ideal Transition Voltage +FS – 1 1/2 LSB 0 V +1/2 LSB 0 V –1/2 LSB –FS +1/2 LSB Table 6. Key Output Codes vs. Input Voltage (2’s Complement Code) Rev. 4.00 10 MP3274 APPLICATION INFORMATION The MP3274 is a complete A/D converter system, with its own built-in reference and clock. It may be used by itself (“standalone” operation), or it may be interfaced with a microprocessor which can control both conversion and formatting of output. Ground Reference The ground reference pin can be used for remote ground sensing of a common mode input signal with a maximum 6 V p-p around AGND. Successful application of the MP3274 requires careful attention to four main areas: 1) 2) 3) 4) This common input can also be used to dither each input’s “zero”. By averaging multiple conversions digitally, higher resolution for each input conversion can be obtained. Patterns for this dither can be a ramp, a stair step, or white noise. Physical layout. Connection/Trimming according to mode of operation. Conditioning of input signals. Control and Timing considerations. Physical Layout 130k The 12-bit accuracy of the MP3274 represents a dynamic range of 72dB. In order that this be preserved, thorough precautions must be taken to avoid any interfering signals, whether conducted or radiated. • • 26k 1 of 32 COMP GND Ref. Avoid placing the chip and its analog signals near logic traces. In general, using a double sided printed circuit card with a good ground plane on the component side is recommended. Routing analog signals between ground traces will help isolate digital control logic. If these lines cross, do so at right angles. The GND Ref. is the positive terminal of the MUX/Instrumentation amplifier and will provide common mode noise rejection. It should be close to and shielded together with the channel inputs in order to take advantage of this feature. 130k 26k S A R 1/2 VREF VDAC 12 Figure 7. Equivalent Input Circuit Power supplies should be quiet and well regulated. Grounds should be tied together at the package and back to the system ground with a single path. Bypass the supplies at the device with a 0.01 to 0.1µF ceramic cap and a 10-47 µF tantalum type, in parallel. Quasi Differential Sampling Method 1 For remote ground sensing where the remote ground does not change more than 3 V from the A/D ground, connect GND Ref to the remote ground. “Stand-Alone” Operation The MP3274 can be used in “stand-alone” operation, which is useful in systems not requiring full computer bus interface capability. This operation is available for either parallel or serial mode. Method 2 Where Method 1 applies to each channel or group of channels, add a mux to allow connecting the appropriate ground to GND Ref. For this operation, CS = 0, ADEN = 1, and conversion is controlled by WR. The 3-state buffers are enabled when RD goes low. There are two possible conditions that the 3-state buffers could be in during a conversion. If RD goes low prior to WR, the output buffers are enabled and the data from the previous conversion is available at the outputs during STL = 1. At the end of the present conversion which is initiated at the rising edge of WR, STS returns low and the new conversion result is placed on the output data buffers. Method 3 Use two parts. Tie both GND Ref pins together and connect this node to the “common” remote GND. Control the sample point by connecting each STL through an “OR” gate whose output is “NAND” connect with WR (inverted WR). Use this output as WR to both WR inputs. By controlling the WR, sample delay differences between the two converters is minimized. Two parts from the same date code will further minimize this difference. Treat one A/D as the (+) terminal and the other as the (–) terminal of the differential signal. Now the difference can be taken digitally. If WR goes low prior to RD the data buffers remain in a high impedance state and conversion is initiated at the rising edge of WR. Upon the end of the conversion the STS returns low and the conversion result is placed on the output data buffers. Rev. 4.00 11 MP3274 68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) P68 D D1 Seating Plane A2 1 D D1 B e1 C D3 A1 A INCHES SYMBOL A MILLIMETERS MIN MAX MIN MAX .165 .180 4.19 4.57 A1 .095 .118 2.51 3.00 A2 0.146 0.154 3.71 3.91 B 0.013 0.021 0.330 0.553 C 0.097 0.0103 0.246 0.261 D .985 .995 25.02 25.27 D1 (1) .950 .954 24.13 24.23 D2 .890 .930 22.60 23.62 D3 0.800 Ref 20.32 Ref. e1 0.050 BSC 1.27 BSC Note: (1) Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in. Rev. 4.00 12 D2 MP3274 68 LEAD PIN GRID ARRAY (PGA) G68 D D1 A e ÉÉ ÉÉ É É ÉÉ ÉÉ D b L K J H e G D1 F E C B A 1 Index Mark D IP 2 3 4 5 6 7 8 9 10 11 Q Pin 1 L1 IP = Index Pin, not connected Seating Plane INCHES SYMBOL MIN MAX A 0.079 0.095 b 0.016 0.020 MILLIMETERS MIN MAX PAD PIN PAD PIN 2.00 2.41 0.406 0.508 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 B2 B1 C2 C1 D2 D1 E2 E1 F2 F1 G2 G1 H2 H1 J2 J1 K1 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 K2 L2 K3 L3 K4 L4 K5 L5 K6 L6 K7 L7 K8 L8 K9 L9 L10 D 1.086 1.110 27.6 28.2 D1 0.788 0.812 20.0 20.6 e L1 Q 0.100 typ. 0.170 0.190 0.050 typ. CONNECTION TABLE 2.54 typ. 4.32 4.83 1.27 typ. PAD PIN 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 K10 K11 J10 J11 H10 H11 G10 G11 F10 F11 E10 E11 D10 D11 C10 C11 B11 PAD PIN 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 B10 A10 B9 A9 B8 A8 B7 A7 B6 A6 B5 A5 B4 A4 B3 A3 A2 Note: The letters A-H and numbers 1-8 are the coordinates of a grid. For example, pin 1 is at the intersections of the “B” vertical line and the “2” horizontal line. Rev. 4.00 13 MP3274 Notes Rev. 4.00 14 MP3274 Notes Rev. 4.00 15 MP3274 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 4.00 16