E2U0034-28-82 ¡ Semiconductor MSM7586-01/03 ¡ Semiconductor This version: Aug. 1998 MSM7586-01/03 Previous version: Nov. 1996 p/4 Shift QPSK MODEM/ADPCM CODEC GENERAL DESCRIPTION The MSM7586 is a CMOS IC developed for use with digital cordless telephones. The device provides a p/4 shift QPSK modem function and a CODEC function which performs transcoding between the voice band analog signal and 32 kbps ADPCM data. The MSM7586 performs DTMF tone and several types of tone generation, transmit/receive data, mute and gain control, side-tone pass and its gain control, and VOX function. FEATURES (p/4 Shift QPSK Modem Unit) • 384 kbps transmission speed • Built-in root Nyquist digital filter for the baseband band limiter • Built-in D/A converters for the analog outputs of the quadrature signal component I and Q • The DC offset and gain can be adjusted with respect to the differential I and Q analog outputs • Completely digitized p/4 shift QPSK demodulator system (ADPCM CODEC Unit) • ADPCM system: built-in ITU-T Recommendations G.726 (32kbps, 24 kbps, 16 kbps) • Transmit/receive full-duplex capability • PCM interface code format: selectable between m-law and A-law • Serial ADPCM and PCM transmission rate: 64 kbps to 2,048 kbps • Transmit/receive mute function; transmit/receive programmable gain setting • Side tone generator (8-step level adjustment) • Built-in DTMF tone, ringing tone, and various ringing tone generators • Built-in VOX function (Common Unit) • Operate with a single 3 V power supply (VDD: 2.7 V to 3.6 V) • Low power consumption When entire system is operating: 20 mA Typ. When powered down: 0.02 mA Typ. • Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name: MSM7586-01TS-K) (Product name: MSM7586-03TS-K) 1/42 ¡ Semiconductor MSM7586-01/03 RXSC SL1 PDN0 PDN1 PDN2 Phase detector IFIN AFC RXD Delay detector MCK SL2 AGM DGM VDDM VDAM BLOCK DIAGRAM AFC Decision RXC SL1 IFCK X2 SL2 DEC To each block DPLL RPR X1 EXCKM DENM DINM DOUTM RCW MODEM MCU interface To each block SLS 4 R7, R6 R5, R4 I+ +1 I– –1 Q+ +1 Q– –1 BSTO CRM1-B7 to B4 D/A LPF DC Adjust CRM1-B3 to B0 TXD S/P MAPPING Root Nyquist LPF ATT TXW D/A LPF DC Adjust ATT To D/A SGM CRM0-B6 <MODEM Unit> VREF SGCR TXCI PLL 3.84M 1/10 384k TXCO <CODEC Unit> Receiver R SGCT Transmitter SW1 T IO1 CRC5-B7 IO2 CRC5-B6 AIN1– AIN1+ VDAC SW2 VOICE DETECT – + VOXO ADPCM CODER GSX1 AIN2– T CRC4-B6 A/D Convertor RC Filter – + CRC2-B6 to B4 BPF ATT GSX2 AOUT+ AOUT– COMPA NDER DTMF /Tone Generator –1 ATT – + CRC4-B5 CRC3-B3 to B0 CRC2-B2 to B0 D/A Convertor RC Filter LPF + + ADPCM DECODER EXPAN DER ATT AIN3 R AIN4 CRC5-B4 CRC5-B5 SW3 – + SW4 SW5 S / P PCMSI P / S PCMSO To each block S / P PCMRI P / S PCMRO S / P IR RSYNC CODEC MCU interface EXCKC DENC DINC DOUTC RESET TOUT3 TOUT2 TOUT1 VOXI IO7 IO6 IO4 IO5 T IO3 GSX4 Power detect To each block Noise generator – + VDDC VDAC DGC AGC PDN3 GSX3 XSYNC IS BCLK Sign bit CRC3-B7 to B5 R PWI VFRO SAO P / S 2/42 ¡ Semiconductor MSM7586-01/03 RXSC SLS IFIN NC X1 NC NC X2 IFCK MCK PDN0 PDN1 PDN2 NC RCW AFC RPR RXC RXD NC DENM EXCKM DOUTM DINM 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100 VDDM PIN CONFIGURATION (TOP VIEW) 18 58 NC GSX2 19 57 PCMSO IO1 20 56 PCMSI IO2 21 55 IS VFRO 22 54 NC PWI 23 53 IR AOUT– 24 52 PCMRO AOUT+ 25 51 PCMRI 50 RSYNC AIN2 VOXO 59 49 17 VOXI XSYNC IO7 48 60 NC 16 47 BCLK IO6 DENC 61 46 15 EXCKC NC IO5 45 62 DOUTC 14 44 R4 GSX1 DINC 63 43 13 NC R5 AIN1– RESET 64 42 12 41 R6 AIN1+ PDN3 65 40 11 TOUT3 R7 SGCT 39 66 TOUT2 10 38 DGC SGCR TOUT1 67 37 9 NC DGM AGC 36 68 IO4 8 35 BSTO AGM IO3 69 34 7 NC NC SGM 33 70 GSX4 6 32 TXCI NC AIN4 71 31 5 NC TXCO I+ 30 72 VDDC 4 29 TXD I– VDAC 73 28 3 GSX3 TXW Q+ 27 NC 74 26 75 2 SAO 1 Q– AIN3 VDAM NC : No connect pin 100-Pin Plastic TQFP 3/42 ¡ Semiconductor MSM7586-01/03 PIN AND FUNCTIONAL DESCRIPTIONS (Modem Unit) TXD Transmit data input for 384 kbps. TXCI Transmit clock input. When the control register CRM0 - B6 is "0", a 384 kHz clock pulse synchronous with TXD should be input to this pin. This clock pulse should be continuous because this device use APLL to generate an internal clock pulse. When CRM0 - B6 is "1", a 3.84 MHz clock pulse should be input to this pin. When the 3.84 MHz clock pulse is applied to TXCL, TXCO outputs a 384 kHz clock pulse, which is generated by dividing the TXCL input by 10. The transmit data, synchronous to the 384 kHz clock pulse, should be input to the TXD. In this case the devices do not use APLL, and the 3.84 MHz clock pulse need not be continuous. (Refer to Fig. 1.) TXCO Transmit clock output. When CRM0 - B6 is "0", TXCO outputs the 384 kHz clock pulse (APLL output) for monitoring purposes. When CRM0 - B6 is "1", this pin outputs a 384 kHz clock pulse generated by dividing the TXCI input by 10. (Refer to Fig. 1.) TXW Transmit data window signal input. The transmit timing signal for the burst data is input to this pin. If TXW is "1", the modulation data is output. (Refer to Fig. 1) 4/42 ¡ Semiconductor (1) CRM0 – B6 = "0" TXD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 TXCI (384 kHz) TXW TXCO (384 kHz) I, Q Delay of 6.25 symbols (2) CRM0 – B6 = "1" TXD , , MSM7586-01/03 Ramp rise-up 2 symbols D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 TXCI (3.84 MHz) TXW TXCO (3.84 kHz) I, Q Delay of 6.25 symbols Dn-1 Dn Ramp rise-up 2 symbols Delay of 6.25 symbols Ramp Fall-down 2 symbols Delay of 6.25 symbols Ramp Fall-down 2 symbols Dn-1 Dn Figure 1 Transmit Timing Diagram 5/42 ¡ Semiconductor MSM7586-01/03 BSTO BSTO is the modulator side burst window output. The burst position of the I and Q baseband modulator output is output. I+, I– Quadrature modulation signal I Component differential analog output. Their output levels are 500 mVpp (when TXD = "0": 360 mVpp typ.) with 1.6 Vdc as the center value. The output pin load conditions are: R ≥ 10 kW, C £ 20 pF. The gain of these pins can be adjusted using the control register CRM1 - B7 to B4, and the offset voltage at the I– pin can be adjusted using CRM3 - B7 to B3. Q+, Q– Quadrature modulation signal Q component differential analog outputs. Their output levels are 500 mVpp (when TXD = "0": 360 mVpp typ.) with 1.6 Vdc as the center value. The output pin load conditions are: R ≥ 10 kW, C £ 20 pF. The gain of these pins can be adjusted using the control register CRM1 - B3 to B0, and the offset voltage at the Q– pin can be adjusted by using CRM4 - B7 to B3. SGM Internal reference voltage output. The output voltage value is approximately 2.0 V. Insert a bypass capacitor between this pin and the AGM pin. During power down, this output is at 0 V. The external SG voltage if necessary should be used via a buffer. 6/42 ¡ Semiconductor MSM7586-01/03 PDN0, PDN1, PDN2 Various power down control. PDN0 controls the standby mode/communication mode; PDN1 controls the modulator unit; and PDN2 controls the demodulator unit. Refer to Table 1 for details. The control register reset input width should be 200ns or more. Table 1: Description of Modem Power Down Control PDN0 PDN2 PDN1 Standby Mode Operation State Mode Name 0 0/1 1 Entire system is powered down. The control register is reset. Mode A 0 0 0 Entire system is powered down. The control register is not reset. Mode B 0 1 0 Modulator unit is powered off. (VREF and PLL also powered off.) Mode C 1 0 0 Modulator unit is powered off. (VREF and PLL are powered on.) Demodulator unit is powered on. Communication Mode Mode D I and Q outputs are in a high impedance state. Only the demodulator clock regenerator unit is powered on. 1 0 1 Modulator unit is powered on. Mode E Only the demodulator clock regenerator unit is powered on. 1 1 0 Modulator unit is powered off. (VREF and PLL are powered off.) Mode F I and Q outputs are in a high impedance state. Demodulator unit is powered on. 1 1 1 Modulator unit is powered on. Mode G Demodulator unit is powered on. 7/42 ¡ Semiconductor MSM7586-01/03 VDDM, VDAM +3 V power supply for the modem unit. Supplied to the digital circuits through the VDDM pin and to the analog circuits through the VDAM pin. VDDM and VDAM, and VDDC and VDAC should be connected as close as possible on the PC board. DGM, AGM Ground pins for the modem unit. DGM is the ground pin of the digital system, and AGM is the ground pin of the analog system. Since DGM and AGM are isolated inside the IC, connect them as close as possible on the circuit board. MCK Master clock input. The clock frequency is 19.2 MHz. IFIN Modulated signal input for the demodulator block. Select the IF frequency can be selected from 1.2 MHz, 10.7 MHz, 10.75 MHz, and 10.8 MHz, based on CRM0 - B4 and B3. IFCK Clock frequency 19.0222 MHz input for demodulator block IF frequencies of 10.7 MHz. If the IF frequency is 1.2 MHz or 10.8 MHz, set this pin to "0" or "1". (Refer to Fig. 2.) X1, X2 Crystal oscillator connection pins. When supplying a 19.0222 MHz clock to IFCK, use these pins. (Refer to Fig. 2.) When IFIN = 10.7 MHz When IFIN = 1.2 MHz or 10.8 MHz MSM7586 MSM7586 X1 X2 IFCK X1 X2 IFCK 19.0222 MHz Figure 2 How to Use IFCK, X1, and X2 8/42 ¡ Semiconductor MSM7586-01/03 RXD, RXC, RXSC Receive data and receive clock outputs. When the modem unit is powered on, RXD, RXC and RXSC are selected based on SLS as shown in Figure 3. These outputs are used by the clock regenerator circuit. RXD RXC RXSC SLS 1 Symbol The regenerated data and clock are selected asynchronously by the SLS signal. Figure 3 Timing Diagram of RXD, RXC, and RXSC SLS Receive side operation slot selection signal. This device has two clock regenerator circuits and two AFC data memory registers. If SLS is "0", slot 1 is selected, if SLS is "1", slot 2 is selected. RPR High-speed phase clock control signal input for the clock recovery circuit. If this pin is at "0", the circuit is always in the low-speed phase clock mode. If this pin is at "1", the clock recovery circuit enters the high-speed phase clock mode. When the phase difference is less than a defined value, the circuit shifts to the low-speed phase clock mode automatically. 9/42 ¡ Semiconductor MSM7586-01/03 AFC AFC operation range specification signal input. As shown in Fig. 4, the AFC information is reset when both AFC and RPR are set to "1". AFC operation starts after a fixed number of clock cycles and the AFC information is reset. If RPR is set to "1", an average number of times that AFC turns on is low. If RPR is "0", AFC is high. If AFC is "0", frequency error is not calculated, but the frequency is corrected using an error that is held. RCW Clock recovery circuit operation ON/OFF control signal input. If RCW this pin is "0", DPLL does not make any phase corrections. (CASE1) AFC RPR AFC information is reset. (CASE2) Average number of times AFC is high. Average number of times AFC is low. AFC information is maintained. AFC "0" RPR The clock recovery circuit starts with the previous AFC information. Average number of times AFC is high. AFC information is maintained. Figure 4 AFC Control Timing Diagram DENM , EXCKM, DINM, DOUTM Serial control ports for the microprocessor interface. The device contains a 6-byte control register (CRM0 - 5). An external CPU uses these pins to read data from and write data to the control register. DENM is the "Enable" signal input pin. EXCKM is a data shift clock pulse input pin. DINM is an address and data input pin. DOUTM is a data output pin. Figure 5 shows input/output timing diagram. 10/42 , , ¡ Semiconductor MSM7586-01/03 DENM EXCKM W DINM A2 A1 A0 DOUTM B7 B6 B5 B4 B3 B2 B1 B0 B2 B1 B0 High Impedance (a) Write Data Timing Diagram DENM EXCKM DINM R DOUTM A2 A1 A0 B7 High Impedance B6 B5 B4 B3 (b) Read Data Timing Diagram Figure 5 Modem Unit MCU Interface I/O Timing The register map is shown below. Table 2: Modem Unit Control Register (CRM0 to 5) Map Register Data Description Address Name A2 A1 A0 B7 CRM0 0 0 0 — CRM1 0 0 1 CRM2 0 1 0 CRM3 0 1 1 CRM4 1 0 0 CRM5 1 0 1 B6 B5 TXC MOD SEL OFF Ich Ich GAIN3 R7 R/W B4 B3 B2 B1 B0 IFSEL1 IFSEL0 — TEST1 TEST0 Ich Ich Qch Qch Qch Qch GAIN2 GAIN1 GAIN0 GAIN3 GAIN2 GAIN1 GAIN0 R6 R5 R4 — — — — R/W — — — R/W — — ICT1 ICT0 Ich Ich Ich Ich Ich Offset4 Offset3 Offset2 Offset1 Offset0 Qch Qch Qch Qch Qch Offset4 Offset3 Offset2 Offset1 Offset0 — ICT5 ICT4 ICT3 ICT2 LOCAL LOCAL INV1 INV0 R/W R/W R/W R/W R/W: Read/Write enable R: Read-only register R7, R6, R5, R4 These are the control register data output pins. These output the data CRM2 - B7, B6, B5, and B4, respectively. 11/42 ¡ Semiconductor MSM7586-01/03 (CODEC Unit) AIN1+, AIN1-, AIN2, GSX1, GSX2 The transmit analog input and the output for transmit gain adjustment. The pin AIN1–(AIN2) connects to the inverting input of the internal transmit amplifier, and the pin AIN1+ connects to the non-inverting input of the internal transmit amplifier. The pin GSX1 (GSX2) connects to output of the internal transmit amplifier. See Fig. 6 for gain adjustment. VFRO, AOUT+, AOUT-, PWI Used for the receive analog output and the output for receive gain adjustment. VFRO is an output of the receive filter. AOUT+ and AOUT– are differential analog signal outputs which can directly drive ZL = 350 W+120 nF or the 1.2 kW load. See Fig. 6 for gain adjustment. However, these outputs are in high impedance state during power down. SAO, AIN3, AIN4, GSX3, GSX4 Input pins for the internal operational amp. Refer to Fig.␣ 6 for connection information. However, these output pins are in the high impedance state during power down. 12/42 ¡ Semiconductor MSM7586-01/03 AIN1– Vi C1 R1 Differential analog input signal C1 R2 – Reference voltage generator + AIN1+ R1 R2 GSX1 SGCT + – AIN2 C2 R3 – to ENCODER + R4 GSX2 AOUT+ Z L = 120 nF + 350 W –1 Analog output signal Vo Transmit gain : (V GSX2 /Vi) = (R2/R1) ¥ (R4/R3) Receive gain : (V O /V VFRO ) = 2 ¥ (R6/R5) R6 – AOUT– R5 VFRO SAO R7 Sounder output signal + R8 from DECODER +1 +1 AIN3 GSX3 – + Sounder output gain : (V GSX3 ) = V SAO ¥ (R8/R7) Figure 6 CODEC Unit Analog Interface 13/42 ¡ Semiconductor MSM7586-01/03 IO1 to IO7 I/O pins of the internal analog switch. Refer to the control register description table (CRC5) and the block diagram for connection information and control methods. TOUT1 to TOUT3 Sign bit output pins of the tone generator. Output control of each pin is performed by the control register. Refer to the control register description table (CRC5) and the block diagram for connection information and control methods. SGCT, SGCR Output pins of the CODEC unit analog signal ground voltage. SGCT outputs the analog signal ground voltage of the transmit system, and SGCR outputs the same for the receive system. The output voltage value is approximately 1.4 V. Connect 10 mF and 0.1 mF bypass capacitors (ceramic type) between these pins and the AGC pin. During power down, the output changes to 0 V. The external SG voltage if necessary should be used via a buffer. VDDC, VDAC CODEC unit +3 V power supply. VDDC is supplied to the digital system power supply, and VDAC is supplied to the analog system power supply. VDDC and VDAC, and VDDM and VDAM must be connected as possible on the PC board. DGC, AGC CODEC unit ground. DGC is the digital system ground pin, and AGC is the analog system ground pin. Since DGC and AGC are unconnected in the device, place them as close together as possible on the circuit board. PDN3 CODEC unit power-down control input. The CODEC unit changes to the power - down state when set to a digital "0." Since the powerdown control is handled by an OR with control register CRC0 - B5, set CRC0 - B5 to digital "0" when using this pin. RESET Reset control input pin of the CODEC unit control register. When set to digital "0," each bit of the control register is reset. During normal operation, set this pin to digital "1." A more than 200ns reset signal should be input. 14/42 ¡ Semiconductor MSM7586-01/03 PCMSO Transmit PCM data output. This PCM output signal is output from MSB synchronous with the rising edge of BCLK and XSYNC. PCMSI Transmit PCM data input. This signal is converted to the ADPCM data. The PCM signal is shifted on the falling edge of BCLK. Normally, this pin is connected to PCMSO. PCMRO Receive PCM data output. The PCM signal is the output signal after ADPCM decoder processing. This signal is serially output from the MSB synchronous with the rising edge of BCLK and RSYNC. PCMRI Receive PCM data input. The PCM input signal is shifted on the falling edge of BCLK and input from MSB. Normally, this pin is connected to PCMRO. IS Transmit ADPCM signal output. This signal is the output signal after ADPCM encoding, and is serially output from MSB synchronous with the rising edge of BCLK and XSYNC. This pin is an open drain output which remains in a high impedence state during power-down, and requires a pull-up resistor. IR Receive ADPCM signal input. Input data is shifted serially from MSB on the falling edge of BCLK synchronous with RSYNC. BCLK Shift clock input for the PCM data (PCMSO, PCMSI, PCMRO, PCMRI) and the ADPCM data(IS, IR) . The frequency ranges from 64 kHz to 2048 kHz. XSYNC Transmit PCM and ADPCM data 8 kHz synchronous signal input. This signal should be synchronous with BCLK. XSYNC is used for indicating MSB of the transmit serial PCM and ADPCM data stream. RSYNC Receive PCM and ADPCM data 8 kHz synchronous signal input. This signal should be synchronous with BCLK signal. RSYNC is used for indicating MSB of the receive serial PCM and ADPCM data stream. 15/42 ¡ Semiconductor MSM7586-01/03 VOXO Transmit VOX function signal output. VOX function is used to recognize the presence or absence of the transmit voice signal by detecting the signal energy. "H" and "L" levels on this pin correspond to the presence and the absence, respectively. This result also appears at the register data CRC7 - B7. The signal energy detect threshold is set by the control register data CRC6 - B6, B5. VOXI Signal input for receive VOX function. The "H" level on VOXI indicates the presence of voice signal, the decoder block processes normal receive signal, and the voice signal appears at analog output pins . The "L" level indicates the absence of voice signal, the background noise generated in this device is transferred to the analog output pins. The background noise amplitude is set by the control register CRC6. Because this signal is ORed with the register data CRC6 - B3, the control register data CRC6 - B3 should be set to digital "0". Input voice signal GSX2 pin VOXO pin Voice Silience Voice detection time Tvxon Voice Silence detection time (Hangover time) Tvxoff (a) Transmission Side VOX Function Timing Diagram VOXI pin Voice Silience Regenerated voice signal generation time Internal background noise generation time Voice Regenerated voice VFRO pin (b) Receive Side VOX Function Timing Diagram Note: The VOXO and VOXI pin function are enabled when CRC6 - B7 is set to "1". Figure 7 VOX Function 16/42 ¡ Semiconductor MSM7586-01/03 , , DENC, EXCKC, DINC, DOUTC Serial control ports for MCU interface. Reading and writing data are performed by an external MCU through these pins. The 8-byte control registers (CRC0 - 7) are provided for the CODEC unit in this device. DENC is the "Enable" control signal input, EXCKC is the data shift clock input, DINC is the address and data input, and DOUTC is the data output. Figure 8 shows input/output timing diagram. DENC EXCKC W DINC A2 A1 A0 DOUTC B7 B6 B5 B4 B3 B2 B1 B0 B2 B1 B0 High Impedance (a) Write Data Timing Diagram DENC EXCKC DINC R DOUTC A2 A1 A0 B7 High Impedance B6 B5 B4 B3 (b) Read Data Timing Diagram Figure 8 CODEC Unit MCU Interface I/O Timing The register map is shown below. Table 3: CODEC Unit Control Register (CRC0 to 7) Map Register Data Description Address Name A2 A1 A0 CRC0 0 0 0 CRC1 0 0 1 CRC2 0 1 0 CRC3 0 1 1 CRC4 1 0 0 CRC5 1 0 1 CRC6 1 1 0 CRC7 1 1 1 B7 A/m SEL MODE1 B6 — MODE0 B5 PDN ALL B4 B3 B2 B1 — — — — TX RX TX RX RESET RESET MUTE MUTE — PDN SAO/AOUT RX TX TX TX TX RX RX RX RX GAIN2 GAIN1 GAIN0 ON/OFF GAIN2 GAIN1 GAIN0 TONE TONE TONE TONE TONE GAIN3 GAIN2 GAIN1 GAIN0 TONE4 TONE3 TONE2 TONE1 TONE0 R/W TOUT3 TOUT2 TOUT1 CONT CONT CONT GAIN1 GAIN0 TONE SAO/ SEND VFRO SW2 SW3 SW4/5 CONT CONT CONT CONT VOX ON ON OFF VOX ON/OFF LVL1 LVL0 TIME IN LEVEL SEL LVL1 LVL0 — — — — — OUT TX NOISE TX NOISE LVL1 LVL0 R/W ON/OFF GAIN2 DTMF/ OTHERS SEL SW1 VOX R/W R/W PAD ON/OFF Side Tone Side Tone Side Tone R/W B0 — R/W R/W RX NOISE RX NOISE RX NOISE R/W R R/W: Read/Write enable R: Read-only register 17/42 ¡ Semiconductor MSM7586-01/03 ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit — –0.3 to +5 V — –0.3 to VDD + 0.3 V VDIN — –0.3 to VDD + 0.3 V TSTG — –55 to +150 °C Symbol Condition Power Supply Voltage VDD Analog Input Voltage VAIN Digital Input Voltage Storage Temperature RECOMMENDED OPERATING CONDITIONS (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Min. Typ. Max. Unit 2.7 — 3.6 V –25 +25 +70 °C Input pins fully digital 0.45 ¥ VDD — VDD V VIL Input pins fully digital 0 — 0.16 ¥ VDD V Digital Input Rise Time tIr Input pins fully digital — — 50 ns Digital Input Fall Time tIf Input pins fully digital — — 50 ns RDL IS (Pull-up resistance) 500 — — W CDL Input pins fully digital — — 100 pF 10 + 0.1 — — mF –0.01% 19.2 +0.01% MHz Parameter Symbol Power Supply Voltage VDD Operating Temperature Ta Input High Voltage VIH Input Low Voltage Digital Output Load CSG Master Clock Frequency FMCK Master Clock Duty Ratio CODEC Unit Modem Unit Bypass Capacitor for SG Conditon Voltage must be fixed — Between SGM and AGM, and between SGCT/R and AGC MCK DMCK MCK 40 50 60 % Modulator Side Input FTXC1 TXCI (When CRM0 - B6 = "0") — 384 — kHz Frequency FTXC2 TXCI (When CRM0 - B6 = "1") — 3.84 — MHz Demodulator Side FIFCK1 IFCK (When IFIN = 10.7 MHz) — 19.0222 — MHz Input Frequency FIFCK2 IFCK (When IFIN = 10.75 MHz) — 19.1111 — MHz Clock Duty Ratio DCKM IFCK, TXCI, EXCKM 40 50 60 % IFIN 45 50 55 % Transmit Sync Pulse tXSM, tSXM TXCI´TXW 200 — — ns Setting Time tSDM, tDHM TXCI´TXD 200 — — ns 64 — 2048 kHz — 8.0 — kHz IF Input Duty Ratio DCIF BCLK Bit Clock Frequency FBCK Synchronous Signal Frequency FSYNC XSYNC, RSYNC Clock Duty Ratio DCKC Fig.9 BCLK, EXCKC Transmit Sync Pulse Setting Time tXSC, tSXC BCLK´XSYNC Receive Sync Pulse Setting Time tRSC, tSRC BCLK´RSYNC tWSC XSYNC, RSYNC Synchronous Signal Width Fig.12 40 50 60 % 100 — — ns 100 — — ns 1 BCLK — 100 ms PCM, ADPCM Set-up Time tDSC — 100 — — ns PCM, ADPCM Hold Time tDHC — 100 — — ns 18/42 ¡ Semiconductor MSM7586-01/03 ELECTRICAL CHARACTERISTICS DC Characteristics (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Power Supply Current (Modem Unit) * When CODEC Unit is in a Power Down State Power Supply Current (CODEC Unit) * When Modem Unit is in a Power Down State Input Leakage Current * Symbol Condition Min. Typ. IDD1 Mode A, Mode B (When VDD = 3.0 V) — 0.02 0.1 mA IDD2 Mode C (When VDD = 3.0 V) — 5.5 11.0 mA IDD3 Mode D (When VDD = 3.0 V) — 5.5 11.0 mA IDD4 Mode E (When VDD = 3.0 V) — 11.5 23.0 mA IDD5 Mode F (When VDD = 3.0 V) — 9.5 19.0 mA IDD6 Mode G (When VDD = 3.0 V) — 14.0 28.0 mA IDD7 When operating * (When no signal, and VDD = 3.0 V) — 8.0 16.0 mA IDD8 — 12.0 19.0 mA IDD9 When powered down (When VDD = 3.0 V) — 0.02 0.1 mA VI = VDD — — 2.0 mA IIH IIL Output High Voltage VOH Output Low Voltage VOL Output Leakage Current IO Input Capacitance CIN VI = 0 V Max. Unit — — 0.5 mA IOH = 0.4 mA 0.5 ¥ VDD — VDD V IOH = 1 mA 0.8 ¥ VDD — VDD V 0 0.2 0.4 V — — 10 mA — 5 — pF IOL = –1.2 mA (IS pin is 500 W pull-up) IS pin — IDD7 applies when CRC0 - B0 = "0" and CRC4 - B5 = "0"; IDD8 applies when operating at other times. 19/42 ¡ Semiconductor MSM7586-01/03 Analog Interface Characteristics (Modem Unit) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Symbol Condition Min. Typ. Max. Unit Output Resistance Load RLIQ I+, I–, Q+, Q– 10 — — kW Output Capacitance Load CLIQ I+, I–, Q+, Q– — — 20 pF Output DC Voltage Level VDCM I+, I–, Q+, Q– (TXW = 0) 1.55 1.6 1.65 V 340 360 380 mVPP –20 — +20 mV Output AC Voltage Level VACM Offset Voltage Difference VOFF Modulator D/A I+, I–, Q+, Q– (For TXD = 0 continuous input) Difference among I+, I–, Q+ and Q– FSDA — — 1.92 — MHz FCDA — — 380 — kHz Output DC Voltage Adjustment Level Range DCVL — — ±45 — mV Output AC Voltage Adjustment Level Range ACVL — — ±4 — % P600 600 kHz detuning (continuous) 60 — — dB P900 900 kHz detuning (continuous) 65 — — dB EVM — 1.0 3.0 Conversion Sampling Frequency Modulator D/A Conversion Offset Frequency Out-of-band Spectrum Modulation Accuracy — % rms Demodulator Side IF Input Level IFV IFIN input level 0.4 — VDD VPP IFIN Input Impedance RIF DC impedance — 20 — kW SGM Output Voltage VSGM — — 2.0 — V SGM Output Impedance RSGM — — 1.5 — kW 1.5 — VDD VPP 0.7 — VDD VPP IX11 Master Clock External Input Level IX12 X1 input level (When CRM5 – B1 = "0") X1 input level (When CRM5 – B1 = "1") X1 Input Impedande RX1 — — 2.0 — MW X1 Input Capacitance CX1 — — 10 — pF 20/42 ¡ Semiconductor MSM7586-01/03 Digital Interface Characteristics (Modem Unit) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Transmit Symbol Condition Reference Digital I/O Setting Time tXDM1,2 C load = 50 pF tXDM3,4 Fig. 9 Receive Digital I/O Setting Time tRDM1,2 C load = 50 pF Fig. 10 Serial Port Digital I/O Setting Time EXCK Clock Frequency Min. Typ. Max. Unit 0 — 200 ns 0 — 400 ns 0 — 200 ns tM1 50 — — ns tM2 50 — — ns tM3 50 — — ns tM4 50 — — ns tM5 100 — — ns 50 — — ns 50 — — ns tM8 0 — 100 ns tM9 50 — — ns tM10 50 — — ns tM11 0 — 50 ns tM12 200 — — ns — — 10 MHz tM6 tM7 C load = 50 pF Feckm EXCKM Fig. 11 — 21/42 ¡ Semiconductor MSM7586-01/03 Analog Interface Characteristics (CODEC Unit) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Input Resistance Symbol RINC Output Resistance Load Output Capacitance Load AIN+, AIN–, AIN2, PWI, AIN3, AIN4 Max. Unit 10 — — MW GSX1, GSX2, VFRO, SAO 20 — — kW AOUT+, AOUT–, GSX4 1.2 — — kW RLC3 GSX3 150 — — W CLC1 GSX1, GSX2, VFRO, SAO — — 100 pF CLC2 AOUT+, AOUT–, GSX4 — — 100 pF CLC3 GSX3 — — 100 pF — — 1.3 VPP — — 1.3 VPP — — 1.3 VPP –100 — +100 mV –20 — +20 mV — 1.4 — V VOC2 GSX1, GSX2, VFRO, SAO(RL = 20 kW) AOUT+, AOUT–, GSX4 (RL = 1.2 kW) GSX3(RL = 150 W) VOFC1 VFRO, SAO VOFC2 SGCT, SGCR Output Voltage Typ. RLC2 VOC3 Offset Voltage Min. RLC1 VOC1 Output Voltage Level (*1) Condition VSGC GSX1, GSX2, AOUT+, AOUT–, GSX3, GSX4 SGCT, SGCR SGCT Output Impedance RSGCT SGCT — 40 80 kW SGCR Output Impedance RSGCR SGCR — 4 8 kW SGCT Rise Time TSGCT — 600 — ms SGCR Rise Time TSGCR — 15 — ms Analog Switch OFF Resistance RSWof SW1 to SW5 50 — — MW Analog Switch ON Resistance RSWon SW1 to SW5 100 — 400 W Note : *1 For the Recommended Circuit (Rise time to 90% of max. level) For the Recommended Circuit (Rise time to 90% of max. level) –7.7 dBm (600 W) = 0 dBm0, +3.14 dBm0 = 1.30 VPP (A-law) –7.7 dBm (600 W) = 0 dBm0, +3.17 dBm0 = 1.30 VPP (m-law) 22/42 ¡ Semiconductor MSM7586-01/03 Digital Interface Characteristics (CODEC Unit) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Symbol Digital Output Delay Time tSDXC, tSDRC tXDC1, tRDC1 PCM, ADPCM Interface tXDC2, tRDC2 tXDC3, tRDC3 Condition Reference 1 LSTTL + 100 pF pull-up : 500 W Fig. 12 Items in parenthesis ( ) mean C load = 10 pF, and the pull-up £ 2 kW Typ. Max. Unit 0 — 200 (100) ns 0 — 200 (100) ns 0 — 200 (100) ns 0 — 200 (100) ns tC1 50 — — ns tC2 50 — — ns tC3 50 — — ns tC4 50 — — ns tC5 100 — — ns 50 — — ns 50 — — ns Serial Port Digital I/O tC6 Timing Characteristics tC7 C load = 50 pF Fig. 13 tC8 0 — 100 ns tC9 50 — — ns tC10 50 — — ns tC11 0 — 50 ns tC12 EXCK Clock Frequency Min. Feckc EXCKC — 200 — — ns — — 10 MHz 23/42 ¡ Semiconductor MSM7586-01/03 AC Characteristics (CODEC Unit) Parameter Symbol (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Condition Frequency (Hz) Level dBm0 Min. Typ. Max. Unit — — dB — +0.20 dB LOSS T1 0 to 60 25 –0.15 LOSS T2 300 to 3 k Transmit Frequency LOSS T3 1020 Response LOSS T4 3300 –0.15 — +0.80 dB LOSS T5 3400 0 — 0.80 dB LOSS T6 3968.75 13 — — dB LOSS R1 0 to 3000 –0.15 — +0.20 dB LOSS R2 1020 LOSS R3 3300 LOSS R4 3400 LOSS R5 3968.75 Receive Frequency Response SD T1 Distortion Ratio (*2) Distortion Ratio (*2) Transmit Gain Tracking Receive Gain Tracking Note: *2 Reference 0 dB –0.15 — +0.80 dB 0 — 0.80 dB 13 — — dB 3 35 — — dB 0 35 — — dB 35 — — dB SD T4 –40 28 — — dB SD T5 –45 23 — — dB SD R1 3 35 — — dB SD T3 1020 0 35 — — dB –30 35 — — dB SD R4 –40 28 — — dB SD R5 –45 23 — — dB GT T1 3 –0.2 — +0.2 dB GT T2 –10 SD R2 Receive Signal to dB –30 SD T2 Transmit Signal to 0 Reference SD R3 1020 dB Reference –40 –0.2 — +0.2 dB GT T4 –50 –0.5 — +0.5 dB GT T3 1020 GT T5 –55 –1.2 — +1.2 dB GT R1 3 –0.2 — +0.2 dB GT R2 –10 –40 –0.2 — +0.2 dB GT R4 –50 –0.5 — +0.5 dB GT R5 –55 –1.2 — +1.2 dB GT R3 1020 dB Reference P-message filter used 24/42 ¡ Semiconductor MSM7586-01/03 AC Characteristics (CODEC Unit) Parameter Idle Channel Symbol NIDLT (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Condition Frequency (Hz) Level dBm0 Other — AIN = SG — Min. Typ. — — Noise NIDLR (*2) Absolute Level (*4) AVT AVR — (*3) 0 1020 Power Supply Noise PSRRT Noise frequency: Rejection Ratio PSRRR Noise level: 0 kHz to 50 kHz 50 mVpp Max. Unit –68 (–75.7) dBm0p –72 (dBmp) — — — GSX2 0.285 0.320 0.359 Vrms VFRO 0.285 0.320 0.359 Vrms 30 — — dB 30 — — dB — (–79.7) Notes: *2 P-message filter used *3 PCMRI input: "11010101" (A-law), "11111111" (m-law) *4 0.320 Vrms = 0 dBm0 = –7.7 dBm (600 W) ADPCM unit characteristics are fully compliant with ITU-T Recommendation G.726. AC Characteristics (DTMF and Other Tones) Parameter Frequency Deviation Tone Reference Output Level (*5) DTMF tones Min. Typ. Max. Unit –7 — +7 Hz DFT2 Other various tones –7 — +7 Hz VTL Transmit side tone DTMF (low group) –18 –16 –14 dBm0 VTH (Gain setting 0dB) DTMF (high group), other Receive side tone DTMF (low group) (Tone generator gain setting –6dB) DTMF (high group), other –16 –14 –12 dBm0 –10 –8 –6 dBm0 –8 –6 –4 dBm0 1 2 3 dB VRL VRH DTMF Tone Level Relative Value RDTMF Note: Condition Symbol DFT1 (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) VTH/VTL, VRH/VRL *5 Not including programmable gain set values AC Characteristics (Gain Settings) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Transmit/Receive Gain Setting Accuracy Condition Symbol DG For all gain set values Min. Typ. Max. Unit –1 0 +1 dB AC Characteristics (VOX Function) (VDD = 2.7 V to 3.6 V, Ta = –25°C to +70°C) Parameter Transmit VOX Detection Time (Voice and Silence Test Time) TVXON SilenceÆvoice VOXO pin: See Fig. 7 TVXOF VoiceÆsilence Transmit VOX Detection Level Accuracy (Voice Detection Level) Note: Condition Symbol DVX Voice/silence differential: 10 dB For detection level set values by CRM6 - B6, B5 Min. — Typ. 10*6 Max. Unit — ms 140/300 160/320 180/340 –2.5 0 +2.5 ms dB *6 When single tone is input at 1000Hz 25/42 , , ¡ Semiconductor MSM7586-01/03 TIMING DIAGRAM (Modem Unit) Transmit Data Input Timing TXCI [TXCO*] (384 kHz) TXW 1 tXSM 2 3 N-2 N-1 N tSXM N+1 tXSM tSXM tDSM tDHM 1 TXD 2 3 N-2 N-1 N TXCO in brackets [ ] is when CRM0 - B6 = 1 Transmit Clock (TXCO) Timing (When CRM0 - B6 = 1) TXCI (3.84 MHz) TXCO (384 kHz) 1 2 3 4 5 6 tXDM1 7 8 9 10 tXDM2 tXDM1 Transmit Burst Position (BSTO) Output Timing (When CRM0 - B6 = 0) 1 TXCI (384 kHz) 2 9 10 N N+1 N+16 N+17 N+18 TXW tXDM3 tXDM4 BSTO Figure 9 Modem Unit Transmit Side (Modulator Side) Digital I/O Timing Receive Side Data I/O Timing SLS RXC tRDM2 tRDM1 RXD Figure 10 Modem Unit Receive Side (Demodulator Side) Digital I/O Timing Serial Port Timing for Microcontroller Interface DENM 1 EXCKM tM1 DINM tM3 2 3 4 tM6 tM4 W/R tM12 tM10 tM5 tM2 A2 5 6 11 12 tM9 tM7 A1 A0 B7 B1 B0 tM11 tM8 DOUTM B7 B1 B0 Figure 11 Modem Unit Serial Control Port Interface 26/42 ¡ Semiconductor MSM7586-01/03 (CODEC Unit) Transmit Side PCM, ADPCM Timing 0 BCLK 1 tSXC tXSC XSYNC 2 3 4 5 6 7 8 10 tWSC tXDC1 tXDC2 tXDC3 LSB MSB PCMSO 9 tSDXC BCLK 0 tXSC XSYNC 1 tSXC 2 tXDC1 tXDC2 IS 3 4 6 7 8 9 10 5 6 7 8 9 10 9 10 tXDC3 LSB MSB tSDXC 5 Receive Side PCM, ADPCM Timing 1 tSRC BCLK tRSC 2 RSYNC 4 tDHC tDSC IR 3 tWSC tXDC3 MSB BCLK 0 tRSC LSB 1 tSRC 2 3 tRDC1 tRDC2 4 5 6 7 8 RSYNC tRDC3 LSB MSB PCMRO tSDXC Figure 12 CODEC Unit PCM, ADPCM Interface Serial Port Timing for Microcontroller Interface DENC 1 EXCKC tC1 DINC tC3 2 3 4 tC6 tC4 W/R tC12 tC10 tC5 tC2 A2 5 6 11 12 tC9 tC7 A1 A0 B7 B1 B0 tC11 tC8 DOUTC B7 B1 B0 Figure 13 CODEC Unit Serial Control Port Interface 27/42 ¡ Semiconductor MSM7586-01/03 Modem Unit Mode State Transition Time Mode A* PDN1 = 1 Note: Values not indicated are less than 1 ms. 1 ms Standby mode (PDN0 = 0) 5 ms Mode B Mode C PDN1 = 0 PDN2 = 1 PDN1 = 0 PDN2 = 0 Communication mode (PDN0 = 1) 40 ms Mode E 5 ms Mode D PDN1 = 1 PDN2 = 0 Mode F PDN1 = 0 PDN2 = 0 5 ms PDN1 = 0 PDN2 = 1 40 ms Mode G PDN1 = 1 PDN2 = 1 * Note that this state clears the register. Figure 14 Modem Unit Power Down State Transition Time 28/42 ¡ Semiconductor MSM7586-01/03 Modem Unit Demodulator Control Timing Diagram (Example) 1st slot Demodulator unit Modulator input data G R1 G PDN2 SLS AFC RXD RXC "0" R1 (1) Control ch/ synchronous burst (SS + PR = 64 bits) 240 bits 625 ms 64 bits RXD G G G G G G G G R R R R SS SS PR PR PR UW CR CR G G G G G G G G CR CR G G G G G G G G AFC* RPR RCW* 56 bits (2) When synchronization is not yet established AFC* RPR RCW* (3) Communication ch (SS + PR = 8 bits) RXD G G 8 bits G G G G G G R R R R SS SS PR PR PR UW AFC RPR "0" RCW Less than 30 bits *AFC and RCW may be controlled at the same timing. G: Guard bit R: Ramp bit SS: Start symbol bit PR: Preamble bit UW: Unique word bit CR: CRC bit Figure 15 Modem Unit Demodulator Timing Diagram Example 29/42 ¡ Semiconductor MSM7586-01/03 FUNCTIONAL DESCRIPTION Control Register Description Table (Modem Unit) (1) CRM0 (Basic Operation Mode Setting) B7 CRM0 — Initial Value (Note) 0 Note: B6 B5 TXC MOD SEL OFF 0 0 B4 B3 B2 B1 B0 IFSEL1 IFSEL0 — TEST1 TEST0 0 0 0 0 0 The initial value is the value set when a reset is applied by the RESET pin. B7, B2: ..... Not used B6: ............ Transmission timing clock selection 0: TXCI input: 384 kHz TXCO output: APLL 384 kHz output Transmission data TXD is input synchronized to the rise of TXCI. APLL is ON. 1: TXCI input: 3.84 MHz TXCO output: 384 kHz (TXCI divided by 10) Transmission data TXD is input synchronized to the rise of TXCO. APLL is OFF. B5: Modulation OFF/ON control 0: Modulation ON 1: Modulation OFF B4, B3: ..... Receive side input IF frequency selection (0,0), (0,1): 1.2 MHz (1,0): 10.8 MHz (1,1): 10.7 MHz/10.75 MHz B1, B0: ..... Device test control bit Since it is used for LSI testing, it is normally set to "0." 30/42 ¡ Semiconductor MSM7586-01/03 (2) CRM1 (I and Q Gain Adjustment) B7 CRM1 B6 B5 B4 B3 B2 B1 B0 Ich Ich Ich Ich Qch Qch Qch Qch GAIN3 GAIN2 GAIN1 GAIN0 GAIN3 GAIN2 GAIN1 GAIN0 0 0 0 0 0 0 0 0 Initial Value B7 to B4: .... I+ and I- output gain setting: 3 mV steps (refer to Table 4) B3 to B0: .... Q+ and Q- output gain setting: 3 mV steps (refer to Table 4) Table 4: I and Q Gain Setting Table CRM1 - B7 B6 B5 B4 CRM1 - B3 B2 B1 B0 0 1 1 1 Amplitude value: 1.042 reference value 0 1 1 0 1.036 0 1 0 1 1.030 0 1 0 0 1.024 0 0 1 1 1.018 0 0 1 0 1.012 0 0 0 1 1.006 0 0 0 0 1.000 (Reference value) 1 1 1 1 0.994 1 1 1 0 0.988 1 1 0 1 0.982 1 1 0 0 0.976 1 0 1 1 0.970 1 0 1 0 0.964 1 0 0 1 0.958 1 0 0 0 0.952 Description (3) CRM2 (Output to R7 to R4 pins) CRM2 Initial Value B7 B6 B5 B4 B3 B2 B1 B0 R7 R6 R5 R4 — — — — 0 0 0 0 0 0 0 0 B7 to B4: .... Output to R7 to R4 pin 31/42 ¡ Semiconductor MSM7586-01/03 (4) CRM3 (I- Output Offset Voltage Adjustment) B7 CRM3 B6 B5 B4 B3 Ich Ich Ich Ich Ich Offset4 Offset3 Offset2 Offset1 Offset0 0 0 0 0 0 Initial Value B2 B1 B0 — — — 0 0 0 B2 B1 B0 — — — 0 0 0 B7 to B3: .... I- output pin offset voltage adjustment (refer to Table 5) B2 to B0: .... Not used (5) CRM4 (Q- Output Offset Voltage Adjustment) B7 CRM4 B6 B5 B4 B3 Qch Qch Qch Qch Qch Offset4 Offset3 Offset2 Offset1 Offset0 0 0 0 0 0 Initial Value B7 to B3: .... Q- output pin offset voltage adjustment (refer to Table 5) B2 to B0: .... Not used Table 5: Ich and Qch Offset Adjustment Values CRM3 - B7 B6 B5 B4 B3 Offset Voltage CRM4 - B7 B6 B5 B4 B3 CRM3 - B7 B6 B5 B4 B3 Offset Voltage CRM4 - B7 B6 B5 B4 B3 0 1 1 1 1 +45 mV 1 1 1 1 1 –3 mV 0 1 1 1 0 +42 mV 1 1 1 1 0 –6 mV 0 1 1 0 1 +39 mV 1 1 1 0 1 –9 mV 0 1 1 0 0 +36 mV 1 1 1 0 0 –12 mV 0 1 0 1 1 +33 mV 1 1 0 1 1 –15 mV 0 1 0 1 0 +30 mV 1 1 0 1 0 –18 mV 0 1 0 0 1 +27 mV 1 1 0 0 1 –21 mV 0 1 0 0 0 +24 mV 1 1 0 0 0 –24 mV 0 0 1 1 1 +21 mV 1 0 1 1 1 –27 mV 0 0 1 1 0 +18 mV 1 0 1 1 0 –30 mV 0 0 1 0 1 +15 mV 1 0 1 0 1 –33 mV 0 0 1 0 0 +12 mV 1 0 1 0 0 –36 mV 0 0 0 1 1 +9 mV 1 0 0 1 1 –39 mV 0 0 0 1 0 +6 mV 1 0 0 1 0 –42 mV 0 0 0 0 1 +3 mV 1 0 0 0 1 –45 mV 0 0 0 0 0 0 mV 1 0 0 0 0 –48 mV 32/42 ¡ Semiconductor MSM7586-01/03 (6) CRM5 (IC Test) CRM5 Initial Value Note: B7 B6 B5 B4 ICT5 ICT4 ICT3 ICT2 0 0 0 0 B3 B2 LOCAL LOCAL INV1 INV0 0 0 B1 B0 ICT1 ICT0 0 0 B7 to B4: .... LSI test control bit Since B7 to B4 of CRM5 are used for LSI testing, they should normally be set to "0". B3, B2: .......Local inverted mode setting bit (Use if the phase of the demodulator side IF input is inverted due to the system configuration.) (0,0): Normal mode(1,1): Local inverted mode B1: .............. Waveform shaping mode switching bit of the oscillator circuit unit clock (When using a master clock external input, increase the X1 pin input sensitivity.) 0: Normal mode 1: Clock waveform shaping mode B0: .............. Oscillator circuit unit power on control bit 0: Normal mode 1: Oscillator circuit unit is always powered on 33/42 ¡ Semiconductor MSM7586-01/03 (CODEC Unit) (1) CRC0 (Basic Operation Mode Settings) B7 A/m CRC0 SEL Initial Value 0 B6 — 0 B5 PDN ALL 0 B4 B3 B2 B1 — — — — 0 0 0 0 B0 PDN SAO/AOUT 0 B7: ........................... PCM interface companding selection 0: m-law 1: A-law B6, B4, B3, B2, B1: . Not used (These pins are used to test the device. They should be set to "0" during normal operation.) B5: ........................... Power down (entire unit) 0: Power ON 1: Power down ORed with the inverse of the external power down signal. When using this data, set PDN3 to "1." B0: ........................... The sounder output amp (SAO, GSX3) and receiver system output amp (VFRO, AOUT+, AOUT-) power down control 0: The output amp of the side not selected by CRC4 - B5 is powered down. 1: The sounder system output amp and receiver system output amp are both powered ON. (2) CRC1 (ADPCM Unit Operation Mode Settings) CRC1 Initial Value B7 B6 B5 B4 B3 B2 B1 B0 MODE1 MODE0 TX RESET RX RESET TX MUTE RX MUTE — RX PAD 0 0 0 0 0 0 0 0 B7, B6: .......ADPCM unit compression algorithm selection (0,0): 32 kbps (0,1): 64 kbps (G.711 through) (1,0): 24 kbps (1,1): 16 kbps B5: .............. Transmit side ADPCM reset (according to the G.726 specifications): 1: Reset The ADPCM reset input width should be 125 ms or more. B4: .............. Receive side ADPCM reset (according to the G.726 specifications): 1: Reset The ADPCM reset input width should be 125 ms or more. B3: .............. Transmit side ADPCM data mute: 1: Mute B2: .............. Receive side ADPCM data mute: 1: Mute B1: .............. Not used B0: .............. Receive side PAD 0: No PAD 1: A PAD with a 12 dB loss is inserted in the receive side voice path 34/42 ¡ Semiconductor MSM7586-01/03 (3) CRC2 (PCM CODEC Unit Operation Mode Settings and Transmit/Receive Gain Adjustment) B7 CRC2 Initial Value B6 B5 B4 B3 B2 B1 B0 TX TX TX TX RX RX RX RX ON/OFF GAIN2 GAIN1 GAIN0 ON/OFF GAIN2 GAIN1 GAIN0 0 0 1 1 0 0 1 1 B7: .............. Transmit side PCM signal ON/OFF 0: ON 1: OFF When OFF, transmits a PCM idle pattern. B6, B5, B4: Transmit side signal gain adjustment (refer to Table 6) B3: .............. Receive side PCM signal ON/OFF 0: ON 1: OFF When OFF transmits a PCM idle pattern. B2, B1, B0: .Receive side signal gain adjustment (refer to Table 6) Table 6: Receive/Transmit Gain Settings • MSM7586-01 B6 B5 B4 Transmit Side Gain B2 B1 B0 Receive Side Gain 0 0 0 –6 dB 0 0 0 –6 dB 0 0 1 –4 dB 0 0 1 –4 dB 0 1 0 –2 dB 0 1 0 –2 dB 0 1 1 0 dB 0 1 1 0 dB 1 0 0 +2 dB 1 0 0 +2 dB 1 0 1 +4 dB 1 0 1 +4 dB 1 1 0 +6 dB 1 1 0 +6 dB 1 1 1 +8 dB 1 1 1 +8 dB • MSM7586-03 B6 B5 B4 Transmit Side Gain B2 B1 B0 Receive Side Gain 0 0 0 –6 dB 0 0 0 –12 dB 0 0 1 –4 dB 0 0 1 –9 dB 0 1 0 –2 dB 0 1 0 –6 dB 0 1 1 0 dB 0 1 1 –3 dB 1 0 0 +2 dB 1 0 0 0 dB 1 0 1 +4 dB 1 0 1 +3 dB 1 1 0 +6 dB 1 1 0 +6 dB 1 1 1 +8 dB 1 1 1 +9 dB The above gain settings table shows the transmit/receive voice signal gain settings and the transmit side gain settings for DTMF tones and other tones. Tone signal transmission is enabled by CRC4 - B6 (discussed later), and the gain setting is set to the levels shown below. DTMF tones (low group): ................................. –16 dBm0 DTMF tones (high group) and other tones: ... –14 dBm0 For example, if the transmit gain set value is set to +8 dB (B6, B5, B4) = (1, 1, 1), then the following tones appear at the PCMSO pin. DTMF tones (low group): ................................. –8 dBm0 DTMF tones (high group) and other tones: ... –6 dBm0 35/42 ¡ Semiconductor MSM7586-01/03 However, the gain of the receive side tone and the gain of the side tones (path from transmit side to receive side) are set by the CRC3 register. (4) CRC3 (Side Tone and Tone Generator Gain Adjustment) B7 B6 B5 Side Tone Side Tone Side Tone CRC3 Initial Value B4 B3 B2 B1 B0 TONE TONE TONE TONE TONE GAIN2 GAIN1 GAIN0 ON/OFF GAIN3 GAIN2 GAIN1 GAIN0 0 0 0 0 0 0 0 0 B7, B6, B5: ........ Side tone gain adjustment (refer to Table 7) B4: ..................... Tone generator ON/OFF 0: OFF 1: ON B3, B2, B1, B0: . Tone generator Receive side gain adjustment (refer to Table 8) Table 7: Side Tone Gain Settings • MSM7586-01 B7 B6 B5 Side Tone Gain 0 0 0 OFF 0 0 1 –21 dB 0 1 0 –19 dB 0 1 1 –17 dB 1 0 0 –15 dB 1 0 1 –13 dB 1 1 0 –11 dB 1 1 1 – 9 dB B7 B6 B5 Side Tone Gain 0 0 0 OFF 0 0 1 –15 dB 0 1 0 –13 dB 0 1 1 –11 dB 1 0 0 – 9 dB 1 0 1 – 7 dB 1 1 0 – 5 dB 1 1 1 – 3 dB • MSM7586-03 36/42 ¡ Semiconductor MSM7586-01/03 Table 8: Receive Side Tone Generator Gain Settings • MSM7586-01 B3 B2 B1 B0 Tone Generator Gain B3 B2 B1 B0 Tone Generator Gain 0 0 0 0 –36 dB 1 0 0 0 –20 dB 0 0 0 1 –34 dB 1 0 0 1 –18 dB 0 0 1 0 –32 dB 1 0 1 0 –16 dB 0 0 1 1 –30 dB 1 0 1 1 –14 dB 0 1 0 0 –28 dB 1 1 0 0 –12 dB 0 1 0 1 –26 dB 1 1 0 1 –10 dB 0 1 1 0 –24 dB 1 1 1 0 – 8 dB 1 1 1 1 –22 dB 1 1 1 1 – 6 dB Tone Generator Gain B3 B2 B1 B0 Tone Generator Gain • MSM7586-03 B3 B2 B1 B0 0 0 0 0 OFF 1 0 0 0 –20 dB 0 0 0 1 –34 dB 1 0 0 1 –18 dB 0 0 1 0 –32 dB 1 0 1 0 –16 dB 0 0 1 1 –30 dB 1 0 1 1 –14 dB 0 1 0 0 –28 dB 1 1 0 0 –12 dB 1 1 0 1 –10 dB 0 1 0 1 –26 dB 0 1 1 0 –24 dB 1 1 1 0 – 8 dB 1 –22 dB 1 1 1 1 – 6 dB 1 1 1 The receive side tone generator gain settings shown in Table 8 are set with the following levels as a reference. DTMF tones (low group): ................................. –2 dBm0 DTMF tones (high group) and other tones: ... 0 dBm0 For example, if the tone generator gain set value is set to -6 dB (B3, B2, B1, B0)=(1, 1, 1, 1), then tones at the following levels appear at the SAO or VFRO pin. DTMF tones (low group): ................................. –8 dBm0 DTMF tones (high group) and other tones: ... –6 dBm0 37/42 ¡ Semiconductor MSM7586-01/03 (5) CRC4 (Tone Generator Operation Mode and Frequency Settings) B7 CRC4 B6 B5 DTMF/OT TONE SAO/ HERS SEL SEND VFRO 0 0 0 Initial Value B4 B3 B2 B1 B0 TONE4 TONE3 TONE2 TONE1 TONE0 0 0 0 0 0 B7: ........................... Selection of DTMF signal and other tones (S tone, F tone, R tone, etc.) 0: Other tones 1: DTMF tones B6: ........................... Transmission side tone transmit 0: Voice signal transmit 1: Tone transmit B5: ........................... Receive side tone output pin selection 0: VFRO output 1: SAO output B4, B3, B2, B1, B0: . Tone frequency setting (refer to Table 9) Table 9: Tone Generator Frequency Settings (a) When B7 = 1 (DTMF Tones) B4 B3 B2 B1 B0 Description B4 B3 B2 B1 B0 Description * 0 0 0 0 697 Hz + 1209 Hz * 1 0 0 0 852 Hz + 1209 Hz * 0 0 0 1 697 Hz + 1336 Hz * 1 0 0 1 852 Hz + 1336 Hz * 0 0 1 0 697 Hz + 1477 Hz * 1 0 1 0 852 Hz + 1477 Hz * 0 0 1 1 697 Hz + 1633 Hz * 1 0 1 1 852 Hz + 1633 Hz * 0 1 0 0 770 Hz + 1209 Hz * 1 1 0 0 941 Hz + 1209 Hz * 0 1 0 1 770 Hz + 1336 Hz * 1 1 0 1 941 Hz + 1336 Hz * 0 1 1 0 770 Hz + 1477 Hz * 1 1 1 0 941 Hz + 1477 Hz * 0 1 1 1 770 Hz + 1633 Hz * 1 1 1 1 941 Hz + 1633 Hz Description (b) When B7 = 0 (Outside of DTMF Tones) B4 B3 B2 B1 B0 Description B4 B3 B2 B1 B0 0 0 0 0 0 2730 Hz/2500 Hz 8 Hz Wamble 1 0 0 0 0 — 0 0 0 0 1 2000 Hz/2667 Hz 8 Hz Wamble 1 0 0 0 1 1300 Hz Single tone 0 0 0 1 0 1000 Hz/1333 Hz 8 Hz Wamble 1 0 0 1 0 1333 Hz Single tone 0 0 0 1 1 — 1 0 0 1 1 — 0 0 1 0 0 — 1 0 1 0 0 — 0 0 1 0 1 — 1 0 1 0 1 2000 Hz Single tone 0 0 1 1 0 — 1 0 1 1 0 — 0 0 1 1 1 — 1 0 1 1 1 — 0 1 0 0 0 — 1 1 0 0 0 — 0 1 0 0 1 400 Hz Single tone 1 1 0 0 1 — 0 1 0 1 0 — 1 1 0 1 0 — 0 1 0 1 1 — 1 1 0 1 1 — 0 1 1 0 0 — 1 1 1 0 0 2667 Hz Single tone 0 1 1 0 1 — 1 1 1 0 1 — 0 1 1 1 0 — 1 1 1 1 0 2730 Hz Single tone 0 1 1 1 1 1000 Hz Single tone 1 1 1 1 1 — 38/42 ¡ Semiconductor MSM7586-01/03 (6) CRC5 (Control of Switches, etc.) B7 CRC5 Initial Value B6 B5 B4 SW1 SW2 SW3 SW4/5 CONT CONT CONT CONT 0 0 0 0 B7, B6: .......SW1, SW2 control B5: .............. SW3 control B4: .............. SW4/5 control B2, B1, B0: .TOUT3 to 1 control B3 — 0 B2 B1 B0 TOUT3 TOUT2 TOUT1 CONT CONT CONT 0 0 0 0: Open 1: Closed 0: Open 1: Closed 0: SW4 open, SW5 closed 1: SW4 closed, SW5 open 0: TOUT3 to 1 disable 1: TOUT3 to 1 enable (7) CRC6 (VOX Function Control) CRC6 Initial Value B7 B6 B5 B4 B3 B2 B1 B0 VOX ON ON OFF VOX RX NOISE RX NOISE RX NOISE ON/OFF LVL1 LVL0 TIME IN LEVEL SEL LVL1 LVL0 0 0 0 0 0 0 0 0 B7: .............. VOX function ON/OFF 0: OFF 1: ON B6, B5: .......Transmit side voice/silence detector level settings (For the signal of 1kHz) MSM7586-01 (0,0): –30 dBm0 (0,1): –35 dBm0 (1,0): –40 dBm0 (1,1): –45 dBm0 MSM7586-03 (0,0): –20 dBm0 (0,1): –26 dBm0 (1,0): –32 dBm0 (1,1): –38 dBm0 B4: .............. Hangover time (refer to Fig. 7) settings 0: 160 ms 1: 320 ms B3: .............. Receive side VOX input signal 0: Internal background noise transmit 1: Voice receive signal transmit When using this data, set the VOXI pin to "0." B2: .............. Receive side background noise level setting 0: Internal automatic setting 1: External (by B1, B0) setting Internal automatic setting Æ Sets to the voice signal level when B3 (VOXI) changes from "1" to "0." B1, B0: .......External setting background noise level (0,0): No noise (0,1): –55 dBm0 (1,0): –45 dBm0 (1,1): –35 dBm0 39/42 ¡ Semiconductor MSM7586-01/03 (8) CRC7 (Detect Register: Read-only) B7 VOX CRC7 Initial Value Note: B6 B5 Silent Level Silent Level OUT 1 0 0 0 0 B4 B3 B2 B1 B0 — — — — — * * * * * B7: ........................... Transmit side voice/silence detection 0: Silence 1: Voice B6, B5: .................... Transmit side silence level (indicator) MSM7586-01 (0,0):Below –60 dBm0 (0,1): –50 to –60 dBm0 (1,0): –40 to –50 dBm0 (1,1): Above –40 dBm0 MSM7586-03 (0,0):Below –50 dBm0 (0,1): –40 to –50 dBm0 (1,0): –30 to –40 dBm0 (1,1): Above –30 dBm0 These outputs are enabled when the VOX function is turned ON by CRC6 - B7. B4, B3, B2, B1, B0: . Not used 40/42 ¡ Semiconductor MSM7586-01/03 APPLICATION CIRCUIT MSM7586 100 1 30 29 7 10 + – 10 mF 1 mF – 1 mF + 10 mF 1 mF – 1 mF + 10 mF 1 mF 11 9 67 8 68 1000 pF 97 2 3 RF 4 5 MIC 1 mF SGCT R1 R2 12 13 14 R3 18 R4 19 25 Speaker R8 Sounder Ringer 19.2 MHz PDN2 VDAM PDN1 VDDC PDN0 VDAC DENM SGM EXCKM SGCR DOUTM SGCT DINM AGC BSTO DGC TXCI AGM TXCO DGM TXD TXW IFIN RXD Q– RXC Q+ RPR I– AFC I+ RCW SLS AIN1+ RXSC AIN1– GSX1 PDN3 AIN2 RESET GSX2 DINC AOUT+ DOUTC AOUT– EXCKC PWI R5 22 VFRO R7 26 SAO 27 AIN3 28 GSX3 32 AIN4 33 GSX4 38 TOUT1 39 TOUT2 40 TOUT3 DENC 24 R6 VDDM 23 90 91 95 92 BCLK XSYNC RSYNC PCMSO PCMSI IS IR PCMRO PCMRI MCK IFCK X1 VOXI VOXO 87 88 89 79 78 77 76 69 71 MODEM CONT. 72 73 74 81 82 83 84 85 98 99 41 42 44 45 46 47 61 60 59 57 56 VDDC 500 W ADPCM CODEC CONT. 55 53 52 51 49 50 X2 R1 ≥ Output drive resistance of MIC R2//R3 ≥ 20 kW R4, R5, R7 ≥ 20 kW R6//Input resistance of speaker ≥ 1.2 kW R8//Input resistance of sounder ≥ 150 W 41/42 ¡ Semiconductor MSM7586-01/03 PACKAGE DIMENSIONS (Unit : mm) TQFP100-P-1414-0.50-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.55 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 42/42