MWS5114 1024-Word x 4-Bit LSI Static RAM March 1997 Features Description • Fully Static Operation The MWS5114 is a 1024 word by 4-bit static random access memory that uses the ion-implanted silicon gate complementary MOS (CMOS) technology. It is designed for use in memory systems where low power and simplicity in use are desirable. This type has common data input and data output and utilizes a single power supply of 4.5V to 6.5V. • Industry Standard 1024 x 4 Pinout (Same as Pinouts for 6514, 2114, 9114, and 4045 Types) • Common Data Input and Output • Memory Retention for Standby Battery Voltage as Low as 2V Min The MWS5114 is supplied in 18 lead, hermetic, dual-in-line sidebrazed ceramic packages (D suffix) and in 18 lead dualin-line plastic packages (E suffix). • All Inputs and Outputs Directly TTL Compatible • Three-State Outputs • Low Standby and Operating Power Ordering Information 200ns 250ns 300ns TEMPERATURE RANGE MWS5114E3 MWS5114E2 MWS5114E2X MWS5114E1 0oC to +70oC MWS5114D3 MWS5114D3X MWS5114D2 MWS5114D1 0oC to +70oC PACKAGE PKG. NO. PDIP Burn-In E18.3 E18.3 SBDIP Burn-In D18.3 D18.3 Pinout MWS5114 (PDIP, SBDIP) TOP VIEW A6 1 18 VDD A5 2 17 A7 A4 3 16 A8 A3 4 15 A9 A0 5 14 I/O1 A1 6 13 I/O2 A2 7 12 I/O3 CS 8 11 I/O4 VSS 9 10 WE OPERATIONAL MODES FUNCTION CS WE DATA PINS Read 0 1 Output: Dependent on data Write 0 0 Input Not Selected 1 X High Impedance CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 6-160 File Number 1325.2 MWS5114 Functional Block Diagram A4 VDD A5 A6 VSS MEMORY ARRAY 64 ROWS 64 COLUMNS ROW SELECT A7 A8 A9 I/O1 I/O2 COLUMN I/O CIRCUITS INPUT DATA CONTROL COLUMN SELECT I/O3 A0 I/O4 CS ENABLE WE 6-161 A1 A2 A3 MWS5114 Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) Plastic DIP Package . . . . . . . . . . . . . . 75 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 75 20 Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature. . . . . . . . . . . . . . . . . . . . . . . . . +265oC Recommended Operating Conditions At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS ALL TYPES PARAMETER MIN MAX UNITS DC Operating Voltage Range 4.5 6.5 V Input Voltage Range VSS VDD V Static Electrical Specifications At TA = 0oC to +70oC, VDD = ±5%, Except as Noted CONDITIONS LIMITS MWS5114-3 MWS5114-2 MWS5114-1 SYMBOL VO (V) VIN (V) VDD (V) MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX UNITS Quiescent Device Current IDD - 0, 5 5 - 75 100 - 75 100 - 75 250 µA Output Low (Sink) Current IOL 0.4 0, 5 5 2 4 - 2 4 - 2 4 - mA Output High (Source) Current IOH 4.6 0, 5 5 -0.4 -1 - -0.4 -1 - -0.4 -1 - mA Output Voltage Low-Level VOL - 0, 5 5 - 0 0.1 - 0 0.1 - 0 0.1 V Output Voltage High-Level VOH - 0, 5 5 4.9 5 - 4.9 5 - 4.9 5 - V Input Low Voltage VIL 0.5, 4.5 - 5 - 1.2 0.8 - 1.2 0.8 - 1.2 0.8 V Input High Voltage VIH 0.5, 4.5 - 5 2.4 - - 2.4 - - 2.4 - - V Input Leakage Current (Note 2) IIN - 0, 5 5 - ±0.1 ±5 - ±0.1 ±5 - ±0.1 ±5 µA Operating Current (Note 3) IDD1 - 0, 5 5 - 4 8 - 4 8 - 4 8 mA PARAMETER 6-162 MWS5114 Static Electrical Specifications At TA = 0oC to +70oC, VDD = ±5%, Except as Noted (Continued) CONDITIONS LIMITS MWS5114-3 MWS5114-2 MWS5114-1 PARAMETER SYMBOL VO (V) VIN (V) VDD (V) MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX UNITS Three-State Output Leakage Current (Note 4) IOUT 0, 5 0, 5 5 - ±0.5 ±5 - ±0.5 ±5 − ±0.5 ±5 µA Input Capacitance CIN - - - - 5 7.5 - 5 7.5 - 5 7.5 pF Output Capacitance COUT - - - - 10 15 - 10 15 - 10 15 pF NOTES: 1. Typical values are for TA = 25oC and nominal VDD . 2. All inputs in parallel. 3. Outputs open circuited; cycle time = 1µs. 4. All outputs in parallel. 6-163 MWS5114 Dynamic Electrical Specifications at TA = 0oC to +70oC, VDD = 5V ±5%, Input tR, tF = 10ns; CL = 50pF and 1 TTL Load LIMITS MWS5114-3 PARAMETER SYMBOL (NOTE 1) MIN MWS5114-2 MWS5114-1 (NOTE 2) TYP MAX (NOTE 1) MIN (NOTE 2) TYP MAX (NOTE 1) MIN (NOTE 2) TYP MAX UNITS READ CYCLE TIMES (FIGURE 1) Read Cycle tRC 200 160 - 250 200 - 300 250 - ns Access from Address tAA - 160 200 - 200 250 - 250 300 ns Chip Selection to Output Valid tCO - 110 150 - 150 200 - 200 250 ns Chip Selection to Output Active tCX 20 100 - 20 100 - 20 100 - ns Output Three-State from Deselection tOTD - 75 125 - 75 125 - 75 125 ns Output Hold from Address Change tOHA 50 100 - 50 100 - 50 100 - ns tWC 200 160 - 250 200 - 300 220 - ns tW 125 100 - 150 120 - 200 140 - ns Write Release tWR 50 40 - 50 40 - 50 40 - ns Address to Chip Select Setup Time tACS 0 0 - 0 0 - 0 0 - ns Address to Write Setup Time tAW 25 20 - 50 40 - 50 40 - ns Data to Write Setup Time tDSU 75 50 - 75 50 - 75 50 - ns tDH 30 10 - 30 10 - 30 10 - ns WRITE CYCLE TIMES (FIGURE 2) Write Cycle Write Data Hold from Write NOTES: 1. Time required by a limit device to allow for the indicated function. 2. Typical values are for TA = 25oC and nominal VDD. 6-164 MWS5114 tRC tAA ADDRESS CS tCO tOTD tCX DOUT tOHA ACTIVE VALID NOTE: 1. WE is high during the Read Cycle. Timing measurement reference level is 1.5V. FIGURE 1. READ CYCLE TIMING WAVEFORMS tWC ADDRESS tACS tWR CS tAW tW WE tDSU tDH DIN DON’T CARE VALID NOTE: 1. WE is low during the Write Cycle. Timing measurement reference level is 1.5V. FIGURE 2. WRITE CYCLE TIMING WAVEFORMS Data Retention Specifications at TA = 0oC to +70oC; See Figure 3 TEST CONDITIONS LIMITS ALL TYPES SYMBOL VDR (V) VDD (V) MIN (NOTE 1) TYP MAX UNITS VDR - - 2 - - V IDD 2 - - 25 50 µA MWS5114-2 2 - - 25 50 µA MWS5114-1 2 - - 60 125 µA tCDR - 5 300 - - ns Recovery to Normal Operation Time tRC - 5 300 - - ns VDD to VDR Rise and Fall Time tR, tF 2 5 1 - - µs PARAMETER Minimum Data Retention Voltage Data Retention Quiescent Current MWS5114-3 Chip Deselect to Data Retention Time NOTE: 1. Typical Values are for TA = 25oC and nominal VDD. 6-165 MWS5114 DATA RETENTION MODE VDD 0.95 VDD 0.95 VDD VDR tCDR tRC tR tF VIH CS VDR VIL VIH VIL FIGURE 3. LOW VDD DATA RETENTION TIMING WAVEFORMS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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