NC7SZ57 / NC7SZ58 TinyLogic® UHS Universal Configurable Two-Input Logic Gates Features Description Ultra High Speed Typical Usage Replaces Two (2) TinyLogic® Gate Devices Reduces Part Counts in Inventory The NC7SZ57 and NC7SZ58 are universal configurable two-input logic gates. Each device is capable of being configured for 1 of 5 unique two-input logic functions. Any possible two-input combinatorial logic function can be implemented, as shown in the Function Selection Table. Device functionality is selected by how the device is wired at the board level. Figures 4 through 13 illustrate how to connect the NC7SZ57 and NC7SZ58, respectively, for the desired logic function. All inputs have been implemented with hysteresis. Proprietary Noise/EMI Reduction Circuitry Implemented Capable of Implementing any Two-Input Logic Functions Broad VCC Operating Range: 1.65V to 5.5V Power Down High Impedance Input/Output Over-Voltage Tolerant Inputs Facilitate 5V to 3V Translation The device is fabricated with advanced CMOS technology to achieve ultra high speed with high output drive while maintaining low static power dissipation over a broad VCC operating range. The device is specified to operate over the 1.65V to 5.5V VCC operating range. The input and output are high impedance when VCC is 0V. Inputs tolerate voltages up to 5.5V independent of VCC operating range. Ordering Information Part Number Top Mark Package NC7SZ57P6X Z57 6-Lead SC70, EIAJ SC-88a, 1.25mm Wide NC7SZ57L6X KK 6-Lead Micropak™, 1.0mm Wide NC7SZ57FHX KK 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch NC7SZ58P6X Z58 6-Lead SC70, EIAJ SC-88a, 1.25mm Wide NC7SZ58L6X LL 6-Lead Micropak™, 1.0mm Wide NC7SZ58FHX LL 6-Lead, MicroPak2™ , 1x1mm Body, .35mm Pitch © 2000 Fairchild Semiconductor Corporation NC7SZ57 • NC7SZ58 • Rev. 1.0.4 Packing Method 3000 Units on Tape & Reel 5000 Units on Tape & Reel 3000 Units on Tape & Reel 5000 Units on Tape & Reel www.fairchildsemi.com NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates September 2011 Figure 1. SC70 (Top View) Figure 2. MicroPak™ (Top Through View) Figure 3. Pin 1 Orientation Notes: 1. AAA represents product code top mark (see Ordering Information). 2. Orientation of top mark determines pin one location. 3. Reading the top mark left to right, pin one is the lower left pin. Pin Definitions Pin # SC70 Pin # MicroPak™ Name 1 1 I1 2 2 GND 3 3 I0 Data Input 4 4 Y Output 5 5 VCC 6 6 I2 © 2000 Fairchild Semiconductor Corporation NC7SZ57 • NC7SZ58 • Rev. 1.0.4 Description Data Input Ground NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates Pin Configurations Supply Voltage Data Input www.fairchildsemi.com 2 Inputs NC7SZ57 NC7SZ58 I2 I1 I0 Y = (I0) • (I2) + (I1) • (I2) Y = (I0) • (I2) + (I1) • (I2) L L L H L L L H L H L H L H L L H H L H H L L L H H L H L H H H L H L H H H H L H = HIGH Logic Level L = LOW Logic Level Function Selection Table 2-Input Logic Function Device Selection Connection Configuration 2-Input AND NC7SZ57 Figure 4 2-Input AND with Inverted Input NC7SZ58 Figure 10, Figure 11 2-Input AND with Both Inputs Inverted NC7SZ57 Figure 7 2-Input NAND NC7SZ58 Figure 9 2-Input NAND with Inverted Input NC7SZ57 Figure 5, Figure 6 2-Input NAND with Both Inputs Inverted NC7SZ58 Figure 12 2-Input OR NC7SZ58 Figure 12 2-Input OR with Inverted Input NC7SZ57 Figure 5, Figure 6 2-Input OR with Both Inputs Inverted NC7SZ58 Figure 9 2-Input NOR NC7SZ57 Figure 7 2-Input NOR with Inverted Input NC7SZ58 Figure 9, Figure 10 2-Input NOR with Both Inputs Inverted NC7SZ57 Figure 4 2-Input XOR NC7SZ58 Figure 13 2-Input XNOR NC7SZ57 Figure 8 © 2000 Fairchild Semiconductor Corporation NC7SZ57 • NC7SZ58 • Rev. 1.0.4 NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates Function Table www.fairchildsemi.com 3 two-input function. The logical implementation is next to the board-level physical implementation of how the pins of the function should be connected. Figure 4 through Figure 8 show the logical functions that can be implemented using the NC7SZ57. The diagrams show the DeMorgan’s equivalent logic duals for a given Figure 4. Figure 6. 2-Input AND Gate Figure 5. 2-Input NAND with Inverted B Input Figure 8. © 2000 Fairchild Semiconductor Corporation NC7SZ57 • NC7SZ58 • Rev. 1.0.4 2-Input NAND with Inverted A Input Figure 7. 2-Input XNOR Gate 2-Input NOR Gate NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates NC7SZ57 Logic Configurations www.fairchildsemi.com 4 implementation is next to the board-level physical implementation of how the pins of the function should be connected. Figure 9 through Figure 13 show the logical functions that can be implemented using the NC7SZ58. The diagrams show the DeMorgan’s equivalent logic duals for a given two-input function. The logical Figure 9. Figure 11. 2-Input NAND Gate Figure 10. 2-Input AND with Inverted A Input 2-Input AND with Inverted B Input Figure 13. © 2000 Fairchild Semiconductor Corporation NC7SZ57 • NC7SZ58 • Rev. 1.0.4 Figure 12. 2-Input XOR Gate 2-Input OR Gate NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates NC7SZ58 Logic Configurations www.fairchildsemi.com 5 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Units VCC Supply Voltage -0.5 7.0 V VIN DC Input Voltage -0.5 7.0 V VOUT 7.0 V IIK DC Input Diode Current VIN < 0.5V -50 mA IOK DC Output Diode Current VOUT < -0.5V -50 mA IOUT ICC or IGND TSTG DC Output Voltage -0.5 DC Output Source / Sink Current ±50 mA DC VCC or Ground Current ±50 mA +150 °C Storage Temperature Range -65 TJ Maximum Junction Temperature under Bias +150 °C TL Lead Temperature, Soldering 10 Seconds +260 °C PD Power Dissipation at +85°C MicroPak™-6 130 SC70-6 180 MicroPak2™-6 ESD mW 120 Human Body Model, JEDEC:JESD22-A114 4000 Charged Device Model, JEDEC:JESD22-C101 2000 V Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC VIN VOUT TA JA Parameter Conditions Min. Max. Units V Supply Voltage Operating 1.65 5.5 Supply Voltage Data Retention 1.5 5.5 Input Voltage 0 5.5 V Output Voltage 0 VCC V -40 +85 °C Operating Temperature Thermal Resistance © 2000 Fairchild Semiconductor Corporation NC7SZ57 • NC7SZ58 • Rev. 1.0.4 SC70-6 350 MicroPak™-6 500 MicroPak2™-6 560 NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates Absolute Maximum Ratings °C/W www.fairchildsemi.com 6 Symbo l VP VN VH Parameter Positive Threshold Voltage Negative Threshold Voltage Hysteresis Voltage VCC Conditions Typ. Max. Min. Max. 1.65 0.60 0.99 1.40 0.60 1.40 1.00 1.39 1.80 1.00 1.80 3.00 1.30 1.77 2.20 1.30 2.20 4.50 1.90 2.49 3.10 1.90 3.10 5.50 2.20 2.95 3.60 2.20 3.60 1.65 0.20 0.50 0.90 0.20 0.90 2.30 0.40 0.75 1.15 0.40 1.15 3.00 0.60 0.99 1.50 0.60 1.50 4.50 1.00 1.43 2.00 1.00 2.00 5.50 1.20 1.70 2.30 1.20 2.30 1.65 0.15 0.48 0.90 0.15 0.90 2.30 0.25 0.64 1.10 0.25 1.10 3.00 0.40 0.78 1.20 0.40 1.20 4.50 0.60 1.06 1.50 0.60 1.50 5.50 0.70 1.25 1.70 0.70 1.70 1.65 1.55 1.65 1.55 2.20 2.30 2.20 2.90 3.00 2.90 4.40 4.50 4.40 3.00 VIN=VIH or VIL IOH= -100µA 4.50 VOH Min. TA=-40 to +85°C 2.30 2.30 HIGH Level Output Voltage TA=+25°C 1.65 IOH= -4mA 1.29 1.52 1.29 2.30 IOH= -8mA 1.90 2.15 1.90 3.00 VIN=VIH or VIL IOH= -16mA 2.40 2.80 2.40 3.00 IOH= -24mA 2.30 2.68 2.30 4.50 IOH= -32mA 3.80 4.20 3.80 Units V V V V Continued on the following page… © 2000 Fairchild Semiconductor Corporation NC7SZ57 • NC7SZ58 • Rev. 1.0.4 NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates DC Electrical Characteristics www.fairchildsemi.com 7 Symbol Parameter VCC TA=+25°C Conditions Min. Typ. 0.10 0.10 0.10 0.10 0.10 0.10 0.10 0.08 0.24 0.24 0.10 0.30 0.30 0.15 0.40 0.40 3.00 IOL=8mA VIN=VIH or IOL=16mA VIL IOL=24mA 0.22 0.55 0.55 4.50 IOL=32mA 0.22 0.55 0.55 VIN=VIH or VIL IOL=100µA IOL=4mA 1.65 3.00 Input Leakage Current IOFF Power Off Leakage Current ICC Quiescent Supply Current Units Max. 0.10 2.30 IIN Min. 1.65 4.50 VOL Max. 2.30 3.00 LOW Level Output Voltage TA=-40 to +85°C V 0 to 5.50 VIN 5.5V, GND ±0.1 ±1.0 µA 0 VIN or VOUT 5.5V 1 10 µA 1.65 to 5.5 VIN 5.5V, GND 1 10 µA Units Figure AC Electrical Characteristics Symbol Parameter VCC TA=25°C Conditions 1.8 ± 0.15 2.5 ± 0.2 tPHL, tPLH Propagation Delay In to Y 3.3 ± 0.3 5.0 ± 0.5 3.3 ± 0.3 5.0 ± 0.5 CIN Input Capacitance CPD Power Dissipation Capacitance CL=15pF, RL=1M CL=50pF, RL=500 0 Min. Typ. Max. Min. Max. 3.0 8.0 14.0 3.0 14.5 1.5 4.9 8.0 1.5 8.5 1.2 3.7 5.3 1.2 5.7 0.8 2.8 4.3 0.8 4.6 1.5 4.2 6.0 1.5 6.5 1.0 3.4 4.9 1.0 5.3 2 3.3 TA=-40 to 85°C ns Figure 14 Figure 16 pF 14 Note 4 pF 5.0 Figure 15 17 Note: 4. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output loading and operating at 50% duty cycle. (See Figure 12) CPD is related to ICCD dynamic operatic current by the expression: ICCD = (CPD)(VCC)(fin) + (ICCstatic). © 2000 Fairchild Semiconductor Corporation NC7SZ57 • NC7SZ58 • Rev. 1.0.4 NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates DC Electrical Characteristics (Continued) www.fairchildsemi.com 8 Note: 5. CL includes load and stray capacitance. 6. Input PRR = 1.0MHz, tW = 500ns. Figure 14. AC Test Circuit Note: 7. Input = AC waveforms. 8. PRR = Variable; Duty Cycle = 50%. © 2000 Fairchild Semiconductor Corporation NC7SZ57 • NC7SZ58 • Rev. 1.0.4 Figure 15. ICCD Test Circuit Figure 16. AC Waveforms NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates AC Loadings and Waveforms www.fairchildsemi.com 9 SYMM C L 2.00±0.20 0.65 A 0.50 MIN 6 4 B PIN ONE 1.25±0.10 1 1.90 3 0.30 0.15 (0.25) 0.40 MIN 0.10 0.65 A B 1.30 LAND PATTERN RECOMMENDATION 1.30 1.00 0.80 SEE DETAIL A 1.10 0.80 0.10 C 0.10 0.00 C 2.10±0.30 SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE (R0.10) 0.25 0.10 0.20 A) THIS PACKAGE CONFORMS TO EIAJ SC-88, 1996. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. D) DRAWING FILENAME: MKT-MAA06AREV6 30° 0° 0.46 0.26 DETAIL A SCALE: 60X Figure 17. 6-Lead, SC70, EIAJ SC-88a, 1.25mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf Package Designator P6X © 2000 Fairchild Semiconductor Corporation NC7SZ57 • NC7SZ58 • Rev. 1.0.4 Tape Section Cavity Number Leader (Start End) 125 (Typical) Cavity Status Cover Type Status Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 10 2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X 0.25 0.15 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X BOTTOM VIEW DETAIL A PIN 1 TERMINAL 0.075 X 45 CHAMFER (0.13) 4X Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M-1994 4. FILENAME AND REVISION: MAC06AREV4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT. Figure 18. 6-Lead, MicroPak™, 1.0mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. Package Designator L6X © 2000 Fairchild Semiconductor Corporation NC7SZ57 • NC7SZ58 • Rev. 1.0.4 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 11 0.89 0.35 0.05 C 1.00 2X B A 5X 0.40 PIN 1 MIN 250uM 0.66 1.00 1X 0.45 6X 0.19 0.05 C TOP VIEW RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB 2X 0.90 0.05 C 0.35 0.55MAX C 5X 0.52 SIDE VIEW 0.73 (0.08) 4X 1 DETAIL A 2 1X 0.57 0.09 0.19 6X 3 0.20 6X ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION (0.05) 6X 5X 0.35 0.25 6 5 4 0.35 0.60 (0.08) 4X 0.10 .05 C C B A 0.40 0.30 BOTTOM VIEW NOTES: A. COMPLIES TO JEDEC MO-252 STANDARD B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LANDPATTERN RECOMMENDATION IS BASED ON FSC DESIGN. E. DRAWING FILENAME AND REVISION: MGF06AREV3 Figure 19. 0.075X45° CHAMFER DETAIL A PIN 1 LEAD SCALE: 2X 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf. Package Designator FHX © 2000 Fairchild Semiconductor Corporation NC7SZ57 • NC7SZ58 • Rev. 1.0.4 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 12 NC7SZ57 / NC7SZ58 — TinyLogic® UHS Universal Configuration Two-Input Logic Gates © 2000 Fairchild Semiconductor Corporation NC7SZ57 • NC7SZ58 • Rev. 1.0.4 www.fairchildsemi.com 13