ONSEMI NCP434

NCP434, NCP435
2A Ultra-Small Controlled
Load Switch with
Auto-Discharge Path
The NCP434 and NCP435 are a low Ron MOSFET controlled by
external logic pin, allowing optimization of battery life, and portable
device autonomy.
Indeed, due to a current consumption optimization with PMOS
structure, leakage currents are eliminated by isolating connected IC’s
on the battery when not used.
Output discharge path is also embedded to eliminate residual
voltages on the output (NCP435 only).
Available in wide input voltage range from 1.0 V to 4.0 V, and a very
small 0.96 x 0.96 mm WLCSP4, 0.5 mm pitch.
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MARKING
DIAGRAM
1
WLCSP4
CASE 567FG
XX
Features
•
•
•
•
•
•
•
= Specific Device Code
PIN DIAGRAM
1 V − 3.6 V Operating Range
29 mW P MOSFET at 3.3 V
DC current up to 2 A
Output Auto−discharge (NCP435)
Active high EN pin
WLCSP4 0.96 x 0.96 mm
These are Pb−Free Devices
Typical Applications
•
•
•
•
•
XX
Mobile Phones
Tablets
Digital Cameras
GPS
Portable Devices
1
2
A
OUT
IN
B
GND
EN
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
V+
LS
NCP435
DCDC Converter
A2
or
LDO
B2
IN
OUT
EN GND
A1
Platform IC’n
B1
ENx
EN
0
Figure 1. Typical Application Circuit
© Semiconductor Components Industries, LLC, 2013
March, 2013 − Rev. 4
1
Publication Order Number:
NCP435/D
NCP434, NCP435
PIN FUNCTION DESCRIPTION
Pin Name
Pin Number
Type
Description
IN
A2
POWER
Load−switch input voltage; connect a 1 mF or greater ceramic capacitor from IN to GND as
close as possible to the IC.
GND
B1
POWER
Ground connection.
EN
B2
INPUT
OUT
A1
OUTPUT
Enable input, logic high turns on power switch.
Load−switch output; connect a 1 mF ceramic capacitor from OUT to GND as close as
possible to the IC is recommended.
BLOCK DIAGRAM
IN: Pin A2
OUT: Pin A1
Gate driver and soft
start control
Control
logic
EN: Pin B2
Optional:
NCP435
EN block
GND: Pin B1
Figure 2. Block Diagram
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VEN , VIN , VOUT
−0.3 to + 4.0
V
VIN , VOUT
0 to + 4.0
V
TJ
−40 to + 125
°C
Storage Temperature Range
TSTG
−40 to + 150
°C
Moisture Sensitivity (Note 1)
MSL
Level 1
IN, OUT, EN, Pins
From IN to OUT Pins: Input/Output
Maximum Junction Temperature
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
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2
NCP434, NCP435
OPERATING CONDITIONS
Symbol
Parameter
VIN
Operational Power Supply
VEN
Enable Voltage
Conditions
Min
Max
Unit
1.0
3.6
V
0
3.6
TA
Ambient Temperature Range
CIN
Decoupling input capacitor
1
mF
COUT
Decoupling output capacitor
1
mF
RqJA
Thermal Resistance Junction−to−Air
IOUT
Maximum DC current
PD
Power Dissipation Rating (Note 7)
−40
Typ
WLCSP package (Note 6)
25
+85
100
°C
°C/W
2
A
TA ≤ 25°C
WLCSP package
0.5
W
TA = 85°C
WLCSP package
0.2
W
2. According to JEDEC standard JESD22−A108.
3. This device series contains ESD protection and passes the following tests:
4. Human Body Model (HBM) ±4.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) ±250 V per JEDEC standard: JESD22−A115 for all pins.
Charge Device Model (CDM) ±2.0 kV per JEDEC standard: JESD22−C101 for all pins.
5. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78 class II.
6. The RqJA is dependent of the PCB heat dissipation and thermal via.
7. The maximum power dissipation (PD) is given by the following formula:
PD +
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3
T JMAX * T A
R qJA
NCP434, NCP435
ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C for VIN between 1.0 V to 3.6 V
(Unless otherwise noted). Typical values are referenced to TA = +25°C and VIN = 3.3 V (Unless otherwise noted).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
mW
POWER SWITCH
Static drain−source on−
state resistance
RDS(on)
RDIS
Output discharge path
VIN = 4 V
TA = 25°C, I = 200 mA (Note 9)
27
30
VIN = 3.3 V
TA = 25°C, I = 200 mA
29
34
VIN = 3.3 V
TA = 85°C
VIN = 1.8 V
TA = 25°C, I = 200 mA
43
38
52
VIN = 1.2 V
TA = 25°C, I = 200 mA
80
120
VIN = 1.1 V
TA = 25°C, I = 100 mA
110
EN = low
VIN = 3.3 V, NCP435 only
65
90
W
TR
Output rise time
VIN = 3.3 V
CLOAD = 1 mF, RLOAD = 25 W
(Note 8)
35
61
90
ms
TF
Output fall time
VIN = 3.3 V
CLOAD = 1 mF, RLOAD = 25 W
(Note 8)
20
42
70
ms
Ton
Gate turn on
VIN = 3.3 V
Gate turn on + Output rise time
65
126
190
ms
Ten
Enable time
VIN = 3.3 V
From EN low to high to
VOUT = 10% of fully on
30
66
100
ms
VIH
High−level input voltage
VIL
Low−level input voltage
REN
Pull down resistor
0.9
V
0.5
V
5.1
7
MW
VIN = 3.3 V, EN = low, No load
0.15
0.6
mA
VIN = 3.3 V, EN = high, No load
0.3
0.6
mA
QUIESCENT CURRENT
IQ
Current consumption
8. Parameters are guaranteed for CLOAD and RLOAD connected to the OUT pin with respect to the ground
9. Guaranteed by design and characterization, not production tested.
TIMINGS
VIN
EN
VOUT
TEN
TR
TDIS
TOFF
TON
Figure 3. Enable, Rise and fall time
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4
TF
NCP434, NCP435
TYPICAL CHARACTERISTICS
Figure 4. RDS(on) (mW) vs. VIN (V) from
1 V to 2. 6 V
Figure 5. RDS(on) (mW) vs. VIN (V) from
1 V to 4 V
Figure 6. RDS(on) (mW) vs. Iload (mA)
Figure 7. RDS(on) (mW) vs. Temperature
(5C)
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5
NCP434, NCP435
Figure 9. RDS(on) (mW) vs.
Current (mA)
Figure 8. RDS(on) (mW) vs.
Temperature (5C) at 1.2 V and
3.6 V
Figure 10. Standby Current (mA)
versus VIN (V), No Load
Figure 11. Standby Current (mA)
versus VIN (V), VOUT Short to GND
Figure 12. Quiescent Current (mA) versus VIN (V), No Load
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6
NCP434, NCP435
Figure 13. Enable Time, Rise Time, and Ton Time
Figure 14. Disable Time, Fall Time and Toff Time
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7
NCP434, NCP435
FUNCTIONAL DESCRIPTION
Overview
The auto−discharge is activated when EN pin is set to low
level (disable state).
The discharge path ( Pull down NMOS) stays activated as
long as EN pin is set at low level and VIN > 1.0 V.
In order to limit the current across the internal discharge
NMOSFET, the typical value is set at 65 W.
The NCP434 − NCP435 are high side P channel MOSFET
power distribution switch designed to isolate ICs connected
on the battery in order to save energy. The part can be turned
on, with a range of battery from 1.0 V to 4 V.
Enable Input
Enable pin is an active high. The path is opened when EN
pin is tied low (disable), forcing P MOS switch off.
The IN/OUT path is activated with a minimum of VIN of
1.0 V and EN forced to high level.
CIN and COUT Capacitors
IN and OUT, 1 mF, at least, capacitors must be placed as
close as possible the part for stability improvement.
Auto Discharge (NCP435 Only)
NMOS FET is placed between the output pin and GND,
in order to discharge the application capacitor connected on
OUT pin.
APPLICATION INFORMATION
Power Dissipation
TJ + RD
Main contributor in term of junction temperature is the
power dissipation of the power MOSFET. Assuming this,
the power dissipation and the junction temperature in
normal mode can be calculated with the following
equations:
P D + R DS(on)
PD
RDS(on)
IOUT
ǒIOUTǓ
TJ
RqJA
TA
R qJA ) T A
= Junction temperature (°C)
= Package thermal resistance (°C/W)
= Ambient temperature (°C)
PCB Recommendations
2
The NCP434 − NCP435 integrate an up to 2 A rated
PMOS FET, and the PCB design rules must be respected to
properly evacuate the heat out of the silicon. By increasing
PCB area, especially around IN and OUT pins, the RqJA of
the package can be decreased, allowing higher power
dissipation.
= Power dissipation (W)
= Power MOSFET on resistance (W)
= Output current (A)
Figure 15. Routing Example 1 oz, 2 Layers, 1005C/W
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8
NCP434, NCP435
Figure 16. Routing Example 2 oz, 4 Layers, 605C/W
Example of Application Definition
T J * T A + R qJA
P D + R qJA
R DS(on)
At 2 A, 25°C ambient temperature, RDS(on) 44 mW @ VIN
1.8 V, the junction temperature will be:
I2
T J + R qJA
TJ: Junction Temperature.
TA: Ambient Temperature.
Rq = Thermal resistance between IC and air, through PCB.
RDS(on): intrinsic resistance of the IC MOSFET.
I: load DC current.
P D + 25 ) ǒ0.044
2 2Ǔ
100 + 46° C
Taking into account of Rtq obtain with:
• 2 oz, 4 layers: 60°C/W.
At 2 A, 25°C ambient temperature, RDS(on) 44 mW @ VIN
1.8 V, the junction temperature will be:
Taking into account of Rq obtain with:
TJ + TA ) Rq
• 1 oz, 2 layers: 100°C/W.
P D + 25 ) ǒ0.044
2 2Ǔ
60 + 35.5° C
ORDERING INFORMATION
Marking
Package
Shipping†
NCP434FCT2G
AJ
WLCSP 0.96 x 0.96 mm
(Pb−Free)
3000 / Tape & Reel
NCP435FCT2G
AH
WLCSP 0.96 x 0.96 mm
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NCP434, NCP435
PACKAGE DIMENSIONS
WLCSP4, 0.96x0.96
CASE 567FG
ISSUE O
ÈÈ
ÈÈ
D
PIN A1
REFERENCE
2X
0.05 C
2X
0.05 C
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
B
E
DIM
A
A1
A2
b
D
E
e
TOP VIEW
A2
0.05 C
RECOMMENDED
SOLDERING FOOTPRINT*
A
A1
0.05 C
NOTE 3
4X
0.03 C
SEATING
PLANE
e
b
0.05 C A B
C
SIDE VIEW
A1
MILLIMETERS
MIN
MAX
0.54
0.63
0.22
0.28
0.33 REF
0.29
0.34
0.96 BSC
0.96 BSC
0.50 BSC
0.50
PITCH
e
B
PACKAGE
OUTLINE
4X
0.50
PITCH
0.25
DIMENSIONS: MILLIMETERS
A
1
2
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
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any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
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PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
NCP435/D