ONSEMI NIS1050MNTBG

NIS1050
Protection Interface Circuit
for PMICs with Integrated
OVP Control
The NIS1050 is a protection IC targeted at the latest generation of
PMICs from the leading mobile phone and UMPC chipset vendors. It
includes a highly stable low-current LDO and a low impedance power
N-Channel MOSFET.
The LDO provides a low current, five volt supply to the PMIC, and
the NFET is the external pass element for the OVIC circuit. These
stages combine with the internal PMIC to protect the charging circuit
from low-impedance overvoltage conditions that can occur from
either the AC/DC or USB supply.
The NIS1050 is available in the low−profile 6-lead 2x2mm WDFN6
surface mount package.
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MARKING
DIAGRAMS
1
PM M
WDFN6, 2x2
CASE 506AN
PM = Specific Device Code
M = Date Code
Features
• Lower Power Dissipation and Higher Efficiency vs. Zener Shunt
•
•
•
ORDERING INFORMATION
Regulator
LDO Highly Stable across Temperature, Operates Without Bypass
Capacitors
Wide 3-30 V Power Supply Voltage Input Range
Low−Profile (0.75mm) 6-Lead 2x2mm WDFN6 Package
Device
Package
Shipping†
NIS1050MNTBG
WDFN6
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Typical Applications
• Power Interface for New Generation PMICs from Leading Mobile
PMIC
OVP_SNS
3,7
6,8
2
NIS1050
Voltage
Detector
2
LDO
5
OVP_CLAMP
Bandgap
Reference
4
Over−Voltage
Protection
V_IN_OKAY
V_REF_2
V_REF_1
OVP_CTL
1
3
LDO
other
control
inputs
A) If okay, FET is closed
B) If not okay, FET is opened
4
Controller
VCHG
Vbus
VCHG
10k
USB
4.7uF
Vout, OUTPUT VOLTAGE (V)
Phone and UMPC Chipset Vendors
5.30
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
−40 −15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 1. Typical Application
© Semiconductor Components Industries, LLC, 2009
July, 2009 − Rev. 0
Figure 2. Output Voltage Variation with
Temperature
1
Publication Order Number:
NIS1050/D
NIS1050
1
8
2
3
6
5
7
4
Figure 3. Pin Assignment
Table 1. FUNCTIONAL PIN DESCRIPTION
Pin
Function
Description
1
Source
2
Gate
3, 7
Vin
4
Ground
5
Vout
This is the output of the internal LDO. It passes the input voltage through to the output and clamps
that voltage if it exceeds the regulation limit.
6, 8
Drain
Positive input voltage to the device.
This is the source of the power FET and connects to the PMIC pin of the same name.
This pin is the gate of the FET switch.
Positive input voltage to the device.
Negative input voltage to the device. This is used as the internal reference for the IC.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage, Operating, Steady-State (OVP_sense to Gnd)
Vin
-0.3 to 30
V
Gate-to-Source Voltage
VGS
±8
V
Drain Current, Peak (10 ms pulse)
IDpk
20
A
Drain Current, Continuous (Note 1, Steady-State)
TA = 25°C
TA = 85°C
ID
A
Total Power Dissipation @ TA = 25°C (Note 1, 2)
Pmax
750
mW
Operating Temperature Range
TJ
-40 to 125
°C
Non-operating Temperature Range
TJ
-55 to 150
°C
Maximum Lead Temperature for Soldering Purposes
TL
260
°C
3.7
2.7
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Surface Mounted on FR4 Board using the minimum recommended pad size of 30 mm2, 2 oz Cu.
2. Dual die operation (equally−heated).
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
Unit
Junction-to-Ambient – Steady State (Note 3)
RqJA
83
°C/W
Junction-to-Ambient – Steady State Min Pad (Note 4)
RqJA
177
Junction-to-Ambient – t ≤ 5 s (Note 3)
RqJA
54
Junction-to-Ambient – Steady State (Note 3)
RqJA
58
Junction-to-Ambient – Steady State Min Pad (Note 4)
RqJA
133
Junction-to-Ambient – t ≤ 5 s (Note 3)
RqJA
40
SINGLE DIE OPERATION (SELF-HEATED)
DUAL DIE OPERATION (EQUALLY-HEATED)
3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm2, 2 oz Cu).
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2
°C/W
NIS1050
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: Vcc (OVP_sense) = 5.0 V, TJ = 25°C)
Symbol
Characteristics
Min
Typ
Max
Unit
POWER FET
Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 V)
TJ = 85°C
IDSS
1.0
10
mA
Gate-to-Source Leakage Current (VDS = 0 V, VGS = ±8 V)
IGSS
100
nA
1.0
V
Gate Threshold Voltage (VGS = VDS, ID = 250 mA)
VGS(th)
Negative Gate Threshold Temperature Coefficent
VGS(th)/TJ
2.8
RDS(on)
47
56
Forward Transconductance (VDS = 5 V, ID = 2.0 A)
gFS
4.5
S
Input Capacitance (VDS = 15 Vdc, VGS = 0 Vdc, f = 1 MHz)
CISS
427
pF
Output Capacitance (VDS = 15 Vdc, VGS = 0 Vdc, f = 1 MHz)
COSS
51
pF
Reverse Transfer Capacitance (VDS = 15 Vdc, VGS = 0 Vdc, f = 1 MHz)
CRSS
32
pF
Drain-to-Source On-Resistance (Note 5)
VGS = 4.5 V, ID = 2.0 A
VGS = 2.5 V, ID = 2.0 A
0.4
0.7
mV/°C
mW
70
90
LDO (Unless otherwise noted, TJ = 25°C, Vin = 5.0 V)
Regulated Output Voltage (Vcc = 5.5 V Io = 1 mA)
Vout
Response to Input Transient
(Vin 0 to 30 volts, <1 ms rise time, 5.0 kW resistive load, Note 6)
Time for signal above 5.5 volts
Peak Voltage
4.6
5.0
5.3
V
tpulse
Vpk
5.0
9.0
ms
V
Headroom (Vin – Vout, Iout = 1.2 mA, Vin = 4.6 V)
Vhead
150
mV
Headroom (Vin – Vout, Iout = 10 mA, Vin = 4.8 V, TJ = -40 to 125°C)
Vhead
1000
mV
850
mA
3.0
V
TOTAL DEVICE
Input Bias Current
Ibias
Minimum Operating Voltage
Vin-min
5. Pulse test: Pulse width 300 ms, duty cycle 2%.
6. Guaranteed by design.
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3
110
NIS1050
ID, DRAIN CURRENT (AMPS)
5
VGS = 1.7 V to 8 V
TJ = 25°C
1.6 V
4
3
1.5 V
2
1.4 V
1.3 V
1
1.2 V
0
0
1
3
2
4
5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
TYPICAL PERFORMANCE CURVES
1.6
1.4
ID = 2 A
VGS = 4.5 V
1.2
1.0
0.8
0.6
−50
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. On−Region Characteristics
Figure 5. On−Resistance Variation with
Temperature
5.30
Vout, OUTPUT VOLTAGE (V)
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
−40
−15
10
35
60
85
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Output Voltage Variation with
Temperature
Mounting Considerations
impedance of the FET will not vary significantly since pad
6 is part of the lead-frame and therefore connected to pad 8
by a metal path on the lead frame. The majority of the
package impedance comes from the resistance between the
source and pin 1, since this is connected by bond wires.
The LDO and MOSFET are both attached to thermal pads
to provide a low impedance path for the heat generated in
these devices. Both of these pads should have a solid
connection to as much board copper area as possible in order
to maintain a low operating temperature. The main purpose
of both of these pads is for thermal connections, not
electrical connections.
Pad 7 is the input voltage for the LDO. It is electrically
connected to the Vcc pin. This connection is optional and
will have a negligible difference in the electrical
performance of the chip due to the current into the LDO.
Pad 8 is the drain of the power MOSFET. This pad will
also have a low electrical impedance. Either pad 8, pad 6 or
both may be used for electrical connections. The total
Bypass Capacitors
The LDO has been designed to operate in a stable mode
without bypass capacitors; however, it is recommended to
use a low ESR capacitor if fast, ac transients or other
switching type currents will be present. Typically, a value of
1 to 10 nF is adequate for an output bypass capacitor. A 1 nF
capacitor may be added to the input if the input source is
noisy or if it has a high ac impedance due to long trace
lengths.
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4
NIS1050
PACKAGE DIMENSIONS
WDFN6, 2x2
CASE 506AN−01
ISSUE D
D
PIN ONE
REFERENCE
0.10 C
0.10 C
ÍÍ
ÍÍ
ÍÍ
ÇÇ
ÉÉ
EXPOSED Cu
PLATING
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MOLD CMPD
DETAIL B
OPTIONAL
CONSTRUCTIONS
E
TOP VIEW
DIM
A
A1
A3
b
D
D2
E
E2
e
F
K
L
L1
L
L
L1
DETAIL A
A3
DETAIL B
0.10 C
ÉÉÉ
ÉÉÉ
ÇÇÇ
A
B
OPTIONAL
CONSTRUCTIONS
A
0.08 C
NOTE 4
A1
C
SIDE VIEW
0.10 C A
L
SOLDERMASK DEFINED
MOUNTING FOOTPRINT
SEATING
PLANE
1.74
B
1
3
1.10
6X
DETAIL A
2X
0.77
D2
F
D2
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.25
0.35
2.00 BSC
0.57
0.67
2.00 BSC
0.90
1.10
0.65 BSC
0.15 BSC
0.25 REF
0.20
0.30
--0.10
0.47
2.30
E2
0.10 C A
B
PACKAGE
OUTLINE
6
K
4
6X
b
0.10 C A
e
0.05 C
1
B
NOTE 3
6X
BOTTOM VIEW
0.35
0.65
PITCH
DIMENSIONS: MILLIMETERS
The products described herein (NIS1050), may be covered by one or more U.S. patents.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NIS1050/D