PCF8576D Universal LCD driver for low multiplex rates Rev. 10 — 14 February 2011 Product data sheet 1. General description The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily cascaded for larger LCD applications. The PCF8576D is compatible with most microcontrollers and communicates via the two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). 2. Features and benefits AEC-Q100 compliant (PCF8576DT/S400/2) for automotive applications Single chip LCD controller and driver Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing Selectable display bias configuration: static, 1⁄2 or 1⁄3 Internal LCD bias generation with voltage-follower buffers 40 segment drives: Up to 20 7-segment numeric characters Up to 10 14-segment alphanumeric characters Any graphics of up to 160 elements 40 × 4-bit RAM for display data storage Auto-incremented display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5 V Wide logic LCD supply range: From 2.5 V for low-threshold LCDs Up to 6.5 V for high-threshold twisted nematic LCDs Low power consumption 400 kHz I2C-bus interface May be cascaded for large LCD applications (up to 2560 elements possible) No external components required Compatible with chip-on-glass and chip-on-board technology Manufactured in silicon gate CMOS process PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Type number Package Name Description Version TSSOP56 plastic thin shrink small outline package, 56 leads; body width 6.1 mm SOT364-1 PCF8576DT/S400/2 TSSOP56 plastic thin shrink small outline package, 56 leads; body width 6.1 mm SOT364-1 PCF8576DT/2 PCF8576DU/DA/2 wire bond die 59 bonding pads[1] PCF8576DU/2DA/2 bare die [1] Chips in tray. [2] Chips with bumps in tray. 59 bumps[2] PCF8576DU/DA PCF8576DU/2DA 4. Marking Table 2. PCF8576D Product data sheet Marking codes Type number Marking code PCF8576DT/2 PCF8576DT PCF8576DT/S400/2 PCF8576DT/S400 PCF8576DU/DA/2 PC8576D-2 PCF8576DU/2DA/2 PC8576D-2 All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 2 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 5. Block diagram BP0 BP2 BP1 BP3 S0 to S39 40 VLCD DISPLAY SEGMENT OUTPUTS BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY REGISTER OUTPUT BANK SELECT AND BLINK CONTROL DISPLAY CONTROLLER LCD BIAS GENERATOR VSS CLK SYNC OSC CLOCK SELECT AND TIMING BLINKER TIMEBASE OSCILLATOR POWER-ON RESET INPUT FILTERS I2C-BUS CONTROLLER DISPLAY RAM 40 × 4-BIT PCF8576D COMMAND DECODER WRITE DATA CONTROL DATA POINTER AND AUTO INCREMENT VDD SCL SDA SA0 SUBADDRESS COUNTER A0 A1 A2 001aai900 Fig 1. Block diagram of PCF8576D PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 3 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 6. Pinning information 6.1 Pinning BP2 1 56 BP0 BP1 2 55 VLCD BP3 3 54 VSS S0 4 53 SA0 S1 5 52 A2 S2 6 51 A1 S3 7 50 A0 S4 8 49 OSC S5 9 48 VDD S6 10 47 CLK S7 11 46 SYNC S8 12 45 SCL S9 13 44 SDA S10 14 S11 15 43 S39 PCF8576DT 42 S38 S12 16 41 S37 S13 17 40 S36 S14 18 39 S35 S15 19 38 S34 S16 20 37 S33 S17 21 36 S32 S18 22 35 S31 S19 23 34 S30 S20 24 33 S29 S21 25 32 S28 S22 26 31 S27 S23 27 30 S26 S24 28 29 S25 001aaf646 Top view. For mechanical details, see Figure 24. Fig 2. PCF8576D Product data sheet Pinning diagram for PCF8576DT/x (TSSOP56) All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 4 of 50 PCF8576D NXP Semiconductors S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Universal LCD driver for low multiplex rates 21 S3 S18 36 20 S2 S19 37 19 S1 S20 38 18 S0 S21 39 17 BP3 S22 40 16 BP1 S23 41 15 BP2 S24 42 14 BP0 S25 43 S26 44 13 VLCD S27 45 S28 46 S29 47 12 VSS S30 48 S31 49 11 SA0 S32 50 10 A2 S33 51 9 A1 53 54 55 56 57 58 59 1 2 3 4 5 6 7 8 S35 S36 S37 S38 S39 SDA SDA SDA SCL SCL SYNC CLK VDD OSC A0 C1 52 S34 C2 PCF8576DU 001aag424 Viewed from active side. C1 and C2 are alignment marks. For mechanical details, see Figure 25 and Figure 26. Fig 3. PCF8576D Product data sheet Pinning diagram for PCF8576DU/x (bare die) All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 5 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 6.2 Pin description Table 3. Symbol Product data sheet Pin Description PCF8576DT/x PCF8576DU/x SDA 44 1, 58, 59 I2C-bus serial data input and output SCL 45 2, 3 I2C-bus serial clock input CLK 47 5 external clock input or output VDD 48 6 supply voltage SYNC 46 4 cascade synchronization input or output OSC 49 7 internal oscillator enable input A0 to A2 50 to 52 8 to 10 subaddress inputs SA0 53 11 I2C-bus address input; bit 0 VSS 54 12[1] ground supply voltage VLCD 55 13 LCD supply voltage BP0, BP2, BP1, BP3 56, 1, 2, 3 14 to 17 LCD backplane outputs S0 to S39 4 to 43 18 to 57 LCD segment outputs n.c. - - not connected [1] PCF8576D Pin description The substrate (rear side of the die) is connected to VSS and should be electrically isolated. All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 6 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 7. Functional description The PCF8576D is a versatile peripheral device designed to interface any microprocessor or microcontroller with a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 40 segments. The possible display configurations of the PCF8576D depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 4. All of these configurations can be implemented in the typical system shown in Figure 4. Table 4. Selection of possible display configurations Number of Backplanes Icons 7-segment 14-segment Dot matrix/ Elements 4 160 20 10 160 (4 × 40) 3 120 15 7 120 (3 × 40) 2 80 10 5 80 (2 × 40) 1 40 5 2 40 (1 × 40) VDD R≤ Digits/Characters tr 2CB VDD VLCD SDA HOST MICROPROCESSOR/ MICROCONTROLLER 40 segment drives SCL PCF8576D OSC 4 backplanes A0 A1 A2 LCD PANEL (up to 160 elements) SA0 VSS VSS mdb079 The resistance of the power lines must be kept to a minimum. For chip-on-glass applications, due to the Indium Tin Oxide (ITO) track resistance, each supply line must be routed separately between the chip and the connector. Fig 4. Typical system configuration The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCF8576D. The internal oscillator is enabled by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application. 7.1 Power-on reset At power-on the PCF8576D resets to the following starting conditions: • • • • PCF8576D Product data sheet All backplane outputs are set to VLCD All segment outputs are set to VLCD The selected drive mode is: 1:4 multiplex with 1⁄3 bias Blinking is switched off All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 7 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates • • • • Input and output bank selectors are reset The I2C-bus interface is initialized The data pointer and the subaddress counter are cleared (set to logic 0) Display is disabled Data transfers on the I2C-bus must be avoided for 1 ms following power-on to allow the reset action to complete. 7.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between VLCD and VSS. The middle resistor can be bypassed to provide a 1⁄2 bias voltage level for the 1:2 multiplex configuration. The LCD voltage can be temperature compensated externally using the supply to pin VLCD. 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command (see Table 9) from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in Table 5. Table 5. Discrimination ratios LCD drive mode Number of: LCD bias Backplanes Levels configuration V off ( RMS ) ------------------------V LCD V on ( RMS ) ----------------------V LCD V on ( RMS ) D = -----------------------V off ( RMS ) static 1 2 static 0 1 ∞ 1:2 multiplex 2 3 1⁄ 2 0.354 0.791 2.236 4 1⁄ 3 0.333 0.745 2.236 1:3 multiplex 3 4 1⁄ 3 0.333 0.638 1.915 1:4 multiplex 4 4 1⁄ 3 0.333 0.577 1.732 1:2 multiplex 2 A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth. Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and hence the contrast ratios are smaller. 1 Bias is calculated by ------------- , where the values for a are 1+a a = 1 for 1⁄2 bias a = 2 for 1⁄3 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1 V on ( RMS ) = PCF8576D Product data sheet V LCD a 2 + 2a + n -----------------------------2 n × (1 + a) All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 (1) © NXP B.V. 2011. All rights reserved. 8 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates where the values for n are n = 1 for static mode n = 2 for 1:2 multiplex n = 3 for 1:3 multiplex n = 4 for 1:4 multiplex The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: V off ( RMS ) = V LCD a 2 – 2a + n -----------------------------2 n × (1 + a) (2) Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3: V on ( RMS ) D = ----------------------- = V off ( RMS ) 2 (a + 1) + (n – 1) -------------------------------------------2 (a – 1) + (n – 1) (3) Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with 1⁄ 2 bias is 1⁄ 2 bias 21 is ---------- = 1.528 . 3 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: • 1:3 multiplex (1⁄2 bias): V LCD = 6 × V off ( RMS ) = 2.449V off ( RMS ) 4 × 3) - = 2.309V off ( RMS ) • 1:4 multiplex (1⁄2 bias): V LCD = (--------------------3 These compare with V LCD = 3V off ( RMS ) when 1⁄3 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage. 7.3.1 Electro-optical performance Suitable values for Von(RMS) and Voff(RMS) are dependant on the LCD liquid used. The RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. For any given liquid, there are two threshold values defined. One point is at 10 % relative transmission (at Vlow) and the other at 90 % relative transmission (at Vhigh), see Figure 5. For a good contrast performance, the following rules should be followed: V on ( RMS ) ≥ V high (4) V off ( RMS ) ≤ V low (5) Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection of a, n (see Equation 1 to Equation 3) and the VLCD voltage. PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 9 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates Vlow and Vhigh are properties of the LCD liquid and can be provided by the module manufacturer. It is important to match the module properties to those of the driver in order to achieve optimum performance. 100 % Relative Transmission 90 % 10 % Vlow OFF SEGMENT Vhigh GREY SEGMENT VRMS [V] ON SEGMENT 001aam358 Fig 5. PCF8576D Product data sheet Electro-optical characteristic: relative transmission curve of the liquid All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 10 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Figure 6. Tfr LCD segments VLCD BP0 VSS state 1 (on) VLCD state 2 (off) Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V −VLCD VLCD state 2 0V −VLCD (b) Resultant waveforms at LCD segment. mgl745 (1) Vstate1(t) = VSn(t) − VBP0(t). (2) Von(RMS) = VLCD. (3) Vstate2(t) = VSn+1(t) − VBP0(t). (4) Voff(RMS) = 0 V. Fig 6. PCF8576D Product data sheet Static drive mode waveforms All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 11 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.2 1:2 Multiplex drive mode The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD bias voltages of 1⁄2 bias or 1⁄3 bias as shown in Figure 7 and Figure 8. Tfr VLCD BP0 LCD segments VLCD / 2 VSS state 1 VLCD BP1 state 2 VLCD / 2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD VLCD / 2 state 1 0V −VLCD / 2 −VLCD VLCD VLCD / 2 state 2 0V −VLCD / 2 −VLCD (b) Resultant waveforms at LCD segment. mgl746 (1) Vstate1(t) = VSn(t) − VBP0(t). (2) Von(RMS) = 0.791VLCD. (3) Vstate2(t) = VSn+1(t) − VBP1(t). (4) Voff(RMS) = 0.354VLCD. Fig 7. PCF8576D Product data sheet Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 12 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates Tfr VLCD BP0 LCD segments 2VLCD / 3 VLCD / 3 VSS state 1 VLCD BP1 state 2 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 Sn+1 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V −VLCD / 3 −2VLCD / 3 −VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V −VLCD / 3 −2VLCD / 3 −VLCD (b) Resultant waveforms at LCD segment. mgl747 (1) Vstate1(t) = VSn(t) − VBP0(t). (2) Von(RMS) = 0.745VLCD. (3) Vstate2(t) = VSn+1(t) − VBP1(t). (4) Voff(RMS) = 0.333VLCD. Fig 8. PCF8576D Product data sheet Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 13 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies (see Figure 9). Tfr VLCD BP0 LCD segments 2VLCD / 3 VLCD / 3 VSS state 1 VLCD BP1 state 2 2VLCD / 3 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD Sn+2 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V −VLCD / 3 −2VLCD / 3 −VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V −VLCD / 3 −2VLCD / 3 −VLCD (b) Resultant waveforms at LCD segment. mgl748 (1) Vstate1(t) = VSn(t) − VBP0(t). (2) Von(RMS) = 0.638VLCD. (3) Vstate2(t) = VSn+1(t) − VBP1(t). (4) Voff(RMS) = 0.333VLCD. Fig 9. PCF8576D Product data sheet Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 14 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see Figure 10). Tfr VLCD BP0 LCD segments 2VLCD / 3 VLCD / 3 VSS state 1 VLCD BP1 state 2 2VLCD / 3 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD BP3 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD Sn+2 2VLCD / 3 VLCD / 3 VSS VLCD Sn+3 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V −VLCD / 3 −2VLCD / 3 −VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V −VLCD / 3 −2VLCD / 3 −VLCD (b) Resultant waveforms at LCD segment. mgl749 (1) Vstate1(t) = VSn(t) − VBP0(t). (2) Von(RMS) = 0.577VLCD. (3) Vstate2(t) = VSn+1(t) − VBP1(t). (4) Voff(RMS) = 0.333VLCD. Fig 10. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 15 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 7.5 Oscillator 7.5.1 Internal clock The internal logic of the PCF8576D and its LCD drive signals are timed either by its internal oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used as the clock signal for several PCF8576Ds in the system that are connected in cascade. 7.5.2 External clock Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD frame signal frequency is determined by the clock frequency (fclk). Remark: A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. 7.6 Timing The PCF8576D timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the correct timing relationship between each PCF8576D in the system is maintained by the synchronization signal at pin SYNC. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency is a fixed division of the clock frequency from either the internal or an external f clk clock: f fr = ------- . 24 7.7 Display register The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and each column of the display RAM. 7.8 Segment outputs The LCD drive section includes 40 segment outputs S0 to S39 which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display latch. When less than 40 segment outputs are required, the unused segment outputs should be left open-circuit. 7.9 Backplane outputs The LCD drive section includes four backplane outputs BP0 to BP3 which must be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required, the unused outputs can be left open-circuit. In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 16 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.10 Display RAM The display RAM is a static 40 × 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The display RAM bit map Figure 11 shows the rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2 and BP3 respectively. display RAM addresses (columns)/segment outputs (S) 0 1 2 3 4 35 36 37 38 39 0 display RAM bits 1 (rows)/ backplane outputs 2 (BP) 3 mbe525 Display RAM bit map showing direct relationship between RAM addresses and segment outputs; also between bits in a RAM word and the backplane outputs. Fig 11. Display RAM bit map When display data is transmitted to the PCF8576D, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Figure 12; the RAM filling organization depicted applies equally to other LCD types. PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 17 of 50 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LCD segments Sn+2 Sn+3 static display RAM filling order b f Sn+1 BP0 rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 g e Sn+6 Sn Sn+7 c DP d n n+1 n+2 n+3 n+4 n+5 n+6 n+7 c x x x b x x x a x x x f x x x g x x x e x x x d x x x DP x x x Sn a b f g multiplex Sn+2 BP1 e Sn+3 c Sn+1 1:3 Sn+2 DP d a b Sn multiplex BP1 c b f BP0 g 18 of 50 © NXP B.V. 2011. All rights reserved. Sn+1 BP1 c d g e d DP n n+1 n+2 n+3 a b x x f g x x e c x x d DP x x MSB a b LSB f g e c d DP n rows display RAM 0 b rows/backplane 1 DP outputs (BP) 2 c 3 x n+1 n+2 a d g x f e x x MSB LSB b DP c a d g f e DP BP2 n rows display RAM 0 a rows/backplane 1 c BP3 outputs (BP) 2 b 3 DP n+1 f e g d MSB a c b DP f LSB e g d 001aaj646 x = data bit unchanged. Fig 12. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus PCF8576D multiplex e f columns display RAM address/segment outputs (s) byte1 byte2 byte3 byte4 byte5 a Sn 1:4 BP2 DP d c b a columns display RAM address/segment outputs (s) byte1 byte2 byte3 g e rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 BP0 f LSB Universal LCD driver for low multiplex rates Rev. 10 — 14 February 2011 All information provided in this document is subject to legal disclaimers. Sn+1 MSB columns display RAM address/segment outputs (s) byte1 byte2 BP0 1:2 transmitted display byte columns display RAM address/segment outputs (s) byte1 a Sn+4 Sn+5 LCD backplanes NXP Semiconductors PCF8576D Product data sheet drive mode PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates The following applies to Figure 12: • In the static drive mode, the eight transmitted data bits are placed in row 0 of eight successive 4-bit RAM words. • In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into row 0 and 1 of four successive 4-bit RAM words. • In the 1:3 multiplex mode, the eight bits are placed in triples into row 0, 1 and 2 to three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted. • In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into row 0, 1, 2 and 3 of two successive 4-bit RAM words. 7.11 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see Section 7.17). Following this command, an arriving data byte is stored at the display RAM address indicated by the data pointer. The filling order is shown in Figure 12. After each byte is stored, the content of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode: After each byte is stored, the contents of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode: • • • • In static drive mode by eight In 1:2 multiplex drive mode by four In 1:3 multiplex drive mode by three In 1:4 multiplex drive mode by two If an I2C-bus data access is terminated early then the state of the data pointer is unknown. The data pointer should be re-written prior to further RAM accesses. 7.12 Subaddress counter The storage of display data is determined by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter match with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the device-select command (see Section 7.17). If the contents of the subaddress counter and the hardware subaddress do not match then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 19 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF8576D occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 14th display data byte transmitted in 1:3 multiplex mode). The hardware subaddress must not be changed while the device is being accessed on the I2C-bus interface. 7.13 Output bank selector The output bank selector selects one of the four bits per display RAM address for transfer to the display latch. The actual bit chosen depends on the selected LCD drive mode in operation and on the instant in the multiplex sequence. • In 1:4 mode, all RAM addresses of bit 0 are selected, these are followed by the contents of bit 1, bit 2 and then bit 3. • In 1:3 mode, bits 0, 1 and 2 are selected sequentially • In 1:2 mode, bits 0 and 1 are selected • In static mode, bit 0 is selected The PCF8576D includes a RAM bank switching feature in the static and 1:2 drive modes. In the static drive mode, the bank-select command (see Section 7.17) may request the contents of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 7.14 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. The bank-select command (see Section 7.17) can be used to load display data in bit 2 in static drive mode or in bits 2 and 3 in 1:2 mode. The input bank selector functions are independent of the output bank selector. 7.15 Blinker The PCF8576D has a very versatile display blinking capability. The whole display can blink at a frequency selected by the blink-select command (see Section 7.17). Each blink frequency is a fraction of the clock frequency; the ratio between the clock frequency and blink frequency depends on the blink mode selected (see Table 6). An additional feature allows an arbitrary selection of LCD segments to blink in the static and 1:2 drive modes. This is implemented without any communication overheads by the output bank selector which alternates the displayed data between the data in the display RAM bank and the data in an alternative RAM bank at the blink frequency. This mode can also be implemented by the blink-select command (see Section 7.17). PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 20 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates In the 1:3 and 1:4 drive modes, where no alternative RAM bank is available, groups of LCD segments can blink selectively by changing the display RAM data at fixed time intervals. The entire display can blink at a frequency other than the nominal blink frequency by sequentially resetting and setting the display enable bit E at the required rate using the mode-set command (see Section 7.17). Table 6. Blinking frequencies[1] Blink mode Normal operating mode ratio off Nominal blink frequency - blinking off 1 f clk --------768 2 Hz 2 f clk -----------1536 1 Hz 3 f clk -----------3072 0.5 Hz [1] Blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz correspond to an oscillator frequency (fclk) of 1536 Hz (see Section 11). 7.16 Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.16.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 13). SDA SCL data line stable; data valid change of data allowed mba607 Fig 13. Bit transfer PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 21 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 7.16.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P (see Figure 14). SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 14. Definition of START and STOP conditions 7.16.3 System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Figure 15). MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER SDA SCL mga807 Fig 15. System configuration 7.16.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver which is addressed must generate an acknowledge after the reception of each byte. • Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 22 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is shown in Figure 16. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S START condition clock pulse for acknowledgement mbc602 Fig 16. Acknowledgement of the I2C-bus 7.16.5 I2C-bus controller The PCF8576D acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8576D are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. In single device applications, the hardware subaddress inputs A0, A1 and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress. 7.16.6 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 7.16.7 I2C-bus protocol Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8576D. The least significant bit of the slave address that a PCF8576D will respond to is defined by the level tied to its SA0 input. The PCF8576D is a write-only device and will not respond to a read access. Having two reserved slave addresses allows the following on the same I2C-bus: • Up to 16 PCF8576Ds for very large LCD applications • The use of two types of LCD multiplex drive. PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 23 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of two possible PCF8576D slave addresses available. All PCF8576Ds whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level. acknowledge by A0, A1 and A2 selected PCF8576D only acknowledge by all addressed PCF8576Ds R/W slave address S S 0 1 1 1 0 0 A 0 A C COMMAND A DISPLAY DATA A P 0 n ≥ 1 byte(s) 1 byte n ≥ 0 byte(s) update data pointers and if necessary, subaddress counter mdb078 Fig 17. I2C-bus protocol After an acknowledgement, one or more command bytes follow, that define the status of each addressed PCF8576D. The last command byte sent is identified by resetting its most significant bit, continuation bit C, (see Figure 18). The command bytes are also acknowledged by all addressed PCF8576D on the bus. MSB C LSB REST OF OPCODE msa833 Fig 18. Format of command byte After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data directed to the intended PCF8576D device. An acknowledgement after each byte is asserted only by the PCF8576Ds that are addressed via address lines A0, A1 and A2. After the last display byte, the I2C-bus master asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus access. PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 24 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 7.17 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. The commands available to the PCF8576D are defined in Table 7. Table 7. Definition of PCF8576D commands Command Operation Code Bit 7 6 Reference 5 4 3 2 1 0 mode-set C 1 0 [1] E B M1 M0 Table 9 load-data-pointer C 0 P5 P4 P3 P2 P1 P0 Table 10 device-select C 1 1 0 0 A2 A1 A0 Table 11 bank-select C 1 1 1 1 0 I O Table 12 blink-select C 1 1 1 0 A BF1 BF0 Table 13 [1] Not used. All available commands carry a continuation bit C in their most significant bit position as shown in Figure 18. When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is reset, it indicates that the command byte is the last in the transfer. Further bytes will be regarded as display data (see Table 8). Table 8. C bit description Bit Symbol 7 C Value continue bit 0 last control byte in the transfer; next byte will be regarded as display data 1 control bytes continue; next byte will be a command too Table 9. Mode-set command bits description Bit Symbol Value Description 7 C 0, 1 see Table 8 6, 5 - 10 fixed value 4 - - unused 3 E display status 0 1 2 Product data sheet disabled (blank)[1] enabled LCD bias configuration[2] B 1 to 0 PCF8576D Description 0 1⁄ 3 bias 1 1⁄ 2 bias M[1:0] LCD drive mode selection 01 static; BP0 10 1:2 multiplex; BP0, BP1 11 1:3 multiplex; BP0, BP1, BP2 00 1:4 multiplex; BP0, BP1, BP2, BP3 [1] The possibility to disable the display allows implementation of blinking under external control. [2] Not applicable for static drive mode. All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 25 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates Table 10. Load-data-pointer command bits description Bit Symbol Value Description 7 C 0, 1 see Table 8 6 - 0 fixed value 5 to 0 P[5:0] 000000 to 100111 6 bit binary value, 0 to 39; transferred to the data pointer to define one of forty display RAM addresses Table 11. Device-select command bits description Bit Symbol Value Description 7 C 0, 1 see Table 8 6 to 3 - 1100 fixed value 2 to 0 A[2:0] 000 to 111 3 bit binary value, 0 to 7; transferred to the subaddress counter to define one of eight hardware subaddresses Table 12. Bank-select command bits description Bit Symbol Value Description Static 7 C 0, 1 see Table 8 6 to 2 - 11110 fixed value 1 I input bank selection; storage of arriving display data 0 1 0 [1] O Product data sheet RAM bit 0 RAM bits 0 and 1 RAM bit 2 RAM bits 2 and 3 output bank selection; retrieval of LCD display data 0 RAM bit 0 RAM bits 0 and 1 1 RAM bit 2 RAM bits 2 and 3 The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. Table 13. Blink-select command bits description Bit Symbol Value Description 7 C 0, 1 see Table 8 6 to 3 - 1110 fixed value 2 A 1 to 0 PCF8576D 1:2 multiplex[1] blink mode selection 0 normal blinking[1] 1 alternate RAM bank blinking[2] BF[1:0] blink frequency selection 00 off 01 1 10 2 11 3 [1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. [2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 26 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 7.18 Display controller The display controller executes the commands identified by the command decoder. It contains the device’s status registers and coordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order. 8. Internal circuitry VDD VDD VSS VSS SA0 VDD CLK SCL VSS VDD VSS OSC VSS VDD SDA SYNC VSS VSS VDD A0, A1 A2 VSS VLCD BP0, BP1, BP2, BP3 VSS VLCD VLCD S0 to S39 VSS VSS mdb076 Fig 19. Device protection circuits PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 27 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 14. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Max Unit supply voltage −0.5 6.5 V VLCD LCD supply voltage −0.5 +7.5 V VI input voltage on each of the pins CLK, SDA, SCL, SYNC, SA0, OSC, A0 to A2 −0.5 +6.5 V VO output voltage on each of the pins S0 to S39, BP0 to BP3 −0.5 +7.5 V II input current −10 +10 mA IO output current −10 +10 mA IDD supply current −50 +50 mA IDD(LCD) LCD supply current −50 +50 mA ISS ground supply current −50 +50 mA Ptot total power dissipation - 400 mW Po output power - 100 mW VESD electrostatic discharge voltage HBM [1] - ±5000 V MM [2] - ±200 V CDM [3] - ±1000 V latch-up current [4] - 100 mA Tstg storage temperature [5] −65 +150 °C Tamb ambient temperature −40 +85 °C [1] Product data sheet Min VDD Ilu PCF8576D Conditions Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”. [2] Pass level; Machine Model (MM), according to Ref. 8 “JESD22-A115”. [3] Pass level; Charged-Device Model (CDM), according to Ref. 9 “JESD22-C101”. [4] Pass level; latch-up testing according to Ref. 10 “JESD78” at maximum ambient temperature (Tamb(max)). [5] According to the NXP store and transport requirements (see Ref. 12 “NX3-00092”) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long-term storage products, divergent conditions are described in that document. All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 28 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 10. Static characteristics Table 15. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 1.8 - 5.5 V VLCD LCD supply voltage [1] 2.5 - 6.5 V supply current [2] - 6 20 μA - 2.7 - μA - 18 30 μA - 17.5 - μA 1.0 1.3 1.6 V VSS - 0.3VDD V 0.7VDD - VDD V on pins CLK and SYNC 1 - - mA on pin SDA 3 - - mA IDD fclk(ext) = 1536 Hz VDD = 3.0 V; Tamb = 25 °C IDD(LCD) LCD supply current fclk(ext) = 1536 Hz [2] VDD(LCD) = 3.0 V; Tamb = 25 °C Logic VP(POR) power-on reset supply voltage VIL LOW-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, SCL, SDA VIH HIGH-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, SCL, SDA IOL LOW-level output current output sink current; VOL = 0.4 V; VDD = 5 V [3][4] IOH(CLK) HIGH-level output current on pin CLK output source current; VOH = 4.6 V; VDD = 5 V 1 - - mA IL leakage current VI = VDD or VSS; on pins CLK, SCL, SDA, A0 to A2 and SA0 −1 - +1 μA IL(OSC) leakage current on pin OSC VI = VDD −1 - +1 μA - - 7 pF −100 - +100 mV on pins BP0 to BP3 - 1.5 - kΩ on pins S0 to S39 - 6.0 - kΩ [5] input capacitance CI LCD outputs ΔVO output voltage variation on pins BP0 to BP3 and S0 to S39 RO output resistance VLCD = 5 V [6] [1] VLCD > 3 V for 1⁄3 bias. [2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. [3] When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 14 (see Figure 19 too). [4] Propagation delay of driver between clock (CLK) and LCD driving signals. [5] Periodically sampled, not 100 % tested. [6] Outputs measured one at a time. PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 29 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 11. Dynamic characteristics Table 16. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Clock [1] fclk(int) internal clock frequency 1440 1850 2640 Hz fclk(ext) external clock frequency 960 - 2640 Hz tclk(H) HIGH-level clock time 60 - - μs tclk(L) LOW-level clock time 60 - - μs - 30 - ns 1 - - μs - - 30 μs Synchronization tPD(SYNC_N) SYNC propagation delay tSYNC_NL tPD(drv) SYNC LOW time driver propagation delay VLCD = 5 V [2] I2C-bus[3] Pin SCL fSCL SCL clock frequency - - 400 kHz tLOW LOW period of the SCL clock 1.3 - - μs tHIGH HIGH period of the SCL clock 0.6 - - μs tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns Pin SDA Pins SCL and SDA tBUF bus free time between a STOP and START condition 1.3 - - μs tSU;STO set-up time for STOP condition 0.6 - - μs tHD;STA hold time (repeated) START condition 0.6 - - μs tSU;STA set-up time for a repeated START condition 0.6 - - μs tr rise time of both SDA and SCL signals fSCL = 400 kHz - - 0.3 μs tf fall time of both SDA and SCL signals Cb capacitive load for each bus line fSCL < 125 kHz tw(spike) spike pulse width on the I2C-bus - - 1.0 μs - - 0.3 μs - - 400 pF - - 50 ns [1] Typical output duty factor: 50 % measured at the CLK output pin. [2] Not tested in production. [3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 30 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 1 / fCLK tclk(H) tclk(L) 0.7 VDD CLK 0.3 VDD 0.7 VDD SYNC 0.3 VDD tPD(SYNC_N) tSYNC_NL 0.5 V BP0 to BP3, and S0 to S39 (VDD = 5 V) 0.5 V tPD(drv) 001aai163 Fig 20. Driver timing waveforms SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 21. I2C-bus timing waveforms PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 31 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 12. Application information 12.1 Cascaded operation In large display configurations, up to 16 PCF8576Ds can be differentiated on the same I2C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). Table 17. Addressing cascaded PCF8576D Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device 1 0 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 2 1 1 1 1 7 0 0 0 8 0 0 1 9 0 1 0 10 0 1 1 11 1 0 0 12 1 0 1 13 1 1 0 14 1 1 1 15 PCF8576Ds connected in cascade are synchronized to allow the backplane signals from only one device in the cascade to be shared. This arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other cascaded PCF8576Ds contribute additional segment outputs but their backplane outputs are left open-circuit (see Figure 22). All PCF8576Ds connected in cascade are correctly synchronized by the SYNC signal. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is lost accidentally, for example, by noise in adverse electrical environments, or if the LCD multiplex drive mode is changed in an application using several cascaded PCF8576Ds, as the drive mode cannot be changed on all of the cascaded devices simultaneously. SYNC can be either an input or an output signal; a SYNC output is implemented as an open-drain driver with an internal pull-up resistor. The PCF8576D asserts SYNC at the start of its last active backplane signal and monitors the SYNC line at all other times. If cascade synchronization is lost, it is restored by the first PCF8576D to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for each LCD drive mode is shown in Figure 23. PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 32 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates The contact resistance between the SYNC on each cascaded device must be controlled. If the resistance is too high, the device is not able to synchronize properly; this is particularly applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 18. Table 18. SYNC contact resistance Number of devices Maximum contact resistance 2 6 kΩ 3 to 5 2.2 kΩ 6 to 10 1.2 kΩ 10 to 16 700 Ω The PCF8576D can be cascaded with the PCF8562, the PCF8533 or the PCF8534A. This allows optimal drive selection for a given number of pixels to display. Figure 20 and Figure 21 show the timing of the synchronization signals. VDD VLCD 6 SDA 1, 58, 59 SCL 2, 3 SYNC 4 13 40 segment drives LCD PANEL PCF8576DU CLK 5 OSC 7 8 9 10 11 12 A0 A1 A2 SA0 VSS (up to 2560 elements) BP0 to BP3 (open-circuit) VLCD VDD R≤ HOST MICROPROCESSOR/ MICROCONTROLLER tr 2CB V DD LCD 6 13 SDA 1, 58, 59 SCL 2, 3 SYNC 4 PCF8576DU CLK 5 OSC 7 8 VSS V A0 9 A1 10 A2 11 40 segment drives 4 backplanes BP0 to BP3 mdb077 12 SA0 VSS Fig 22. Cascaded PCF8576D configuration PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 33 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates Tfr = 1 ffr BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. BP0 (1/3 bias) SYNC (d) 1:4 multiplex drive mode. mgl755 Fig 23. Synchronization of the cascade for the various PCF8576D drive modes 13. Test information The following quality information corresponds with the following product type: PCF8576DT/S400/2 13.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 34 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 14. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 28 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 24. Package outline SOT364-1 (TSSOP56) PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 35 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 15. Bare die outline Wire bond die; 59 bonding pads PCF8576DU/DA D A 35 (1) 22 21 e 36 x 0 E 0 y X 51 9 C2 52 59 1 8 C1 P4 P3 P2 P1 detail X 0 0.5 1 mm scale Notes 1. Marking code: PC8576D-2 Outline version pcf8576du_da_do References IEC JEDEC JEITA European projection Issue date 08-12-10 10-12-20 PCF8576DU/DA Fig 25. Bare die outline PCF8576DU/DA/2 (for dimensions see Table 19) PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 36 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates Bare die; 59 bumps PCF8576DU/2DA D 35 (1) 22 21 Y e 36 x 0 E 0 y 51 9 C2 52 59 1 8 C1 X L A b detail X A2 A1 detail Y 0 0.5 1 mm scale Notes 1. Marking code: PC8576D-2 Outline version pcf8576du_2da_do References IEC JEDEC JEITA European projection Issue date 08-12-10 10-12-20 PCF8576DU/2DA Fig 26. Bare die outline PCF8576DU/2DA/2 (for dimensions see Table 20) PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 37 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates Table 19. Dimensions of PCF8576DU/DA/2 Original dimensions are in mm. P1[2] P2[3] P3[2] - - - - - - 0.09 0.08 0.066 0.056 - - - - e[1] Unit (mm) A D E max - - - nom 0.38 2.2 2.0 min - - - 0.072 [1] Dimension not drawn to scale. [2] Pad size. [3] Passivation opening. P4[3] Table 20. Dimensions of PCF8576DU/2DA/2 Original dimensions are in mm. Unit (mm) A A1 A2 b D E e[1] L max - - - - - - - - nom 0.40 0.015 0.381 0.052 2.2 2.0 - 0.077 min - - - - - - 0.072 - [1] Dimension not drawn to scale. Table 21. Bonding pad location for PCF8576DU/x All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 3, Figure 25 and Figure 26). PCF8576D Product data sheet Symbol Pad X (μm) Y (μm) Description SDA 1 −34.38 −876.6 I2C-bus serial data input/output SCL 2 109.53 −876.6 I2C-bus serial clock input SCL 3 181.53 −876.6 SYNC 4 365.58 −876.6 cascade synchronization input/output CLK 5 469.08 −876.6 external clock input/output VDD 6 577.08 −876.6 supply voltage OSC 7 740.88 −876.6 internal oscillator enable input subaddress inputs A0 8 835.83 −876.6 A1 9 1005.48 −630.9 A2 10 1005.48 −513.9 SA0 11 1005.48 −396.9 I2C-bus address input; bit 0 VSS 12 1005.48 −221.4 ground supply voltage VLCD 13 1005.48 10.71 LCD supply voltage BP0 14 1005.48 156.51 LCD backplane outputs BP2 15 1005.48 232.74 BP1 16 1005.48 308.97 BP3 17 1005.48 385.2 S0 18 1005.48 493.2 S1 19 1005.48 565.2 S2 20 1005.48 637.2 S3 21 1005.48 709.2 LCD segment outputs All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 38 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates Table 21. Bonding pad location for PCF8576DU/x …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 3, Figure 25 and Figure 26). PCF8576D Product data sheet Symbol Pad X (μm) Y (μm) Description S4 22 347.22 876.6 LCD segment outputs S5 23 263.97 876.6 S6 24 180.72 876.6 S7 25 97.47 876.6 S8 26 14.22 876.6 S9 27 −69.03 876.6 S10 28 −152.28 876.6 S11 29 −235.53 876.6 S12 30 −318.78 876.6 S13 31 −402.03 876.6 S14 32 −485.28 876.6 S15 33 −568.53 876.6 S16 34 −651.78 876.6 S17 35 −735.03 876.6 S18 36 −1005.5 625.59 S19 37 −1005.5 541.62 S20 38 −1005.5 458.19 S21 39 −1005.5 374.76 S22 40 −1005.5 291.33 S23 41 −1005.5 207.9 S24 42 −1005.5 124.47 S25 43 −1005.5 41.04 S26 44 −1005.5 −42.39 S27 45 −1005.5 −125.8 S28 46 −1005.5 −209.3 S29 47 −1005.5 −292.7 S30 48 −1005.5 −376.1 S31 49 −1005.5 −459.5 S32 50 −1005.5 −543 S33 51 −1005.5 −625.6 S34 52 −735.03 −876.6 S35 53 −663.03 −876.6 S36 54 −591.03 −876.6 S37 55 −519.03 −876.6 S38 56 −447.03 −876.6 All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 39 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates Table 21. Bonding pad location for PCF8576DU/x …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 3, Figure 25 and Figure 26). Symbol Pad X (μm) Y (μm) Description S39 57 −375.03 −876.6 LCD segment outputs SDA 58 −196.38 −876.6 I2C-bus serial data input/output SDA 59 −106.38 −876.6 Table 22. Alignment marks All x/y coordinates represent the position of the center of each alignment mark with respect to the center (x/y = 0) of the chip (see Figure 3, Figure 25 and Figure 26). Symbol X (μm) Y (μm) C1 930.42 −870.3 C2 −829.98 −870.3 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 17. Packing information 17.1 Tray information x G A C H y 1,1 2,1 x,1 D 1,2 B F x,y 1,y E mce404 Fig 27. Tray details PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 40 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates Table 23. Tray dimensions (see Figure 27) Symbol Description Value Unit A pocket pitch in x direction 5.59 mm B pocket pitch in y direction 6.35 mm C pocket width in x direction 3.16 mm D pocket width in y direction 3.16 mm E tray width in x direction 50.8 mm F tray width in y direction 50.8 mm G cut corner to pocket 1.1 center 5.83 mm H cut corner to pocket 1.1 center 6.35 mm x number of pockets, x direction 8 - y number of pockets, y direction 7 - PC8576D mdb080 Fig 28. Tray alignment PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 41 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 17.2 Carrier tape information 4 A0 K0 pin 1 index W B0 P1 direction of feed 001aaj314 Fig 29. Tape details Table 24. Carrier tape dimensions Symbol Description Value Unit A0 pocket width in x direction 8.6 mm B0 pocket width in y direction 14.5 mm K0 pocket height 1.8 mm P1 sprocket hole pitch 12 mm W tape width in y direction 24 mm 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 42 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 18.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 30) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 25 and 26 PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 43 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates Table 25. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 26. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 30. temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 44 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 19. Abbreviations Table 27. PCF8576D Product data sheet Abbreviations Acronym Description CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor HBM Human Body Model ITO Indium Tin Oxide LCD Liquid Crystal Display LSB Least Significant Bit MM Machine Model MSB Most Significant Bit MSL Moisture Sensitivity Level PCB Printed Circuit Board RAM Random Access Memory RMS Root Mean Square SCL Serial CLock line SDA Serial DAta line SMD Surface Mount Device All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 45 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 20. References [1] AN10170 — Design guidelines for COG modules with NXP monochrome LCD drivers [2] AN10365 — Surface mount reflow soldering description [3] AN10706 — Handling bare die [4] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [6] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [8] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) [9] JESD22-C101 — Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components [10] JESD78 — IC Latch-Up Test [11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [12] NX3-00092 — NXP store and transport requirements [13] UM10204 — I2C-bus specification and user manual PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 46 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 21. Revision history Table 28. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8576D v.10 20110214 Product data sheet - PCF8576D_9 Modifications: • • • • Adjusted die size Removed product type PCF8576DH/2 Adjusted values of IDD and IDD(LCD) in Table 15 Deleted power-on remark in Section 7.5.1 PCF8576D_9 20090825 Product data sheet - PCF8576D_8 PCF8576D_8 20090319 Product data sheet - PCF8576D_7 PCF8576D_7 20081218 Product data sheet - PCF8576D_6 PCF8576D_6 20081202 Product data sheet - PCF8576D_5 PCF8576D_5 20041222 Product specification - PCF8576D_4 PCF8576D_4 20041008 Product specification - PCF8576D_3 PCF8576D_3 20040617 Product specification - PCF8576D_2 PCF8576D_2 20030623 Product specification - PCF8576D_1 PCF8576D_1 20030401 Objective specification - - PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 47 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 22. Legal information 22.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 22.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 22.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be PCF8576D Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 48 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. 22.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or 23. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCF8576D Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 10 — 14 February 2011 © NXP B.V. 2011. All rights reserved. 49 of 50 PCF8576D NXP Semiconductors Universal LCD driver for low multiplex rates 24. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 8 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 8 7.3.1 Electro-optical performance . . . . . . . . . . . . . . . 9 7.4 LCD drive mode waveforms . . . . . . . . . . . . . . 11 7.4.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 11 7.4.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 12 7.4.3 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 14 7.4.4 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 15 7.5 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5.1 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.7 Display register . . . . . . . . . . . . . . . . . . . . . . . . 16 7.8 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 16 7.9 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 16 7.10 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.11 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.12 Subaddress counter . . . . . . . . . . . . . . . . . . . . 19 7.13 Output bank selector . . . . . . . . . . . . . . . . . . . 20 7.14 Input bank selector . . . . . . . . . . . . . . . . . . . . . 20 7.15 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16 Characteristics of the I2C-bus. . . . . . . . . . . . . 21 7.16.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16.2 START and STOP conditions . . . . . . . . . . . . . 22 7.16.3 System configuration . . . . . . . . . . . . . . . . . . . 22 7.16.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16.5 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 23 7.16.6 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.16.7 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23 7.17 Command decoder . . . . . . . . . . . . . . . . . . . . . 25 7.18 Display controller . . . . . . . . . . . . . . . . . . . . . . 27 8 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 27 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 29 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 30 12 Application information. . . . . . . . . . . . . . . . . . 32 12.1 13 13.1 14 15 16 17 17.1 17.2 18 18.1 18.2 18.3 18.4 19 20 21 22 22.1 22.2 22.3 22.4 23 24 Cascaded operation. . . . . . . . . . . . . . . . . . . . Test information . . . . . . . . . . . . . . . . . . . . . . . Quality information . . . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Tray information . . . . . . . . . . . . . . . . . . . . . . . Carrier tape information . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 34 34 35 36 40 40 40 42 42 42 42 43 43 45 46 47 48 48 48 48 49 49 50 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 14 February 2011 Document identifier: PCF8576D