PRELIMINARY PDM31564 PDM31564 256K x 16 CMOS 3.3V Static RAM Features n n n n n n n n n Description High-speed access times - Com’l: 8, 10, 12, 15, and 20 ns - Ind: 12, 15, and 20 ns Low power operation (typical) - PDM31564SA Active: 300 mW Standby: 25mW High-density 256K x 16 architecture 3.3V (±0.3V) power supply Fully static operation TTL-compatible inputs and outputs Output buffer controls: OE Data byte controls: LB, UB Packages: Plastic SOJ (400 mil) - SO Plastic TSOP (II) - T The PDM31564 is a high-performance CMOS static RAM organized as 262,144 x 16 bits. The PDM31564 features low power dissipation using chip enable (CE) and has an output enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls. The PDM31564 operates from a single 3.3V power supply and all inputs and outputs are fully TTLcompatible. The PDM31564 is available in a 44-pin 400-mil plastic SOJ and a plastic TSOP package for high-density surface assembly and is suitable for use in highspeed applications requiring high-speed storage. 1 2 3 4 5 6 7 A8 - A0 A7-A0 Row Decoder Row Address Buffer Functional Block Diagram Data Input/ Output Buffer I/O15-I/O0 Memory Cell Array 256 512xx128 256 xx 32 8 Vcc Vss 9 10 Sense Amp Column Decoder WE OE UB LB CE 11 Control Logic Clock Generator Column Address Buffer 12 A17 - A9 A15-A8 Rev. 1.2 - 3/31/98 1 PDM31564 PRELIMINARY Pin Configuration SOJ TSOP (II) A4 A3 A2 A1 A0 44 1 43 2 42 3 A5 A4 1 44 A5 A6 A3 2 43 A6 A7 A2 3 42 A7 4 41 OE 4 41 OE A1 5 40 UB A0 5 40 UB LB CE 6 39 LB 6 39 I/O0 7 38 I/O15 I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O2 9 36 I/O13 I/O3 10 35 I/O12 I/O3 10 35 I/O12 Vss Vcc 11 34 Vss Vcc Vss 12 33 Vcc I/O11 I/O4 32 I/O11 I/O10 I/O5 13 14 31 I/O10 15 30 I/O9 CE Vcc Vss I/O4 I/O5 I/O6 I/O7 34 11 33 12 32 13 14 31 15 30 I/O9 I/O6 16 29 I/O8 I/O7 16 29 I/O8 WE 28 NC 27 A8 28 A17 17 18 NC 27 A8 A17 17 18 A16 19 26 A9 A16 19 26 A9 A15 20 21 22 25 A10 A15 25 A10 24 A11 A14 24 A11 A12 A13 20 21 22 23 A12 WE A14 A13 23 Pin Description Name Description A17-A0 Address Inputs I/O15-I/O0 Data Inputs CE Chip Enable Input WE Write Enable Input OE Output Enable Input LB, UB Data Byte Control Inputs NC No Connect Vss Ground VCC Power (+3.3V) Capacitance (TA = +25°C, f = 1.0 MHz) Symbol Parameter Conditions Max. Unit CIN Input Capacitance VIN = VSS 6 pF CI/O Output Capacitance VI/O = VSS 8 pF NOTE: This parameter is determined by device characterization, but is not production tested. 2 Rev. 1.2 - 3/31/98 PDM31564 PRELIMINARY Operating Mode Mode CE OE WE LB UB I/O7-I/O0 I/O15-I/O8 Power Read L L H L L Output Output ICC H L High Impedance Output ICC L H Output High Impedance ICC L L Input Input ICC H L High Impedance Input ICC L H Input High Impedance ICC Write L Output Disable Standby X L L H H X x High Impedance High Impedance ICC L X X H H High Impedance High Impedance ICC H X X X X High Impedance High Impedance ISB 1 2 3 4 NOTE: H = VIH, L = VIL, X = DON’T CARE Absolute Maximum Ratings (1) Symbol Rating Com’l. Ind. Unit VTERM Terminal Voltage with Respect to VSS –0.5 to +4.6 –0.5 to +4.6 V TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C PT Power Dissipation 1.5 1.5 W IOUT DC Output Current 50 50 mA 125 145 °C Tj Maximum Junction Temperature (2) 5 6 7 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Appropriate thermal calculations should be performed in all cases and specifically for those where the chosen package has a large thermal resistance (e.g., TSOP). The calculation should be of the form: Tj = Ta + P * θja where Ta is the ambient temperature, P is average operating power and θja the thermal resistance of the package. For this product, use the following θja values: 8 9 SOJ: 59o C/W TSOP: 87o C/W 10 Recommended DC Operating Conditions Symbol Description VCC VSS Industrial Commercial Rev. 1.2 - 3/31/98 Min. Typ. Max. Unit Supply Voltage 3.0 3.3 3.6 V Supply Voltage 0 0 0 V Ambient Temperature –40 25 85 °C Ambient Temperature 0 25 70 °C 11 12 3 PDM31564 PRELIMINARY DC Electrical Characteristics (VCC = 3.3V ± 0.3V) Symbol Parameter Test Conditions Min. Max. Unit ILI Input Leakage Current VCC = Max., VIN = Vss to VCC Com’l/ Ind. –5 5 µA ILO Output Leakage Current VCC= Max., CE = VIH, VOUT = Vss to VCC Com’l/ Ind. –5 5 µA VIL Input Low Voltage –0.3(1) 0.8 V VIH Input High Voltage 2.2 Vcc + 0.3 V VOL Output Low Voltage IOL = 8 mA, VCC = Min. — 0.4 V VOH Output High Voltage IOH = –4 mA, VCC = Min. 2.4 — V NOTE: 1. VIL(min) = –3.0V for pulse width less than 20 ns. Power Supply Characteristics -8 Symbol Parameter ICC Operating Current CE = VIL -10 -12 Com’l Com’l Com’l 220 210 200 -15 -20 Ind. 210 Com’l 190 Ind. 200 Com’l Ind. 185 195 Unit mA f = fMAX = 1/tRC VCC = Max. IOUT = 0 mA ISB Standby Current CE = VIH 50 45 40 45 35 40 30 35 mA 10 10 10 15 10 15 10 15 mA f = fMAX = 1/tRC VCC = Max. ISB1 Full Standby Current CE ≥ VCC – 0.2V f=0 VCC = Max., VIN ≥ VCC – 0.2V or ≤ 0.2V NOTES: All values are maximum guaranteed values. 4 Rev. 1.2 - 3/31/98 PDM31564 PRELIMINARY AC Test Conditions Input pulse levels 1 VSS to 3.0V Input rise and fall times 2.5 NS Input timing reference levels 1.5V Output reference levels 1.5V Output load 2 See Figures 1 and 2 3 4 5 +3.3V +3.3V 317Ω 317Ω DOUT DOUT 351Ω 30 pF Figure 1. Output Load 351Ω 6 5 pF 7 Figure 2. Output Load Equivalent (for tLZCE, tHZCE, tLZWE, tHZWE, tLZBE, tHZBE, tLZOE, tHZOE) 8 9 10 11 12 Rev. 1.2 - 3/31/98 5 PDM31564 PRELIMINARY Read Timing Diagram tRC ADDRESSES tAA tOH tACE CE tAOE tHZCE(1) OE tBA tHZOE(1) UB, LB tLZBE(1) tHZBE(1) tLZOE(1) tLZCE(1) DOUT Output Data Valid AC Electrical Characteristics Description -8* READ Cycle -10* –12 –15 –20 Symbol Min Max Min Max Min Max Min Max Min Max Unit READ cycle time tRC 8 – 10 – 12 — 15 — 20 — ns Address access time tAA – 8 – 10 — 12 — 15 — 20 ns Chip enable access time tACE – 8 – 10 — 12 — 15 — 20 ns Byte access time tBA – 5 – 6 — 7 — 8 — 9 ns Output hold from address change tOH 4 – 4 – 4 — 4 — 4 — ns Byte disable to output in low-Z(1) tLZBE 0 – 0 – 0 — 0 — 0 — ns Byte enable to output in high-Z(1) tHZBE – 4 – 5 — 8 — 9 — 9 ns low-Z(1) tLZCE 3 – 3 – 4 — 4 — 5 — ns high-Z(1, 2) tHZCE – 4 – 5 — 6 — 7 — 8 ns Chip enable to output in Chip disable to output Output enable access time tAOE – 4 – 5 — 6 — 7 — 10 ns Output enable to output in low-Z(1) tLZOE 0 – 0 – 0 — 0 — 0 — ns Output disable to output in high-Z(1, 2) tHZOE – 4 – 5 — 5 — 6 — 6 ns * VCC = 3.3V +5% 6 Rev. 1.2 - 3/31/98 PDM31564 PRELIMINARY Write Cycle 1 Timing Diagram (WE Controlled) 1 tWC ADDRESSES tAW tAS tWP 2 tAH WE tCW 3 CE tBW 4 UB, LB tHZWE(1) tLZWE(1) High Impedance (3) DOUT (4) tDS DIN 5 tDH Data Stable 6 Write Cycle 2 Timing Diagram (CE Controlled) 7 tWC ADDRESSES tAW tAS tWP 8 tAH WE tCW 9 CE tBW UB, LB tLZBE(1) 10 tHZWE(1) tLZCE(1) High Impedance DOUT tDS DIN 11 tDH Data Stable 12 Rev. 1.2 - 3/31/98 7 PDM31564 PRELIMINARY Write Cycle 3 Timing Diagram (UB, LB Controlled) tWC ADDRESSES tAW tAS tWP tAH WE tCW CE tBW UB, LB tLZCE(1) tHZWE(1) tLZBE(1) High Impedance DOUT tDS DIN tDH Data Stable AC Electrical Characteristics Description -8* -10* -12 -15 -20 WRITE Cycle Sym WRITE cycle time tWC 8 — 10 — 12 — 15 — 20 — ns Chip enable to end of write tCW 7 — 8 — 10 — 11 — 13 — ns Address valid to end of write tAW 7 — 8 — 10 — 11 — 13 — ns Byte pulse width tBW 7 — 8 — 10 — 12 — 13 — ns Address setup time tAS 0 — 0 — 0 — 0 — 0 — ns Address hold from end of write tAH 0 — 0 — 0 — 0 — 0 — ns Write pulse width tWP 7 — 8 — 8 — 9 — 10 — ns Data setup time tDS 5 — 6 — 7 — 8 — 9 — ns ns Data hold time Min. Max Min. Max Min. Max. Min. Max. Min. Max. Unit tDH 0 — 0 — 0 — 0 — 0 — Byte disable to output in low Z(1, 3, 4) tLZBE 0 — 0 — 0 — 0 — 0 — ns Byte enable to output in high Z(1, 3, 4) tHZBE — 6 — 6 — 7 — 8 — 9 ns Output disable to output in low Z(1, 3, 4) tLZOE 0 — 0 — 0 — 0 — 0 — ns Output enable to output in high Z(1, 3, 4) tHZOE — 6 — 6 — 7 — 7 — 8 ns Write disable to output in low Z(1,3, 4) tLZWE 0 — 0 — 0 — 0 — 0 — ns Write enable to output in high Z(1, 3, 4) tHZWE — 6 6 — — 7 — 7 — 9 ns * VCC = 3.3v +5% 8 Rev. 1.2 - 3/31/98 PDM31564 PRELIMINARY NOTES: 1. Parameter is determined by device characterization and is not production tested. See Figure 2 for load conditions. 2. If the CE LOW transition occurs coincident with or after the WE LOW transition, outputs remain in a high impedance state. 3. If the CE HIGH transition occurs coincident with or after the WE HIGH transition, outputs remain in a high impedance state. 4. If OE is HIGH during a write cycle, the outputs are in a high-impedance state during this period. 1 2 3 4 5 Ordering Information XXXXX X Device Type Power XX X Speed Package Type X X Process Temp. Range Preferred Shipping Container 6 Blank Tubes TR Tape & Reel TY Tray 7 Blank Commercial (0° to +70°C) I Industrial (–40°C to +85°C) A Automotive ( –40°C to +105°C) SO T 44-pin 400-mil Plastic SOJ 44-pin Plastic TSOP (II) 8 10 12 15 20 Commercial Only Commercial Only SA Standard Power 8 9 10 PDM31564 - (256Kx16) Static RAM 11 12 Faster Memories for a FasterWorld ™ Rev. 1.2 - 3/31/98 9