ADVANCE INFORMATION PE9704 3.0 GHz Integer-N PLL for Rad Hard Applications Product Description Peregrine’s PE9704 is a high-performance integer-N PLL capable of frequency synthesis up to 3.0 GHz. The device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with existing commercial space PLLs. Features • 3.0 GHz operation • ÷10/11 dual modulus prescaler • Phase detector output • Serial interface or hardwired programmable • Ultra-low phase noise • SEU < 10-9 errors / bit-day • 100 Krad (Si) total dose • 44-lead CQFJ The PE9704 features a ÷10/11 dual modulus prescaler, counters, and a phase comparator as shown in Figure 1. Counter values are programmable through a serial interface, and can also be directly hard wired. The PE9704 is optimized for commercial space applications. Single Event Latch-up (SEL) is physically impossible and Single Event Upset (SEU) is better than 10-9 errors per bit / day. Fabricated in Peregrine’s patented UTSi® (Ultra Thin Silicon) CMOS technology, the PE9704 offers excellent RF performance and intrinsic radiation tolerance. Figure 1. Block Diagram Prescaler 10 / 11 FIN Main Counter 13 MSEL Serial Control 3 20-Bit Frequency Register M(8:0) Direct A(3:0) Control R(5:0) fp 20 fc Phase Detector PD_U PD_D 19* LD 6 FR 6 C ext R Counter * prescaler bypass not available in Direct mode PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 1 of 12 PE9704 Advance Information VDD 2 1 GND R0 3 GND R1 4 FR R2 5 ENH R3 6 LD GND Figure 2. Pin Configuration 44 43 42 41 40 R4 7 39 CEXT R5 8 38 VDD M0 9 37 PD_U M1 10 36 PD_D VDD 11 35 GND VDD 12 34 N/C M2 13 33 VDD M3 14 32 DOUT S_WR, M4 15 31 VDD DATA, M5 16 30 N/C GND 17 29 GND GND FIN A3 A2 E_WR, A1 VDD DMODE A0 M8 M7 CLOCK, M6 18 19 20 21 22 23 24 25 26 27 28 Table 1. Pin Descriptions Pin No. Pin Name Interface Mode Type Description 1 VDD Both (Note 1) Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended. 2 R0 Direct Input R Counter bit0 3 R1 Direct Input R Counter bit1 4 R2 Direct Input R Counter bit2 5 R3 Direct Input R Counter bit3 6 GND Both (Note 1) Ground 7 R4 Direct Input R Counter bit4 8 R5 Direct Input R Counter bit5 (MSB) 9 M0 Direct Input M Counter bit0 10 M1 Direct Input M Counter bit1 11 VDD Both (Note 1) Same as pin 1 12 VDD Both (Note 1) Same as pin 1 13 M2 Direct Input M Counter bit2 14 M3 Direct Input M Counter bit3 S_WR Serial Input Frequency register load enable input. Buffered data is transferred to the frequency register on S_WR rising edge. M4 Direct Input M Counter bit4 DATA Serial Input Binary serial data input. Data is entered LSB first, and is clocked serially into the 20bit frequency control register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of CLOCK. 15 16 Copyright Peregrine Semiconductor Corp. 2003 Page 2 of 12 File No. 70/0083~00B | | UTSi CMOS RFIC SOLUTIONS PE9704 Advance Information Pin No. Pin Name Interface Mode Type Description M5 Direct GND Both CLOCK Serial Input Clock input. Data is clocked serially into either the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of CLOCK. M6 Direct Input M Counter bit6 19 M7 Direct Input M Counter bit7 20 M8 Direct Input M Counter bit8 (MSB) 21 A0 Direct Input A Counter bit0 22 DMODE Both Input Selects direct interface mode (DMODE=1) or serial interface mode (DMODE=0) 23 VDD Both (Note 1) Same as pin 1 E_WR Serial Input Enhancement register write enable. While E_WR is “high”, DATA can be serially clocked into the enhancement register on the rising edge of CLOCK. A1 Direct Input A Counter bit1. 25 A2 Direct Input A Counter bit2 26 A3 Direct Input A Counter bit3 (MSB) 27 FIN Both Input RF prescaler input from the VCO. 3.0 GHz maximum frequency. 28 GND Both Ground. 29 GND Both Ground. 30 N/C 31 VDD Both (Note 1) Same as pin 1 32 DOUT Serial Output Data Out. The Main Counter output, R Counter output, or dual modulus prescaler select (MSEL) can be routed to DOUT through enhancement register programming. 33 VDD Both (Note 1) Same as pin 1 34 N/C 35 GND Both 36 PD_D Both 37 PD_U Both 38 VDD Both (Note 1) Same as pin 1 39 CEXT Both Output Logical “NAND” of PD_U and PD_D, passed through an on-chip, 2 kΩ series resistor. Connecting CEXT to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. 40 GND Both Ground 41 GND Both Ground 42 FR Both Input Reference frequency input 43 ENH Both Output, OD Enhancement mode. When asserted low (“0”), enhancement register bits are functional. 44 LD Serial Output Lock detect output, the open-drain logical inversion of CEXT. When the loop is locked, LD is high impedance; otherwise LD is a logic low (“0”). 17 18 24 Input M Counter bit5 Ground No connect. No connect. Ground. Output PD_D pulses down when fp leads fc. PD_U pulses down when fc leads fp. Note 1: VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level. Note 2: All digital input pins have 70 kΩ pull-down resistors to ground. PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 3 of 12 PE9704 Advance Information Table 2. Absolute Maximum Ratings Symbol VDD Parameter/Conditions Min Electrostatic Discharge (ESD) Precautions Max Units Supply voltage -0.3 4.0 V Voltage on any input -0.3 VDD + 0.3 V II DC into any input -10 +10 mA IO DC into any output -10 +10 mA Storage temperature range -65 150 °C VI Tstg Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up. Table 3. Operating Ratings Symbol When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 4. Parameter/Conditions Min Max Units VDD Supply voltage 2.85 3.15 V TA Operating ambient temperature range -40 85 °C Table 4. ESD Ratings Symbol VESD Note 1: Parameter/Conditions ESD voltage (Human Body Model) – Note 1 Level Units 1000 V Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2 Copyright Peregrine Semiconductor Corp. 2003 Page 4 of 12 File No. 70/0083~00B | | UTSi CMOS RFIC SOLUTIONS PE9704 Advance Information Table 5. DC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol IDD Parameter Operational supply current; Prescaler disabled Prescaler enabled Conditions Min Typ Max Units 10 24 31 mA mA VDD = 2.85 to 3.15 V Digital Inputs: All except FR, FIN (all digital inputs have 70k ohm pull-up resistors) VIH High level input voltage VDD = 2.85 to 3.15 V VIL Low level input voltage VDD = 2.85 to 3.15 V IIH High level input current VIH = VDD = 3.15 V IIL Low level input current VIL = 0, VDD = 3.15 V 0.7 x VDD V 0.3 x VDD V +70 µA µA -1 Reference Divider input: FR IIHR High level input current VIH = VDD = 3.15 V IILR Low level input current VIL = 0, VDD = 3.15 V +100 µA µA -100 Counter and phase detector outputs: fc, fp. VOLD Output voltage LOW Iout = 6 mA VOHD Output voltage HIGH Iout = -3 mA 0.4 VDD - 0.4 V V Lock detect outputs: CEXT, LD VOLC Output voltage LOW, CEXT Iout = 100 µ VOHC Output voltage HIGH, CEXT Iout = -100 µ VOLLD Output voltage LOW, LD Iout = 6 mA PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com 0.4 VDD - 0.4 V V 0.4 V Copyright Peregrine Semiconductor Corp. 2003 Page 5 of 12 PE9704 Advance Information Table 6. AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Conditions Min Max Units 10 MHz Control Interface and Latches (see Figures 1and 3) fClk CLOCK Serial data clock frequency (Note 1) tClkH CLOCK Serial clock HIGH time 30 ns tClkL CLOCK Serial clock LOW time 30 ns tDSU DATA set-up time after CLOCK rising edge 10 ns tDHLD DATA hold time after CLOCK rising edge 10 ns S_WR pulse width 30 ns tPW tCWR tCE tWRC CLOCK rising edge to S_WR rising edge. 30 ns CLOCK falling edge to E_WR transition 30 ns S_WR falling edge to CLOCK rising edge. 30 ns tEC E_WR transition to CLOCK rising edge 30 ns tMDO MSEL data out delay after FIN rising edge CL = 12 pf 8 ns 500 3000 MHz -5 5 dBm 50 300 MHz -5 5 dBm Main Divider (Including Prescaler) FIN Operating frequency PFin Input level range External AC coupling Main Divider (Prescaler Bypassed) FIN Operating frequency PFin Input level range External AC coupling FR Operating frequency (Note 3) PFr Reference input power (Note 2) Single-ended input Comparison frequency (Note 3) Reference Divider 100 -2 MHz dBm Phase Detector fc Note 1: 20 MHz Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk specification. Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p. Note 3: Parameter is guaranteed through characterization only and is not tested. Copyright Peregrine Semiconductor Corp. 2003 Page 6 of 12 File No. 70/0083~00B | | UTSi CMOS RFIC SOLUTIONS PE9704 Advance Information Functional Description The PE9704 consists of a prescaler, counters, a phase detector, and control logic. The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the value of the modulus select. Counters “R” and “M” divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. An additional counter (“A”) is used in the modulus select logic. The phase-frequency detector generates up and down frequency control signals. The control logic includes a selectable chip interface. Data can be written via a serial bus or hardwired directly to the pins. There are also various operational and test modes and a lock detect output. Prescaler Bypass Mode Setting the frequency control register bit PB “high” allows FIN to bypass the ÷10/11 prescaler. In this mode, the prescaler and A counter are powered down, and the input VCO frequency is divided by the M counter directly. This mode is only available when using the serial port to set the frequency control bits. The following equation relates FIN to the reference frequency FR: FIN = (M + 1) x (FR / (R+1)) ) where 1 ≤ M ≤ 511 (3) Reference Counter The reference counter chain divides the reference frequency FR down to the phase detector comparison frequency fc. Main Counter Chain Normal Operating Mode Setting the PB control bit “low” enables the ÷10/11 prescaler. The main counter chain then divides the RF input frequency (FIN) by an integer derived from the values in the “M” and “A” counters. In this mode, the output from the main counter chain (fp) is related to the VCO frequency (FIN) by the following equation: fp = FIN / [10 x (M + 1) + A] where A ≤ M + 1, 1 ≤ M ≤ 511 (1) The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation: fc = FR / (R + 1) where 0 ≤ R ≤ 63 (4) Note that programming R with “0” will pass the reference frequency (FR) directly to the phase detector. When the loop is locked, FIN is related to the reference frequency (FR) by the following equation: FIN = [10 x (M + 1) + A] x (FR / (R+1)) where A ≤ M + 1, 1 ≤ M ≤ 511 (2) A consequence of the upper limit on A is that FIN must be greater than or equal to 90 x (FR / (R+1)) to obtain contiguous channels. The A counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in M. Programming the M counter with the minimum allowed value of “1” will result in a minimum M counter divide ratio of “2”. PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 7 of 12 PE9704 Advance Information Register Programming contents from this buffer register are transferred into the enhancement register on the falling edge of E_WR according to the timing diagram shown in Figure 3. After the falling edge of E_WR, the data provides control bits as shown in Table 8. These bits are active when the Enh input is “low”. Serial Interface Mode Serial Interface Mode is selected by setting the DMODE input “low”. While the E_WR input is “low”, serial data (DATA input), B0 to B19, is clocked into a buffer register on the rising edge of CLOCK, LSB (B0) first. The contents from this buffer register are transferred into the frequency control register on the rising edge of S_WR according to the timing diagram shown in Figure 3. This data controls the counters as shown in Table 7. Direct Interface Mode Direct Interface Mode is selected by setting the DMODE input “high”. In this mode, the counter values are set directly at external pins as shown in Table 7 and Figure 2. All frequency control register bits are addressable except PB (it is not possible to bypass the ÷10/11 dual modulus prescaler in Direct Mode). While the E_WR input is “high”, serial data (DATA input), B0 to B7, is clocked into a buffer register on the rising edge of CLOCK, LSB (B0) first. The Table 7. Frequency Register Programming Interface Mode Enh DMODE R5 R4 M8 M7 PB M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0 Serial* 1 0 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 Direct 1 1 R5 R4 M8 M7 0 M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0 * Data is clocked serially on CLOCK rising edge while E_WR is “low” and transferred to frequency register on S_WR rising edge. LSB (first in) MSB (last in) Table 8. Enhancement Register Programming Interface Mode Enh DMODE Reserved* Reserved* fp output Power down Counter load MSEL output fc output Reserved* Serial** 0 X B0 B1 B2 B3 B4 B5 B6 B7 * Program to 0 * Data is clocked serially on CLOCK rising edge while E_WR is “low” and transferred to frequency register on S_WR rising edge. LSB (first in) Copyright Peregrine Semiconductor Corp. 2003 Page 8 of 12 MSB (last in) File No. 70/0083~00B | | UTSi CMOS RFIC SOLUTIONS PE9704 Advance Information Figure 3. Serial Interface Mode Timing Diagram DATA E_WR tEC tCE CLOCK S_WR tDSU tDHLD tClkH tClkL tCWR tPW tWRC Enhancement Register The functions of the enhancement register bits are shown below. All bits are active high. Operation is undefined if more than one output is sent to DOUT. Table 9. Enhancement Register Bit Functionality Bit Function Bit 0 Reserved** Bit 1 Reserved** Bit 2 fp output Bit 3 Power down Description Drives the M counter output onto the DOUT output. Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the DOUT output. Bit 6 fc output Bit 7 Reserved** Drives the R counter output onto the DOUT output ** Program to 0 PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Copyright Peregrine Semiconductor Corp. 2003 Page 9 of 12 PE9704 Advance Information Phase Detector Outputs Lock Detect Output The phase detector is triggered by rising edges from the main counter (fp) and the reference counter (fc). It has two outputs, PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses “low”. If the divided reference leads the divided VCO in phase or frequency (fc leads fp), PD_U pulses “low”. The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The phase detector gain is 430 mV / radian. A lock detect signal is provided at pin LD, via the pin CEXT (see Figure 1). CEXT is the logical “NAND” of PD_U and PD_D waveforms, driven through a series 2k ohm resistor. Connecting CEXT to an external shunt capacitor provides integration of this signal. PD_U and PD_D are designed to drive an active loop filter which controls the VCO tune voltage. PD_U pulses result in an increase in VCO frequency and PD_D results in a decrease in VCO frequency. The CEXT signal is then sent to the LD pin through an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. Software tools for designing the active loop filter can be found at Peregrine’s web site (www.peregrine-semi.com). Copyright Peregrine Semiconductor Corp. 2003 Page 10 of 12 File No. 70/0083~00B | | UTSi CMOS RFIC SOLUTIONS PE9704 Advance Information Figure 4. Package Drawing 44-lead CQFJ All dimensions are in mils Table 10. Ordering Information Order Code 9704-01 Part Marking PE9704 ES Description Package Engineering Samples 44-pin CQFJ 44-pin CQFJ 9704-11 PE9704 Flight Units 9704-00 PE9704 EK Evaluation Kit PEREGRINE SEMICONDUCTOR CORP. | http://www.peregrine-semi.com Shipping Method 40 units / Tray 40 units / Tray 1 / Box Copyright Peregrine Semiconductor Corp. 2003 Page 11 of 12