Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHW14N50E FEATURES SYMBOL • Repetitive Avalanche Rated • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance QUICK REFERENCE DATA d VDSS = 500 V ID = 14 A g RDS(ON) ≤ 0.4 Ω s GENERAL DESCRIPTION PINNING N-channel, enhancement mode field-effect power transistor, intended for use in off-line switched mode power supplies, T.V. and computer monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching applications. PIN SOT429 (TO247) DESCRIPTION 1 gate 2 drain 3 source tab drain 1 The PHW14N50E is supplied in the SOT429 (TO247) conventional leaded package. 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDSS VDGR VGS ID Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Tj = 25 ˚C to 150˚C Tj = 25 ˚C to 150˚C; RGS = 20 kΩ IDM PD Tj, Tstg Pulsed drain current Total dissipation Operating junction and storage temperature range - 55 500 500 ± 30 14 9 56 192 150 V V V A A A W ˚C MIN. MAX. UNIT - 920 mJ - 23 mJ - 14 A Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS EAR IAS, IAR CONDITIONS Non-repetitive avalanche energy Unclamped inductive load, IAS = 14 A; tp = 0.2 ms; Tj prior to avalanche = 25˚C; VDD ≤ 50 V; RGS = 50 Ω; VGS = 10 V Repetitive avalanche energy1 IAR = 14 A; tp = 2.5 µs; Tj prior to avalanche = 25˚C; RGS = 50 Ω; VGS = 10 V Repetitive and non-repetitive avalanche current 1 pulse width and repetition rate limited by Tj max. December 1998 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHW14N50E THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. in free air TYP. MAX. UNIT - - 0.65 K/W - 45 - K/W ELECTRICAL CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. Drain-source breakdown voltage ∆V(BR)DSS / Drain-source breakdown ∆Tj voltage temperature coefficient RDS(ON) Drain-source on resistance VGS(TO) Gate threshold voltage gfs Forward transconductance IDSS Drain-source leakage current VGS = 0 V; ID = 0.25 mA 500 - - V VDS = VGS; ID = 0.25 mA - 0.1 - %/K 2.0 5 - 0.33 3.0 9.5 0.2 250 10 0.4 4.0 20 500 200 Ω V S µA µA nA V(BR)DSS TYP. MAX. UNIT IGSS VGS = 10 V; ID = 7 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 7 A VDS = 500 V; VGS = 0 V VDS = 400 V; VGS = 0 V; Tj = 125 ˚C Gate-source leakage current VGS = ±30 V; VDS = 0 V Qg(tot) Qgs Qgd Total gate charge Gate-source charge Gate-drain (Miller) charge ID = 14 A; VDD = 400 V; VGS = 10 V - 110 9 53 150 12 60 nC nC nC td(on) tr td(off) tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 250 V; RD = 18 Ω; RG = 4.7 Ω - 16 54 110 53 - ns ns ns ns Ld Ld Ls Internal drain inductance Internal drain inductance Internal source inductance Measured from tab to centre of die Measured from drain lead to centre of die Measured from source lead to source bond pad - 3.5 4.5 7.5 - nH nH nH Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 1700 250 140 - pF pF pF SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IS Tmb = 25˚C - - 14 A Tmb = 25˚C - - 56 A VSD Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage IS = 14 A; VGS = 0 V - 0.99 1.5 V trr Qrr Reverse recovery time Reverse recovery charge IS = 14 A; VGS = 0 V; dI/dt = 100 A/µs - 600 10 - ns µC ISM December 1998 MIN. 2 TYP. MAX. UNIT Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated 120 PHW14N50E Normalised Power Derating PD% 110 1 100 90 D = 0.5 80 0.1 70 0.2 0.1 0.05 60 50 P D 0.02 D = tp/T tp 0.01 40 single pulse 30 20 10 T 0.001 1E-06 0 0 20 40 60 80 100 Tmb / C 120 1E-05 1E-04 140 1E-03 1E-02 1E-01 1E+00 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 PHW14N50E Peak Pulsed Drain Current, IDM (A) Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating ID% Drain Current, ID (A) 110 14 100 90 PHW14N50E Tj = 25 C VGS = 10 V 12 80 6V 10 70 8 60 50 5V 6 4.8 V 30 4 4.6 V 20 10 2 40 4.4 V 4.2 V 4V 0 0 0 20 40 60 80 Tmb / C 100 120 0 140 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V 1 2 3 4 Drain-Source Voltage, VDS (V) 5 Fig.5. Typical output characteristics. ID = f(VDS); parameter VGS Drain-Source On Resistance, RDS(on) (Ohms) PHW14N50E 100 Peak Pulsed Drain Current, IDM (A) 1 PHW14N50E 4V 0.9 RDS(on) = VDS/ ID tp = 10 us 4.4 V 4.2V 4.6 V 4.8V Tj = 25 C 5V 0.8 0.7 10 100 us 0.6 0.5 1 ms 10 ms 1 VGS = 6 V 0.4 d.c. 10V 0.3 100 ms 0.2 0.1 0.1 0 10 100 Drain-Source Voltage, VDS (V) 1000 0 Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp December 1998 1 2 3 4 5 6 7 8 9 Drain Current, ID (A) 10 11 12 13 14 Fig.6. Typical on-state resistance. RDS(ON) = f(ID); parameter VGS 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHW14N50E VGS(TO) / V Drain current, ID (A) PHW14N50E 20 max. 4 VDS > ID X RDS(ON) 18 16 14 typ. 3 12 10 min. 150 C 8 2 Tj = 25 C 6 4 1 2 0 0 1 2 3 4 5 6 7 8 0 -60 Gate-source voltage, VGS (V) 1E-01 PHW14N50E Transconductance, gfs (S) VDS > ID X RDS(ON) -20 0 20 40 60 Tj / C 80 100 120 140 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -40 SUB-THRESHOLD CONDUCTION ID / A Tj = 25 C 1E-02 150 C 2% 1E-03 typ 98 % 1E-04 1E-05 0 2 4 6 8 10 12 14 16 18 20 1E-06 0 Drain current, ID (A) Fig.8. Typical transconductance. gfs = f(ID); parameter Tj 1 2 VGS / V 3 4 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised RDS(ON) = f(Tj) a Capacitances, Ciss, Coss, Crss (pF) PHW14N50E 10000 2 Ciss 1000 1 Coss Crss 100 0 -60 -40 -20 0 20 40 60 Tj / C 80 0.1 100 120 140 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 7 A; VGS = 10 V December 1998 1 10 Drain-Source Voltage, VDS (V) 100 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHW14N50E Source-Drain Diode Current, IF (A) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHW14N50E 20 PHW14N50E Gate-source voltage, VGS (V) VGS = 0 V ID = 14A 300 V Tj = 25 C 15 200 V 10 VDD = 400 V 150 C Tj = 25 C 5 0 0 20 40 60 80 100 Gate charge, QG (nC) 120 0 140 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Drain-Source Voltage, VSDS (V) Fig.16. Source-Drain diode characteristic. IF = f(VSDS); parameter Tj Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS Switching times, td(on), tr, td(off), tf (ns) PHW14N50E 400 100 td(off) 350 Non-repetitive Avalanche current, IAS (A) 300 Tj prior to avalanche = 25 C 250 200 10 tf 150 VDS tr 100 ID td(on) 50 1 1E-06 0 0 5 10 15 20 Gate Resistance, RG (Ohms) 25 30 PHP14N50E 1E-05 1E-04 1E-03 1E-02 Avalanche time, tp (s) Fig.14. Typical switching times; td(on), tr, td(off), tf = f(RG) 1.15 125 C tp Fig.17. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tp); unclamped inductive load Normalised Drain-source breakdown voltage V(BR)DSS @ Tj V(BR)DSS @ 25 C 100 1.1 Maximum Repetitive Avalanche Current, IAR (A) 1.05 Tj prior to avalanche = 25 C 10 1 125 C 1 0.95 0.9 0.85 -100 PHP14N50E 0.1 1E-06 -50 0 50 Tj, Junction temperature (C) 100 150 1E-04 1E-03 1E-02 Avalanche time, tp (s) Fig.15. Normalised drain-source breakdown voltage; V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj) December 1998 1E-05 Fig.18. Maximum permissible repetitive avalanche current (IAR) versus avalanche time (tp) 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHW14N50E MECHANICAL DATA Dimensions in mm 5.3 max 16 max 1.8 Net Mass: 5 g 5.3 o 3.5 max 7.3 3.5 21 max 15.5 max seating plane 2.5 15.5 min 4.0 max 1 2 3 0.9 max 2.2 max 1.1 3.2 max 5.45 0.4 M 5.45 Fig.19. SOT429; pin 2 connected to mounting base. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for SOT429 envelope. 3. Epoxy meets UL94 V0 at 1/8". December 1998 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistors Avalanche energy rated PHW14N50E DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. December 1998 7 Rev 1.000