PHILIPS PHD5N20E

Philips Semiconductors
Product specification
PowerMOS transistor
GENERAL DESCRIPTION
N-channel enhancement mode
field-effect power transistor in a
plastic envelope suitable for surface
mounting featuring high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermal cycling performance with low
thermal resistance. Intended for use
in Switched Mode Power Supplies
(SMPS), motor control circuits and
general
purpose
switching
applications.
PINNING - SOT428
PIN
PHD5N20E
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDS
ID
Ptot
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
PIN CONFIGURATION
DESCRIPTION
1
gate
2
drain
3
source
MAX.
UNIT
200
5.0
60
0.9
V
A
W
Ω
SYMBOL
d
tab
g
2
tab
s
drain
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
ID
Continuous drain current
IDM
PD
∆PD/∆Tmb
VGS
EAS
Pulsed drain current
Total dissipation
Linear derating factor
Gate-source voltage
Single pulse avalanche
energy
Peak avalanche current
Tmb = 25 ˚C; VGS = 10 V
Tmb = 100 ˚C; VGS = 10 V
Tmb = 25 ˚C
Tmb = 25 ˚C
Tmb > 25 ˚C
IAS
Tj, Tstg
Operating junction and
storage temperature range
MIN.
MAX.
UNIT
-
5
3.5
20
60
0.4
± 30
40
A
A
A
W
W/K
V
mJ
-
5
A
- 55
175
˚C
VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω;
VGS = 10 V
VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω;
VGS = 10 V
THERMAL RESISTANCES
SYMBOL
PARAMETER
Rth j-mb
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
Rth j-a
October 1997
CONDITIONS
pcb mounted, minimum
footprint
1
TYP.
MAX.
UNIT
-
2.5
K/W
50
-
K/W
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
ELECTRICAL CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V(BR)DSS
VGS = 0 V; ID = 0.25 mA
200
-
-
V
∆V(BR)DSS /
∆Tj
RDS(ON)
VGS(TO)
gfs
IDSS
Drain-source breakdown
voltage
Drain-source breakdown
voltage temperature coefficient
Drain-source on resistance
Gate threshold voltage
Forward transconductance
Drain-source leakage current
VDS = VGS; ID = 0.25 mA
-
0.25
-
V/K
IGSS
Gate-source leakage current
VGS = 10 V; ID = 2.5 A
VDS = VGS; ID = 0.25 mA
VDS = 50 V; ID = 2.5 A
VDS = 200 V; VGS = 0 V
VDS = 160 V; VGS = 0 V; Tj = 150 ˚C
VGS = ±30 V; VDS = 0 V
2.0
1.5
-
0.68
3.0
3.5
0.1
1
10
0.9
4.0
25
250
100
Ω
V
S
µA
µA
nA
Qg(tot)
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
ID = 4.8 A; VDD = 160 V; VGS = 10 V
-
11
2
5.3
15
3
7
nC
nC
nC
td(on)
tr
td(off)
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 100 V; ID = 4.8 A;
RG = 18 Ω; RD = 20 Ω
-
7
29
27
22
-
ns
ns
ns
ns
Ld
Ls
Internal drain inductance
Internal source inductance
Measured from tab to centre of die
Measured from source lead solder
point to source bond pad
-
3.5
7.5
-
nH
nH
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
300
60
20
-
pF
pF
pF
MIN.
TYP.
MAX.
UNIT
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS
Tj = 25 ˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
IS
Tmb = 25˚C
-
-
5
A
Tmb = 25˚C
-
-
20
A
VSD
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
IS = 5.2 A; VGS = 0 V
-
-
1.5
V
trr
Reverse recovery time
IS = 4.8 A; VGS = 0 V;
dI/dt = 100 A/µs
-
114
-
ns
Qrr
Reverse recovery charge
-
0.8
-
µC
ISM
October 1997
2
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
Normalised Power Derating
PD%
120
PHD5N20E
1E+01
110
Zth j-mb / (K/W)
BUKX52
100
90
80
1E+00
70
0.5
0.2
0.1
0.05
1E-01 0.02
60
50
40
30
PD
tp
D=
tp
T
0
20
10
0
20
40
60
80 100
Tmb / C
120
140
160
180
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
1E-05
1E-03
t/s
1E-01
1E+01
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
Normalised Current Derating
ID%
120
t
T
1E-02
1E-07
0
PHP5N20
ID, Drain current (Amps)
10
10 V
110
7V
6V
Tj = 25 C
100
8
90
5.5 V
80
6
70
60
5V
50
4
40
30
VGS = 4.5 V
2
20
10
0
0
20
40
60
80 100
Tmb / C
120
140
160
0
180
0
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V
100
10
15
20
VDS, Drain-Source voltage (Volts)
25
RDS(on), Drain-Source on resistance (Ohms)
3
4.5 V
5V
PHP5N20
5.5 V
6V
2.5
ID
7V
S/
)
10
ON
D
=V
tp = 10 us
2
S(
RD
100 us
1.5
VGS = 10 V
1 ms
1
DC
30
Fig.5. Typical output characteristics.
ID = f(VDS); parameter VGS
PHP5N20E
ID, Drain current (Amps)
5
1
10 ms
100 ms
0.5
Tj = 25 C
0.1
1
10
100
VDS, Drain-source voltage (Volts)
0
1000
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
October 1997
0
2
4
6
ID, Drain current (Amps)
8
10
Fig.6. Typical on-state resistance.
RDS(ON) = f(ID); parameter VGS
3
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
12
PHD5N20E
VGS(TO) / V
PHP5N20E
ID, Drain current (Amps)
VDS = 30 V
max.
Tj = 25 C
4
10
typ.
3
8
Tj = 175 C
min.
6
2
4
1
2
0
0
0
2
4
6
VGS, Gate-source voltage (Volts)
8
-60
10
gfs, Transconductance (S)
20
60
Tj / C
100
140
180
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 0.25 mA; VDS = VGS
Fig.7. Typical transfer characteristics.
ID = f(VGS); parameter Tj
5
-20
PHP5N20E
1E-01
SUB-THRESHOLD CONDUCTION
ID / A
VDD = 30 V
1E-02
4
Tj = 25 C
2%
1E-03
3
typ
98 %
Tj = 175 C
2
1E-04
1
1E-05
0
1E-06
0
2
4
6
8
ID, Drain current (Amps)
10
0
12
Fig.8. Typical transconductance.
gfs = f(ID); parameter Tj
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2
VGS / V
3
4
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Normalised RDS(ON) = f(Tj)
a
1
1000
Ciss, Coss, Crss, Junction capacitances (pF) PHP5N20E
Ciss
Coss
100
Crss
10
-60
-20
20
60
Tj / C
100
140
1
180
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 2.5 A; VGS = 10 V
October 1997
1
10
100
VDS, Drain-source voltage (Volts)
1000
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
4
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
PHP5N20E
VGS, Gate-Source voltage (Volts)
15
ID = 4.8 A
Tj = 25 C
VDS = 40 V
100 V
PHP5N20E
IF, Source-drain diode current (Amps)
20
VGS = 0 V
160 V
15
10
Tj = 25 C
Tj = 175 C
10
5
5
0
0
5
10
Qg, Gate charge (nC)
15
0
20
Switching times (ns)
PHP5N20E
120
110
100
90
80
70
tr
td(off)
tf
10
td(on)
1
0
40
60
RG, Gate resistance (Ohms)
80
100
EAS, Normalised unclamped inductive energy (%)
20
Fig.14. Typical switching times.
td(on), tr, td(off), tf = f(RG)
1.15
1.5
60
50
40
30
20
10
0
VDD = 100 V
VGS = 10 V
RD = 20 Ohms
ID = 4.8 A
Tj = 25 C
20
0.5
1
VSDS, Source-drain voltage (Volts)
Fig.16. Source-Drain diode characteristic.
IF = f(VSDS); parameter Tj
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); parameter VDS
100
0
40
60
80
100
120
Starting Tj ( C)
140
160
180
Fig.17. Normalised unclamped inductive energy.
EAS% = f(Tj)
Normalised Drain-source breakdown voltage
V(BR)DSS @ Tj
+
V(BR)DSS @ 25 C
1.1
VDD
L
1.05
VDS
-
VGS
1
-ID/100
0
0.95
0.9
0.85
-100
RGS
-50
0
50
Tj, Junction temperature (C)
100
R 01
shunt
150
Fig.18. Unclamped inductive test circuit.
EAS = 0.5 ⋅ LID2 ⋅ V(BR)DSS /(V(BR)DSS − VDD )
Fig.15. Normalised drain-source breakdown voltage.
V(BR)DSS/V(BR)DSS 25 ˚C = f(Tj)
October 1997
T.U.T.
5
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
MECHANICAL DATA
Dimensions in mm : Net Mass: 1.4 g
seating plane
6.73 max
1.1
tab
2.38 max
0.93 max
5.4
4 min
6.22 max
10.4 max
4.6
2
1
0.5
0.5 min
3
0.3
0.5
0.8 max
(x2)
2.285 (x2)
Fig.19. SOT428 : centre pin connected to mounting base.
MOUNTING INSTRUCTIONS
Dimensions in mm
7.0
7.0
2.15
1.5
2.5
4.57
Fig.20. SOT428 : soldering pattern for surface mounting.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Epoxy meets UL94 V0 at 1/8".
October 1997
6
Rev 1.100
Philips Semiconductors
Product specification
PowerMOS transistor
PHD5N20E
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1997
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
October 1997
7
Rev 1.100