ETC PI6C182AH

PI6C182
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Precision 1-10 Clock Buffer
Product Features
Description
• Low noise non-inverting 1-10 buffer
Pericom Semiconductor’s PI6C clock series is produced using the
company’s advanced submicron CMOS technology, achieving
industry leading speed.
• Supports frequency up to 125 MHz (PI6C182A)
The PI6C182/182A is a high-speed low-noise 1-10 noninverting
buffer designed for SDRAM clock buffer applications.
• Supports up to four SDRAM DIMMs
• Low skew (<200ps) between any two output clocks
PI6C182 supports frequencies up to 110 MHz. PI6C182A supports higher frequencies up to 125 MHz.
• I2C Serial Configuration interface
At power up all SDRAM output are enabled and active. The I2C
Serial control may be used to individually activate/deactivate any
of the 10 output drivers.
• Multiple VDD, VSS pins for noise reduction
• 3.3V power supply voltage
• Separate Hi-Z state pin for testing
• 28-pin SSOP package (H)
The output enable (OE) pin may be pulled low to Hi-Z state all
outputs.
Block Diagram
Pin Configuration
Note:
Purchase of I2C components from Pericom conveys a license to
use them in an I2C system as defined by Philips.
SDRAM0
SDRAM1
BUF_IN
SDRAM2
SDRAM3
OE
I2C
SCLOCK
I/O
1
28
VDD5
SDRAM0
2
27
SDRAM7
SDRAM1
3
26
SDRAM6
VSS0
4
25
VSS5
VDD1
5
24
VDD4
SDRAM2
6
23
SDRAM5
SDRAM3
7
22
SDRAM4
VSS1
8
21
VSS4
BUF_IN
9
20
OE
10
19
VDD3
SDRAM8
11
18
SDRAM9
VSS2
12
17
VSS3
VDDIIC
13
16
VSSIIC
SDATA
14
15
SCLOCK
VDD2
SDRAM9
SDATA
VDD0
1
28-Pin
H
PS8165C
01/18/01
PI6C182
Precision
1-10
Clock
Buffer
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Pin Description
Pin
Symbol
Type
Qty.
De s cription
2,3,6,7
SDRAM[0- 3]
O
4
SDRAM Byte 0 clock output
22,23,26,27
SDRAM[4- 7]
O
4
SDRAM Byte 1 clock output
11,18
SDRAM[8- 9]
O
2
SDRAM Byte 2 clock output
9
BUF_IN
I
1
Input for 1- 10 buffer
20
OE
I
1
Hi- Z states all outputs when held LOW. Has a >100kΩ
internal pull- up resistor
14
SDATA
I/O
1
Data pin for I2C circuitry. Has a >100kΩ internal pull- up resistor
15
SCLOCK
I/O
1
Clock pin I2C circuitry. Has a >100kΩ internal pull- up resistor
1,5,10,19,24,28
VDD[0-5]
Power
6
3.3V power supply for SDRAM buffer
4,8,12,17,21,25
VSS[0-5]
Ground
6
Ground for SDRAM buffers
13
VDDIIC
Power
1
3.3V power supply for I2C circuitry
16
VSSIIC
Ground
1
Ground for I2C circuitry
OE Functionality
PI6C182 Serial Configuration Map
OE
SDRAM[0-9]
Note
0
Hi-Z
1
1
BUF_IN
2
Byte0: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Notes:
1. Used for test purposes only
2. Buffers are non-inverting
PI6C182 I2C Address Assignment
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0
Pin #
Description
Bit 7
NC (Initialize to 0)
Bit 6
NC (Initialize to 0)
Bit 5
NC (Initialize to 0)
Bit 4
NC (Initialize to 0)
Bit 3
7
SDRAM3 (Active/Inactive)
Bit 2
6
SDRAM2 (Active/Inactive)
Bit 1
3
SDRAM1 (Active/Inactive)
Bit 0
2
SDRAM0 (Active/Inactive)
Note:
Inactive means outputs are held LOW and
are disabled from switching
2
PS8165C
01/18/01
PI6C182
Precision
1-10
Clock
Buffer
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2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock
output and test mode enable.
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW = write to addressed device). If the
device’s own address is detected, PI6C182 generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then
accepts the following data bytes until another start or stop condition
is
detected.
The PI6C182 is a slave receiver device. It can not be read back.
Sub addressing is not supported. All preceding bytes must be sent
in order to change one of the control bytes.
Every byte put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
During normal data transfers SDATA changes only when SCLOCK
is LOW. Exceptions: A HIGH to LOW transition on SDATA
while SCLOCK is HIGH indicates a “start” condition. A LOW to
HIGH transition on SDATA while SCLOCK is HIGH is a “stop”
condition and indicates the end of a data transfer cycle.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte
2. “Byte Count” byte.
Each data transfer is initiated with a start condition and ended with
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
Byte1: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte2: Optional Register for Possible Future
Requirements (1 = enable, 0 = disable)
Bit
Pin #
Bit 7
27
Bit 6
Description
Bit
Pin #
SDRAM7 (Active/Inactive)
Bit 7
18
SDRAM9 (Active/Inactive)
26
SDRAM6 (Active/Inactive)
Bit 6
11
SDRAM8 (Active/Inactive)
Bit 5
23
SDRAM5 (Active/Inactive)
Bit 5
(Reserved)
Bit 4
22
SDRAM4 (Active/Inactive)
Bit 4
(Reserved)
Bit 3
NC (Initialize to 0)
Bit 3
(Reserved)
Bit 2
NC (Initialize to 0)
Bit 2
(Reserved)
Bit 1
NC (Initialize to 0)
Bit 1
(Reserved)
Bit 0
NC (Initialize to 0)
Bit 0
(Reserved)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .......................................................... –65°C to +150°C
Ambient Temperature with Power Applied ........................... –0°C to +70°C
3.3V Supply Voltage to Ground Potential ........................... –0.5V to +4.6V
DC Input Voltage .................................................................. –0.5V to +4.6V
Description
Note:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Supply Current (VDD = +3.465V, CLOAD = Max.)
Symbol
Parame te r
IDD
IDD
M in.
BUF_IN = 0 MHz
IDD
IDD
Te s t Condition
Supply Current
Typ.
M ax.
Units
3
BUF_IN = 66.66 MHz
130
BUF_IN = 100.0 MHz
230
BUF_IN = 133.3 MHz
360
3
mA
PS8165C
01/18/01
PI6C182
Precision
1-10
Clock
Buffer
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DC Operating Specifications (VDD = +3.3V ±5%, TA = 0°C - 70°C)
Symbol
Parame te r
Te s t Condition
M in.
M ax.
Units
VDD
2.0
VDD +0.3
VSS - 0.3
0.8
0 < VIN < VDD
-5
+5
2.4
Input Voltage
VIH
Input high voltage
VIL
Input low voltage
IIL
Input leakage current
V
mA
VDD[0-9] = 3.3V ±5%
VOH
O utput high voltage
IOH = - 1mA
VOL
O utput low voltage
IOL = 1mA
COUT
O utput pin capacitance
6
CIN
Input pin capacitance
5
LPIN
Pin Inductance
7
nH
70
°C
TA
Ambient Temperature
V
0.4
No Airflow
0
pF
SDRAM Clock Buffer Operating Specification
Symbol
Parame te r
Te s t Conditions M in. Typ.
M ax.
Units
- 46
mA
IOHMIN
Pull- up current
VOUT = 2.0V
IOHMAX
Pull- up current
VOUT = 3.135V
IOLMIN
Pull- down current
VOUT = 1.0V
IOLMAX
Pull- down current
VOUT = 0.4V
tRHSDRAM
Output rise edge rate
SDRAM only
3.3V ±5%
@0.4V- 2.4V
1.5
4
tTHSDRAM
Output fall edge rate
SDRAM only
3.3V ±5%
@2.4V- 0.4V
1.5
4
- 54
54
53
V/ns
AC Timing
Symbol
Parame te r
66 M Hz
100 M Hz
133 M Hz
M in.
M ax.
M in.
M ax.
M in.
M ax.
15.5
10.0
10.5
7.5
8.0
Units
tSDKP
SDRAM CLK period
15.0
tSDKH
SDRAM CLK high time
5.6
3.3
2.1
tSDKL
SDRAM CLK low time
5.3
3.1
1.9
tSDRISE
SDRAM CLK rise time
1.5
4.0
1.5
4.0
1.5
4.0
tSDFALL
SDRAM CLK fall time
1.5
4.0
1.5
4.0
1.5
4.0
tPLH
SDRAM Buffer LH prop delay
1.0
5.0
1.0
5.0
1.0
5.0
tPHL
SDRAM Buffer HL prop delay
1.0
5.0
1.0
5.0
1.0
5.0
tPZL,tPZH
SDRAM Buffer Enable delay
1.0
8.0
1.0
8.0
1.0
8.0
tPLZ,tPHZ
SDRAM Buffer Disable delay
1.0
8.0
1.0
8.0
1.0
8.0
Duty Cycle
Measured at 1.5V
45
55
45
55
45
55
%
tSDSKW
SDRAM O utput to O utput Skew
200
ps
250
250
4
ns
V/ns
ns
PS8165C
01/18/01
PI6C182
Precision
1-10
Clock
Buffer
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Test
Output
Point
Buffer
Test Load
tSDKP
tSDKH
3.3V
Clocking
Interface
(TTL)
2.4
1.5
0.4
tSDKL
tSDRISE
Input
tSDFALL
1.5V
1.5V
Waveform
tphl
tplh
Output
1.5V
Waveform
1.5V
Figure 1. Clock Waveforms
Minimum and Maximum Expected Capacitive Loads
Clock
SDRAM
Min. Load Max. Load
20
30
Units
Notes
pF
SDRAM DIMM Specification
Notes:
1. Maximum rise/fall times are guaranteed at maximum specified load.
2. Minimum rise/fall times are guaranteed at minimum specified load.
3. Rise/fall times are specified with pure capacitive load as shown.
Testing is done with an additional 500Ω resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to the respective clock pins. Typical value
for CI is 10pF. Series resistor value can be increased to reduce EMI provided that the rise and fall
time are still within the specified values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing
clock traces from plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables or any external connectors.
5
PS8165C
01/18/01
PI6C182
Precision
1-10
Clock
Buffer
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PCB Layout Suggestion
C1
C7
1
28
2
27
3
26
VSS
4
25
VSS
VDD
5
24
VDD
6
23
7
22
8
21
9
20
10
19
11
18
VSS
12
17
VSS
VDD
13
16
VSS
14
15
VDD
C2
VSS
C3
VDD
C4
VDD
Ferrite Bead
VCC
C8
C6
22uF
VSS
C5
VDD
Via to GND Plane
Via to VDD Plane
Void in Power Plane
Note:
This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C1-C7 should be placed as close as possible to
their respective VDD.
Recommended capacitor values:
C1-C7 .............. 0.1µF, ceramic
C8 .................. 22µF
6
PS8165C
01/18/01
PI6C182
Precision
1-10
Clock
Buffer
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PI6C182
Clock from
Chipset
SDRAM
10
R
S
SDRAM
DIMM
CL
Spec.
Figure 2. Design Guidelines
28-Pin SSOP Package Data
Ordering Information
P/N
De s cription
PI6C182H
110MHz 28- pin SSOP Package
PI6C182AH
140MHz 28- pin SSOP Package
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8165C
01/18/01