MICROCHIP PIC16LC74B-16

PIC16LC74B-16/PTL16
8-Bit CMOS Microcontrollers with A/D Converter
 1999 Microchip Technology Inc.
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
44
43
42
41
40
39
38
37
36
35
34
TQFP
1
2
3
4
5
6 PIC16LC74B-16/PTL16
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/SS/AN4
RA4/T0CKI
NC
NC
RB4
RB5
RB6
RB7
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
• High-performance RISC CPU
• Specially tested
- 16MHz @ 3V
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 16 MHz clock input
DC - 250 ns instruction cycle
• 4K x 14 words of Program Memory,
192 x 8 bytes of Data Memory (RAM)
• Interrupt capability
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM
technology
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Automotive
temperature ranges
• Low-power consumption:
- < 5 mA @ 5V, 4 MHz
- 23 µA typical @ 3V, 32 kHz
- < 3 µA typical standby current
Pin Diagram:
12
13
14
15
16
17
18
19
20
21
22
PIC16LC74B-16/PTL16 Microcontroller Core
Features:
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM module(s)
- Capture is 16 bit, max. resolution is 15.6 ns
- Compare is 16 bit, max. resolution is 250 ns
- PWM max. resolution is 10 bit
• 8-bit multichannel analog-to-digital converter
• Synchronous Serial Port (SSP) with SPI
and I2C
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP), 8-bits wide, with
external RD, WR and CS controls
• Brown-out detection circuitry for Brown-out Reset
(BOR) Pin Diagrams
Preliminary
DS30026A-page 1
PIC16LC74B-16/PTL16
Table of Contents
1.0 General Description ................................................................................................................................................. 3
2.0 Electrical Characteristics.......................................................................................................................................... 5
3.0 DC and AC Characteristics Graphs and Tables..................................................................................................... 27
4.0 Packaging Information ........................................................................................................................................... 29
Index ............................................................................................................................................................................. 33
On-Line Support ............................................................................................................................................................ 35
Reader Response ......................................................................................................................................................... 36
Product Identification System........................................................................................................................................ 37
To Our Valued Customers
Most Current Data Sheet
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An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The
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We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time
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We appreciate your assistance in making this a better document.
DS30026A-page 2
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
1.0
GENERAL DESCRIPTION
This data sheet covers the PIC16LC74B-16/PTL16
device. The functional characteristics of this device are
identical to the PIC16LC74B. For electrical specifications, see the electrical specifications contained within
this document. For all other information about this
device, see the PIC16C63A/65B/73B/74B data sheet
(DS30605).
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 3
PIC16LC74B-16/PTL16
NOTES:
DS30026A-page 4
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
2.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4).......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2).......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined)..................................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) ............................................................200 mA
Maximum current sunk by PORTC and PORTD (combined) ................................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) ...........................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device, at those or any other conditions above those
indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 5
PIC16LC74B-16/PTL16
FIGURE 2-1:
PIC16LC74B-16/PTL16 VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
Voltage (VDD)
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
8 MHz
16 MHz
Frequency (MHz)
Fmax = (24 MHz/V)(VDD.APP.MIN - 2.5V) + 4 MHz
Note:
VDD.APP.MIN is the minimum VDD of the PICmicro® device in the application.
Fmax is no greater than 16 MHz.
DS30026A-page 6
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
2.1
DC Characteristics:
PIC16LC74B-16/PTL-04 (Commercial)
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
D001
VDD
Supply Voltage
D002*
VDR
D003
VPOR
RAM Data Retention
Voltage (Note 1)
VDD Start Voltage to
ensure internal
Power-on Reset signal
VDD Rise Rate to
ensure internal
Power-on Reset signal
Brown-out Reset
voltage trip point
Supply Current
(Note 2, 5)
D004*
SVDD
D004A*
D005
VBOR
D010
IDD
D010A
D021
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C ≤ TA ≤
+70°C for commercial
Min Typ† Max Units
Conditions
2.5
VBOR*
-
TBD
5.5
5.5
-
V
V
V
-
VSS
-
V
0.05
TBD
-
-
3.65
-
4.35
V
-
2.0
3.8
mA
-
3.0
6.0
mA
-
22.5
48
µA
V/mS PWRT enabled (PWRTE bit clear)
V/mS PWRT disabled (PWRTE bit set)
Note 1:
2:
3:
4:
5:
6:
7:
BODEN bit set
XT, RC osc modes
FOSC = 4 MHz, VDD = 3.0V (Note 4)
HS oscillator mode
Fosc = 16MHz, VDD = 3.0V
LP osc mode
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
VDD = 3.0V, WDT disabled, 0°C to +70°C
Power-down Current
0.9
5
µA
(Note 3, 5)
Module Differential
Current (Note 6)
∆IWDT Watchdog Timer
6.0
20
µA WDTE bit set, VDD = 4.0V
∆IBOR Brown-out Reset
350
425
µA BODEN bit set, VDD = 5.0V
These parameters are characterized but not tested.
Data in "Typ" column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD.
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by
the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
IPD
D022*
D022A*
*
†
RC, LP, XT, HS osc modes (DC - 4 MHz)
BOR enabled (Note 7)
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 7
PIC16LC74B-16/PTL16
2.2
DC Characteristics:
PIC16LC74B-16/PTL-04 (Commercial)
DC CHARACTERISTICS
Param
No.
Sym
VIL
D030
D030A
D031
D032
D033
VIH
D040
D040A
D041
D042
D042A
D043
D060
IIL
D061
D063
D070
IPURB
D080
VOL
D083
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
VOH
VSS
VSS
VSS
Vss
Vss
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
-
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
with Schmitt Trigger buffer 0.8VDD
MCLR
0.8VDD
OSC1 (XT, HS and LP modes) 0.7VDD
OSC1 (in RC mode)
0.9VDD
Input Leakage Current (Notes
2, 3)
I/O ports
-
-
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
-
±1
µA
MCLR, RA4/T0CKI
OSC1
-
-
±5
±5
µA
µA
50
250
400
µA
Vss ≤ VPIN ≤ VDD,
Pin at hi-impedance
Vss ≤ VPIN ≤ VDD
Vss ≤ VPIN ≤ VDD,
XT, HS and LP osc modes
VDD = 5V, VPIN = VSS
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
VDD-0.7
-
-
V
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP
modes)
Input High Voltage
I/O ports
with TTL buffer
PORTB weak pull-up current
Output Low Voltage
I/O ports
OSC2/CLKOUT (RC osc
mode)
D090
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C ≤ TA ≤
+70°C for commercial
Operating voltage VDD range as described in DC spec Section 2.1
Min
Typ†
Max
Units
Conditions
Output High Voltage
I/O ports (Note 3)
2.0
0.25VDD
+ 0.8V
Note1
Note1
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
device be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
DS30026A-page 8
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
2.2
DC Characteristics:
PIC16LC74B-16/PTL-04 (Commercial) (Cont.’d)
DC CHARACTERISTICS
Param
No.
Sym
D092
Characteristic
OSC2/CLKOUT (RC osc
mode)
D150*
VOD
D100
COSC2
D101
CIO
Open-Drain High Voltage
Capacitive Loading Specs
on Output Pins
OSC2 pin
All I/O pins and OSC2 (in RC
mode)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C ≤ TA ≤
+70°C for commercial
Operating voltage VDD range as described in DC spec Section 2.1
Min
Typ†
Max
Units
Conditions
VDD-0.7
-
-
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
-
-
8.5
V
-
-
15
pF
-
-
50
pF
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
RA4 pin
In XT, HS and LP modes when
external clock is used to drive
OSC1.
400
pF
SCL, SDA in I2C mode
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
device be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
D102
Cb
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 9
PIC16LC74B-16/PTL16
2.3
AC (Timing) Characteristics
2.3.1
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
DS30026A-page 10
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
2.3.2
TIMING CONDITIONS
The temperature and voltages specified in Table 2-1
apply to all timing specifications unless otherwise
noted. Figure 2-2 specifies the load conditions for the
timing specifications.
TABLE 2-1:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
AC CHARACTERISTICS
FIGURE 2-2:
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
Operating voltage VDD range as described in DC spec Section 2.1.
LC parts operate for commercial/industrial temp’s only.
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 2
Load condition 1
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464Ω
VSS
CL = 50 pF
15 pF
 1999 Microchip Technology Inc.
Preliminary
for all pins except OSC2/CLKOUT
but including D and E outputs as ports
for OSC2 output
DS30026A-page 11
PIC16LC74B-16/PTL16
2.3.3
TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 2-3:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
3
1
3
4
4
2
CLKOUT
TABLE 2-2:
Param
No.
1A
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
(Note 2)
Fosc
Max
Units
Conditions
(Note 3)
DC
—
4
MHz RC and XT osc modes
DC
—
4
MHz HS osc mode (-04)
DC
—
20
MHz HS osc mode (-20)
DC
—
200
kHz LP osc mode
Oscillator Frequency
DC
—
4
MHz RC osc mode
(Note 1)
0.1
—
4
MHz XT osc mode
4
—
20
MHz HS osc mode
5
—
200
kHz LP osc mode
1
Tosc
External CLKIN Period
250
—
—
ns RC and XT osc modes
(Note 3)
250
—
—
ns HS osc mode (-04)
50
—
—
ns HS osc mode (-20)
5
—
—
µs LP osc mode
Oscillator Period
250
—
—
ns RC osc mode
(Note 3)
250
—
10,000
ns XT osc mode
250
—
250
ns HS osc mode (-04)
50
—
250
ns HS osc mode (-20)
5
—
—
µs LP osc mode
2
TCY
Instruction Cycle Time (Note 1) 200
—
DC
ns TCY = 4/FOSC
3*
TosL, External Clock in (OSC1) High
100
—
—
ns XT oscillator
TosH or Low Time
2.5
—
—
µs LP oscillator
15
—
—
ns HS oscillator
4*
TosR, External Clock in (OSC1) Rise
—
—
25
ns XT oscillator
TosF
or Fall Time
—
—
50
ns LP oscillator
—
—
15
ns HS oscillator
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption.
2: All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
3: When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30026A-page 12
External CLKIN Frequency
(Note 1)
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
FIGURE 2-4:
CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 2.1 for load conditions.
TABLE 2-3:
Param
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units Conditions
10*
TosH2ckL
OSC1↑ to CLKOUT↓
—
75
200
ns
Note 1
11*
TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns
Note 1
12*
TckR
CLKOUT rise time
—
35
100
ns
Note 1
13*
TckF
CLKOUT fall time
—
35
100
ns
Note 1
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
15*
TioV2ckH
Port in valid before CLKOUT ↑
16*
TckH2ioI
Port in hold after CLKOUT ↑
17*
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
18A*
TosH2ioI
OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold time)
19*
TioV2osH
20A*
TioR
—
—
0.5TCY + 20
ns
Tosc + 200
—
—
ns
Note 1
0
—
—
ns
Note 1
—
50
150
ns
200
—
—
ns
Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
Port output rise time
—
—
80
ns
21A*
TioF
Port output fall time
—
—
80
ns
22††*
Tinp
INT pin high or low time
TCY
—
—
ns
23††*
Trbp
RB7:RB4 change INT high or low time
TCY
—
—
ns
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 13
PIC16LC74B-16/PTL16
FIGURE 2-5:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 2-2 for load conditions.
FIGURE 2-6:
BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 2-4:
Parameter
No.
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
30
TmcL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40°C to +125°C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40°C to +125°C
32
Tost
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
33*
Tpwrt
Power-up Timer Period
28
72
132
ms
VDD = 5V, -40°C to +125°C
34
TIOZ
I/O Hi-impedance from MCLR
Low or WDT reset
—
—
2.1
µs
TBOR
Brown-out Reset Pulse Width
100
—
—
µs
35
*
†
VDD ≤ BVDD (D005)
These parameters are characterized but not tested.
Data in "Typ" column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30026A-page 14
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
FIGURE 2-7:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 2-2 for load conditions.
TABLE 2-5:
Param
No.
40*
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Sym
Tt0H
Characteristic
Min
T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
41*
Tt0L
T0CKI Low Pulse Width
42*
Tt0P
T0CKI Period
No Prescaler
With Prescaler
45*
Tt1H
T1CKI High Time
Synchronous, Prescaler = 1
Synchronous, Prescaler = 2,4,8
Asynchronous
Synchronous, Prescaler = 1
Synchronous, Prescaler = 2,4,8
46*
Tt1L
T1CKI Low Time
47*
Tt1P
Asynchronous
T1CKI input period Synchronous
48
Asynchronous
Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
Ft1
*
†
Typ† Max Units
0.5TCY + 20
—
—
ns
10
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
0.5TCY + 20
10
TCY + 40
Greater of:
20 or TCY + 40
N
0.5TCY + 20
25
50
0.5TCY + 20
25
50
Conditions
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4,..., 256)
Must also meet
parameter 47
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
Greater of:
50 OR TCY + 40
N
100
—
—
ns
DC
—
200
kHz
2Tosc
—
7Tosc
—
These parameters are characterized but not tested.
Data in "Typ" column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 15
PIC16LC74B-16/PTL16
FIGURE 2-8:
CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
CCPx
(Capture Mode)
50
51
52
CCPx
(Compare or PWM Mode)
53
54
Note: Refer to Figure 2-2 for load conditions.
TABLE 2-6:
Param
No.
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Sym
Characteristic
50*
TccL
51*
TccH CCP1 and CCP2
input high time
52*
TccP
53*
54*
*
†
CCP1 and CCP2
input low time
Min
0.5TCY + 20
No Prescaler
With Prescaler
No Prescaler
With Prescaler
Typ† Max Units
—
—
ns
20
—
—
ns
0.5TCY + 20
—
—
ns
20
—
—
ns
3TCY + 40
N
—
—
ns
TccR CCP1 and CCP2 output rise time
—
25
45
ns
TccF
—
25
45
ns
CCP1 and CCP2 input period
CCP1 and CCP2 output fall time
Conditions
N = prescale value
(1,4 or 16)
These parameters are characterized but not tested.
Data in "Typ" column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30026A-page 16
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
FIGURE 2-9:
PARALLEL SLAVE PORT TIMING (PIC16LC74B-16/PTL16)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 2-2 for load conditions.
TABLE 2-7:
Parameter
No.
62*
PARALLEL SLAVE PORT REQUIREMENTS (PIC16LC74B-16/PTL16)
Sym
TdtV2wrH
Characteristic
Min
Typ†
Max
Units
Data in valid before WR↑ or CS↑ (setup time)
20
—
—
ns
63*
TwrH2dtI
WR↑ or CS↑ to data–in invalid (hold time)
35
—
—
ns
64
TrdL2dtV
RD↓ and CS↓ to data–out valid
—
—
80
ns
TrdH2dtI
RD↑ or CS↑ to data–out invalid
10
—
30
ns
65*
*
†
Conditions
These parameters are characterized but not tested.
Data in "Typ" column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 17
PIC16LC74B-16/PTL16
FIGURE 2-10: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
BIT6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
Note: Refer to Figure 2-2 for load conditions.
TABLE 2-8:
Param.
No.
EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Symbol
Characteristic
71A
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TscH
SCK input high time
Continuous
(slave mode)
Single Byte
72
TscL
70
71
72A
73
73A
TdiV2scH,
TdiV2scL
TB2B
SCK input low time
(slave mode)
Continuous
Single Byte
Setup time of SDI data input to SCK edge
Last clock edge of Byte1 to the 1st clock
edge of Byte2
Hold time of SDI data input to SCK edge
Min
Typ† Max Units
TCY
—
—
ns
1.25TCY + 30
40
1.25TCY + 30
40
100
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
1.5TCY + 40
—
—
ns
Conditions
Note 1
Note 1
Note 1
TscH2diL,
100
—
—
ns
TscL2diL
75
TdoR
SDO data output rise time
—
20
45
ns
76
TdoF
SDO data output fall time
—
10
25
ns
78
TscR
SCK output rise time (master mode)
—
20
45
ns
79
TscF
SCK output fall time (master mode)
—
10
25
ns
80
TscH2doV, SDO data output valid after SCK edge
—
—
100
ns
TscL2doV
† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
74
DS30026A-page 18
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
FIGURE 2-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
MSb
SDO
LSb
BIT6 - - - - - -1
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
Note: Refer to Figure 2.1 for load conditions.
TABLE 2-9:
Param.
No.
71
EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Symbol
TscH
71A
72
TscL
72A
73
73A
TdiV2scH,
TdiV2scL
TB2B
Characteristic
SCK input high time
(slave mode)
Continuous
Single Byte
SCK input low time
Continuous
(slave mode)
Single Byte
Setup time of SDI data input to SCK
edge
Last clock edge of Byte1 to the 1st clock
edge of Byte2
Hold time of SDI data input to SCK edge
Min
Typ† Max Units
1.25TCY + 30
40
1.25TCY + 30
40
100
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
1.5TCY + 40
—
—
ns
Conditions
Note 1
Note 1
Note 1
TscH2diL,
100
—
—
ns
TscL2diL
75
TdoR
SDO data output rise time
20
45
ns
76
TdoF
SDO data output fall time
—
10
25
ns
78
TscR
SCK output rise time (master mode)
20
45
ns
79
TscF
SCK output fall time (master mode)
—
10
25
ns
80
TscH2doV, SDO data output valid after SCK edge
—
100
ns
TscL2doV
81
TdoV2scH, SDO data output setup to SCK edge
TCY
—
—
ns
TdoV2scL
† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
74
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 19
PIC16LC74B-16/PTL16
FIGURE 2-12: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSb
SDO
LSb
BIT6 - - - - - -1
77
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
Note: Refer to Figure 2-2 for load conditions.
TABLE 2-10:
Param.
No.
EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Symbol
Characteristic
71A
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TssL2scL
TscH
SCK input high time
Continuous
(slave mode)
Single Byte
72
TscL
70
71
72A
73
73A
TdiV2scH,
TdiV2scL
TB2B
SCK input low time
(slave mode)
Continuous
Single Byte
Setup time of SDI data input to SCK edge
Min
Typ† Max Units
TCY
—
—
ns
1.25TCY + 30
40
1.25TCY + 30
40
100
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
1.5TCY + 40
—
—
ns
Last clock edge of Byte1 to the 1st clock
edge of Byte2
Hold time of SDI data input to SCK edge
Conditions
Note 1
Note 1
Note 1
TscH2diL,
100
—
—
ns
TscL2diL
75
TdoR
SDO data output rise time
20
45
ns
76
TdoF
SDO data output fall time
—
10
25
ns
77
TssH2doZ SS↑ to SDO output hi-impedance
10
—
50
ns
78
TscR
SCK output rise time (master mode)
20
45
ns
79
TscF
SCK output fall time (master mode)
—
10
25
ns
80
TscH2doV, SDO data output valid after SCK edge
—
100
ns
TscL2doV
83
TscH2ssH, SS ↑ after SCK edge
1.5TCY + 40
—
—
ns
TscL2ssH
† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
74
DS30026A-page 20
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
FIGURE 2-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
(CKP = 0)
83
71
72
SCK
(CKP = 1)
80
MSb
SDO
BIT6 - - - - - -1
LSb
75, 76
SDI
MSb IN
77
BIT6 - - - -1
LSb IN
74
Note: Refer to Figure 2-2 for load conditions.
TABLE 2-11:
Param.
No.
70
71
Symbol
TssL2scH,
TssL2scL
TscH
71A
72
TscL
72A
73A
EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
TB2B
Characteristic
Min
SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
1.25TCY + 30
40
1.25TCY + 30
40
1.5TCY + 40
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
SCK input high time
(slave mode)
Continuous
Single Byte
SCK input low time
Continuous
(slave mode)
Single Byte
Last clock edge of Byte1 to the 1st clock
edge of Byte2
Hold time of SDI data input to SCK edge
Typ† Max Units
Conditions
Note 1
Note 1
Note 1
TscH2diL,
100
—
—
ns
TscL2diL
75
TdoR
SDO data output rise time
20
45
ns
76
TdoF
SDO data output fall time
—
10
25
ns
77
TssH2doZ SS↑ to SDO output hi-impedance
10
—
50
ns
78
TscR
SCK output rise time (master mode)
—
20
45
ns
79
TscF
SCK output fall time (master mode)
—
10
25
ns
80
TscH2doV, SDO data output valid after SCK edge
—
—
100
ns
TscL2doV
82
TssL2doV SDO data output valid after SS↓ edge
—
—
100
ns
83
TscH2ssH, SS ↑ after SCK edge
1.5TCY + 40
—
—
ns
TscL2ssH
† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
74
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 21
PIC16LC74B-16/PTL16
FIGURE 2-14: I2C BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 2-2 for load conditions.
TABLE 2-12:
Parameter
No.
I2C BUS START/STOP BITS REQUIREMENTS
Sym
TSU:STA
90*
THD:STA
91*
TSU:STO
92*
THD:STO
93
*
Characteristic
Min
Typ Max
START condition
100 kHz mode
4700
—
—
Setup time
400 kHz mode
600
—
—
START condition
100 kHz mode
4000
—
—
Hold time
400 kHz mode
600
—
—
STOP condition
100 kHz mode
4700
—
—
Setup time
400 kHz mode
600
—
—
STOP condition
100 kHz mode
4000
—
—
Hold time
400 kHz mode
600
—
—
Units
Conditions
ns
Only relevant for repeated START
condition
ns
After this period the first clock
pulse is generated
ns
ns
These parameters are characterized but not tested.
DS30026A-page 22
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
FIGURE 2-15: I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 2-2 for load conditions.
TABLE 2-13:
Parameter
No.
100*
101*
102*
103*
I2C BUS DATA REQUIREMENTS
Sym
THIGH
TLOW
TR
TF
Characteristic
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall time
90*
TSU:STA
START condition
setup time
91*
THD:STA
START condition hold
time
106*
THD:DAT
Data input hold time
107*
TSU:DAT
Data input setup time
92*
TSU:STO
STOP condition setup
time
109*
TAA
Output valid from
clock
110*
TBUF
Bus free time
Min
Max
Units
100 kHz mode
4.0
—
µs
400 kHz mode
0.6
—
µs
SSP Module
100 kHz mode
1.5TCY
4.7
—
—
µs
400 kHz mode
1.3
—
µs
SSP Module
100 kHz mode
400 kHz mode
1.5TCY
—
20 + 0.1Cb
—
1000
300
ns
ns
100 kHz mode
400 kHz mode
—
20 + 0.1Cb
300
300
ns
ns
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
—
—
—
—
0.9
—
—
—
—
3500
—
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Conditions
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Cb is specified to be from
10-400 pF
Cb is specified to be from
10-400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can
start
Cb
Bus capacitive loading
—
400
pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of
the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line TR max.+tsu; DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line
is released.
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 23
PIC16LC74B-16/PTL16
FIGURE 2-16: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 2-2 for load conditions.
TABLE 2-14:
Param
No.
USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
—
—
100
ns
120*
TckH2dtV
121*
Tckrf
Clock out rise time and fall time (Master Mode)
—
—
50
ns
122*
Tdtrf
Data out rise time and fall time
—
—
50
ns
*
†
SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
Conditions
These parameters are characterized but not tested.
Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 2-17: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
125
126
Note: Refer to Figure 2-2 for load conditions.
TABLE 2-15:
Parameter
No.
125*
USART SYNCHRONOUS RECEIVE REQUIREMENTS
Sym
TdtV2ckL
126*
TckL2dtl
*
†
Characteristic
Min
Typ†
Max
Units Conditions
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
—
—
ns
Data hold after CK ↓ (DT hold time)
15
—
—
ns
These parameters are characterized but not tested.
Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30026A-page 24
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
TABLE 2-16:
A/D CONVERTER CHARACTERISTICS: PIC16LC74B-16/PTL16-04 (COMMERCIAL)
Param Sym
No.
A01
NR
Characteristic
Resolution
Min
Typ†
Max
Units
Conditions
—
—
8 bits
bit
—
<±1
LSb
VREF = VDD
VSS ≤ VAIN ≤ VREF
VREF = VDD
A02
EABS Total Absolute error
—
A03
EIL
Integral linearity error
—
—
<±1
LSb
VREF = VDD
VSS ≤ VAIN ≤ VREF
A04
EDL
Differential linearity error
—
—
<±1
LSb
VREF = VDD
VSS ≤ VAIN ≤ VREF
A05
EFS
Full scale error
—
—
<±1
LSb
VREF = VDD
VSS ≤ VAIN ≤ VREF
A06
EOFF Offset error
—
—
<±1
LSb
VREF = VDD
VSS ≤ VAIN ≤ VREF
VSS ≤ VAIN ≤ VREF
A10
—
A20
VREF Reference voltage
Monotonicity (Note 3)
—
guaranteed
—
—
2.5V
—
VDD + 0.3
V
A25
VAIN
Analog input voltage
VSS - 0.3
—
VREF + 0.3
V
A30
ZAIN
Recommended impedance of
analog voltage source
—
—
10.0
kΩ
A40
IAD
A/D conversion current (VDD)
—
90
—
µA
Average current consumption when A/D is on.
(Note 1)
A50
IREF
VREF input current (Note 2)
10
—
1000
µA
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD
—
—
10
µA
During A/D Conversion
cycle
* These parameters are characterized but not tested.
†Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 25
PIC16LC74B-16/PTL16
FIGURE 2-18: A/D CONVERSION TIMING
BSF ADCON0, GO
134
1 TCY
(TOSC/2) (1)
131
Q4
130
132
A/D CLK
7
A/D DATA
6
5
4
3
2
1
NEW_DATA
OLD_DATA
ADRES
0
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This
allows the SLEEP instruction to be executed.
TABLE 2-17:
Param
No.
130
131
A/D CONVERSION REQUIREMENTS
Sym
TAD
TCNV
Characteristic
Min
A/D clock period
Conversion time (not including S/H time)
(Note 1)
Typ†
Max
Units
Conditions
2.0
—
—
µs
TOSC based, VREF full range
3.0
6.0
9.0
µs
A/D RC Mode
11
Note 2
—
16
11
—
TAD
µs
VDD = 3.0V, Temp. = 100°C,
Rs = 10KΩ
132
TACQ
Acquisition time
5*
—
—
µs
The minimum time is the amplifier
settling time. This may be used if
the "new" input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
134
TGO
Q4 to A/D clock start
—
TOSC/2
—
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
135
TSWC Switching from convert → sample time
1.5 §
—
—
TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See A/D section for minimum requirements.
DS30026A-page 26
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
3.0
DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and Tables not available at this time.
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 27
PIC16LC74B-16/PTL16
NOTES:
DS30026A-page 28
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
44-Lead TQFP
Example
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
Legend: MM...M
XX...X
AA
BB
C
D
E
Note:
*
PIC16LC74B-16/PTL16/PT
9911HAT
Microchip part number information
Customer specific information*
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 29
PIC16LC74B-16/PTL16
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
CH x 45 °
α
A
c
φ
β
L
A1
A2
(F)
Units
Dimension Limits
n
p
Number of Pins
Pitch
Pins per Side
Overall Height
Molded Package Thickness
Standoff
Foot Length
Footprint (Reference)
Foot Angle
Overall Width
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
n1
A
A2
A1
L
(F)
φ
E
D
E1
D1
c
B
CH
α
β
MIN
.039
.037
.002
.018
0
.463
.463
.390
.390
.004
.012
.025
5
5
INCHES
NOM
44
.031
11
.043
.039
.004
.024
.039
3.5
.472
.472
.394
.394
.006
.015
.035
10
10
MAX
.047
.041
.006
.030
7
.482
.482
.398
.398
.008
.017
.045
15
15
MILLIMETERS*
NOM
44
0.80
11
1.00
1.10
0.95
1.00
0.05
0.10
0.45
0.60
1.00
0
3.5
11.75
12.00
11.75
12.00
9.90
10.00
9.90
10.00
0.09
0.15
0.30
0.38
0.64
0.89
5
10
5
10
MIN
MAX
1.20
1.05
0.15
0.75
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
15
*Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
DS30026A-page 30
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
APPENDIX A: REVISION HISTORY
Version
Date
Revision Description
A
6/99
This is a new data sheet providing the electrical specifications for the 3V, 16 MHz
device. For all other information, see the PIC16C63A/65B/73B/74B data sheet
(DS30605).
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 31
PIC16LC74B-16/PTL16
NOTES:
DS30026A-page 32
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
INDEX
U
A
USART
Synchronous Master Mode
Timing Diagram, Synchronous Receive ............ 24
Timing Diagram, Synchronous Transmission .... 24
A/D
Converter Characteristics .......................................... 25
Timing Diagram .......................................................... 26
Absolute Maximum Ratings ................................................. 5
B
Brown-out Reset (BOR)
Timing Diagram .......................................................... 14
W
Watchdog Timer (WDT)
Timing Diagram ......................................................... 14
WWW, On-Line Support ...................................................... 2
C
Capture/Compare/PWM (CCP)
Timing Diagram .......................................................... 16
D
DC Characteristics ............................................................... 8
E
Electrical Characteristics ...................................................... 5
Errata ................................................................................... 2
G
General Description ............................................................. 3
I
I2C (SSP Module)
Timing Diagram, Data ................................................ 23
Timing Diagram, Start/Stop Bits ................................. 22
P
Packaging .......................................................................... 29
Parallel Slave Port (PSP)
Timing Diagram .......................................................... 17
Power-on Reset (POR)
Timing Diagram .......................................................... 14
Product Identification System ............................................ 37
R
Reset
Timing Diagram .......................................................... 14
Revision History ................................................................. 31
T
Timer0
Timing Diagram .......................................................... 15
Timer1
Timing Diagram .......................................................... 15
Timing Diagrams and Specifications .................................. 12
A/D Conversion .......................................................... 26
Brown-out Reset (BOR) ............................................. 14
Capture/Compare/PWM (CCP) .................................. 16
CLKOUT and I/O ........................................................ 13
External Clock ............................................................ 12
I2C Bus Data .............................................................. 23
I2C Bus Start/Stop Bits ............................................... 22
Oscillator Start-up Timer (OST) ................................. 14
Parallel Slave Port (PSP) ........................................... 17
Power-up Timer (PWRT) ........................................... 14
Reset .......................................................................... 14
Timer0 and Timer1 ..................................................... 15
USART Synchronous Receive ( Master/Slave) ......... 24
USART SynchronousTransmission ( Master/Slave) .. 24
Watchdog Timer (WDT) ............................................. 14
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 33
PIC16LC74B-16/PTL16
DS30026A-page 34
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
ON-LINE SUPPORT
Systems Information and Upgrade Hot Line
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
Connecting to the Microchip Internet Web Site
981103
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems, technical information and more
• Listing of seminars and events
 1999 Microchip Technology Inc.
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER and PRO MATE are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries. FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A.
All other trademarks mentioned herein are the property of
their respective companies.
Preliminary
DS30026A-page 35
PIC16LC74B-16/PTL16
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
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RE:
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Total Pages Sent
From: Name
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Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
Device: PIC16LC74B-16/PTL16
N
Literature Number: DS30026A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30026A-page 36
Preliminary
 1998 Microchip Technology Inc.
PIC16LC74B-16/PTL16
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device
X
-XX
PART NO.
Frequency Temperature
Range
Range
/XX
L16
Package
Pattern
Examples:
a) PIC16LC74B-16/PTL16 = Commercial temp.,
TQFP package, 16 MHz, low voltage VDD limits,
QTP pattern #301.
Device
PIC16LC7X(1), PIC16LC7XT(2);VDD range 2.5V to 5.5V
Frequency Range
04
16
20
= 4 MHz
= 16 MHz
= 20 MHz
Note 1:
2:
Temperature Range
blank
=
0°C to
70°C
(Commercial)
Package
PT
=
TQFP (Thin Quad Flatpack)
Pattern
QTP, SQTP, Code or Special Requirements
L16 = 3V, 16 MHz
LC
T
= Low Voltage CMOS
= in tape and reel - PLCC, QFP, TQFP
packages only.
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 37
PIC16LC74B-16/PTL16
NOTES:
DS30026A-page 38
Preliminary
 1999 Microchip Technology Inc.
PIC16LC74B-16/PTL16
NOTES:
 1999 Microchip Technology Inc.
Preliminary
DS30026A-page 39
Note the following details of the code protection feature on PICmicro® MCUs.
•
•
•
•
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
 2002 Microchip Technology Inc.
M
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 2002 Microchip Technology Inc.