PO54G74A, PO74G74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 10/10/07 54, 74 Series GHz Logic FEATURES: DESCRIPTION: . Patented technology . Specified From –40°C to 85°C, –40°C to 125°C, and –55°C to 125°C . Operating frequency is faster than 600MHz . VCC Operates from 1.65V to 3.6V . Propagation delay < 2ns max with 15pf load . Low input capacitance: 4pf typical . Latch-Up Performance Exceeds 250 mA Per JESD 17 . ESD Protection Exceeds JESD 22 . 5000-VHuman-BodyModel (A114-A) . 200-VMachineModel (A115-A) . Available in 14pin 150mil wide SOIC package . Available in 14pin Ceramic Dual Flatpack . Available in 20pin Leadless Ceramic Chip Carrier Potato Semiconductor’s PO74G74A is designed for world top performance using submicron CMOS technology to achieve higher than 600MHz TTL /CMOS output frequency with less than 2ns propagation delay. This dual D flip-flop is designed for 1.65-V to 3.6-V VCC operation. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V system environment. VCC 1D 2 13 2CLR 1CLK 3 12 2D 1PRE 4 11 2CLK 2PRE 1Q 6 9 2Q GND 7 8 2Q 3 2 1 20 19 18 5 6 17 7 15 8 14 9 10 11 12 13 16 2D NC 2CLK NC 2PRE Logic Block Diagram Pin Description INPUTS 4 1Q GND NC 10 5 1Q 1CLK NC 1PRE NC 1Q 2CLR 14 2Q 2Q 1 1CLR NC VCC 1CLR 1D Pin Configuration OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H H H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 1CLR 1 1D 2 D PRE 1 1CLR 3 1PRE 4 1Q 5 1Q 14 Vcc 13 2CLR 12 2D 11 2CLK Q 10 2PRE Q 9 2Q 8 2Q Q Q CLR D PRE 2 6 CLR GND 7 1 Copyright © Potato Semiconductor Corporation PO54G74A, PO74G74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 10/10/07 54, 74 Series GHz Logic Maximum Ratings Description Max Unit Storage Temperature -65 to 150 °C Operation Temperature -55 to 125 °C Operation Voltage -0.5 to +4.6 V Input Voltage -0.5 to +5.5 V Output Voltage -0.5 to Vcc+0.5 V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. DC Electrical Characteristics Symbol Description VOH Output High voltage VOL Test Conditions Min Typ Max Unit Vcc=3V Vin=VIH or VIL, IOH= -12mA 2.4 3 - V Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA - 0.3 0.5 V VIH Input High voltage Guaranteed Logic HIGH Level (Input Pin) 2 - 5.5 V VIL Input Low voltage Guaranteed Logic LOW Level (Input Pin) -0.5 - 0.8 V IIH Input High current Vcc = 3.6V and Vin = 5.5V - - 1 uA IIL Input Low current Vcc = 3.6V and Vin = 0V - - -1 uA VIK Clamp diode voltage Vcc = Min. And IIN = -18mA - -0.7 -1.2 V Notes: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25 °C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. VoH = Vcc – 0.6V at rated current 2 Copyright © Potato Semiconductor Corporation PO54G74A, PO74G74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 10/10/07 54, 74 Series GHz Logic Power Supply Characteristics Symbol IccQ Description Quiescent Power Supply Current Test Conditions (1) Min Typ Max Unit Vcc=Max, Vin=Vcc or GND - 0.1 40 uA Notes: 1. 2. 3. 4. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at Vcc = 3.3V, 25°C ambient. This parameter is guaranteed but not tested. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. Capacitance Parameters (1) Cin Cout Description Test Conditions Typ Input Capacitance Vin = 0V Output Capacitance Vout = 0V 4 6 Unit pF pF Notes: 1 This parameter is determined by device characterization but not production tested. Switching Characteristics Symbol Description Test Conditions (1) M ax - tsu th Setup time before CLK tPLH Propagation Delay CLK to Q CL = 15pF 2 t PHL Propagation Delay CLK to Q CL = 15pF 2 tr/tf Rise/Fall Time 0.8V – 2.0V 0.8 fmax Input Frequency CL=2pF - 15pF Hold time, data after CLK - Min Unit 0.5 ns 0.5 ns - ns 600 MHz ns ns Notes: 1. See test circuits and waveforms. 2. tPLH, tPHL, tsu, and th are production tested. All other parameters guaranteed but not production tested. 3. Airflow of 1m/s is recommended for frequencies above 500MHz 3 Copyright © Potato Semiconductor Corporation PO54G74A, PO74G74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 10/10/07 54, 74 Series GHz Logic Test Waveforms VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at V LOAD (see Note B) tPLH VM VM VM 0V tPZL tPLZ VLOAD/2 VM tPZH VOH Output VI Output Control VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VΔ VOL tPHZ VM VOH - VΔ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING Test Circuit Vcc Pulse Generator 50Ω D.U.T 15pF to 2pF 4 Copyright © Potato Semiconductor Corporation PO54G74A, PO74G74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 10/10/07 54, 74 Series GHz Logic Packaging Mechanical Drawing: 14 pin 150mil SOIC 0.244 6.20 0.228 5.80 0.010 0.007 0.050 1.27 0.016 0.40 0.25 0.17 X.XX Denotes dimensions in inches X.XX X.XX Denotes dimensions in millimenters X.XX Packaging Mechanical Drawing: 14pin Leadless Ceramic Chip Carrier X.XX Denotes dimensions in inches X.XX X.XX Denotes dimensions in millimenters X.XX 5 Copyright © Potato Semiconductor Corporation PO54G74A, PO74G74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 10/10/07 54, 74 Series GHz Logic Packaging Mechanical Drawing: 20pin Ceramic Dual Flatpack 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 3 2 1 13 12 4 18 5 17 6 16 0.358 (9,09) 7 0.307 (7,80) 15 8 14 0.358 (9,09) 0.342 (8,69) 9 10 11 12 X.XX Denotes dimensions in inches X.XX X.XX Denotes dimensions in millimenters X.XX 13 Ordering Information Ordering Code Package Top-Marking TA PO74G74ASU 14pin SOIC Tube Pb-free & Green PO74G74AS -40°C to 85°C PO74G74ASR 14pin SOIC Tape and reel Pb-free & Green PO74G74AS -40°C to 85°C PO74G74ASiU 14pin SOIC Tube Pb-free & Green PO74G74ASi -40°C to 125° C PO74G74ASiR 14pin SOIC Tape and reel Pb-free & Green PO74G74ASi -40°C to 125° C Tube Pb-free & Green PO54G74AL -55°C to 125° C Tube Pb-free & Green PO54G74AF -55°C to 125° C 14pin Leadless Ceramic Chip Carrier PO54G74ALU 20pin Ceramic Dual Flatpack PO54G74AFU IC Package Information PACKAGE TYPE TAPE WIDTH (mm) TAPE PITCH (mm) PIN 1 LOCATION TAPE TRAILER LENGTH QTY PER REEL TAPE LEADER LENGTH QTY PER TUBE S SOIC 14 16 8 Top Left Corner 39 (12”) 3000 64 (20”) 55 L LCCC 20 N/A N/A N/A N/A N/A N/A 55 F CFP 14 N/A N/A N/A N/A N/A N/A 150 PACKAGE CODE 6 Copyright © Potato Semiconductor Corporation