hmp 1M x 32 SRAM MODULE PUMA 84S32000 - 012/015/020 Elm Road, West Chirton Industrial Estate, North Shields, NE29 8SE, ENGLAND. TEL +44 (0191) 2930500. FAX +44 (0191) 2590997 Issue 2.0 : March 2002 Description Features The PUMA 84S32000 is a 32Mbit CMOS High Speed Static RAM organised as 1M x 32 in a JEDEC 84 pin surface mount J-leaded PLCC, available with access times of 12, 15, and 20ns. The output width is user configurable as 8, 16 or 32 bits using eight Chip Selects (CS1~8). The device features low power standby, multiple ground pins for maximum noise immunity and TTL compatible • Very fast access times of 12/15/20 ns . • JEDEC 84 'J' leaded plastic Surface Mount Package. • Single 5V±10% Power supply. • User Configurable as 8 / 16 / 32 bit wide output. • Operating Power (32-BIT) Low Power Standby CMOS 5.28 W (max) 550 mW (max) inputs and outputs. The PUMA 84S32000 offers a dramatic space saving advantage over eight standard • Fully Static operation. 512Kx8 devices. • Multiple ground pins for maximum noise immunity. Block Diagram Pin Definition NC NC D16 A18 A17 CS4 CS3 CS2 CS1 NC VCC CS8 CS7 CS6 CS5 OE WE A16 A15 A14 D15 A0 - A18 WE OE 11 10 9 512K x 8 SRAM CS1 512K x 8 SRAM D0 - D7 D0 - D7 CS5 512K x 8 SRAM CS2 D8 - D15 512K x 8 SRAM D8 - D15 CS6 512K x 8 SRAM CS3 D16 - D23 512K x 8 SRAM D16 - D23 CS7 512K x 8 SRAM CS4 D24 - D31 512K x 8 SRAM CS8 D24 - D31 NC NC D17 D18 D19 GND D20 D21 D22 D23 VCC D24 D25 D26 D27 GND D28 D29 D30 NC NC 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 14 72 15 71 16 70 17 69 68 18 19 PUMA 84S32000 VIEW 21 23 FROM 63 24 ABOVE 62 25 61 26 60 27 59 28 58 29 57 30 56 55 31 54 32 A13 A12 A11 A10 A9 A8 A7 D0 NC NC NC NC D31 A6 A5 A4 A3 A2 A1 A0 VCC Pin Functions A0 ~ A18 D0 ~ D31 CS1 ~ 8 WE Package Details OE NC VCC GND 65 64 22 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Address Inputs Data Input/Output Chip Select Write Enable Output Enable No Connect Power (+5V) Ground 67 66 20 Plastic 84 J-Leaded JEDEC PLCC NC NC D14 D13 D12 GND D11 D10 D9 D8 VCC D7 D6 D5 D4 GND D3 D2 D1 NC NC PUMA 84S32000 - 012/015/020 Issue 2.0 : March 2002 DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Parameter Symbol (2) T Voltage on any pin relative to VSS Power Dissipation Storage Temperature V PT TSTG Min Typ Max Unit -0.5 -65 - 7.0 5.0 150 V W o C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) VT can be -2.0V pulse of less than 8ns. Recommended Operating Conditions Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temperature (Commercial) (Industrial) DC Electrical Characteristics Parameter I/P Leakage Current Min Typ Max VCC VIH VIL TA TAI 4.5 2.2 -0.3 0 -40 5.0 - 5.5 VCC+0.5 0.8 70 85 Standby Supply Current Min Typ max Unit 0V < VIN < VCC -20 - 20 µA ILO CS = VIH, VI/O = GND to VCC -20 - 20 µA 32-bit mode ICC32 Min. Cycle, CS = VIL, f=fMAX, IOUT = 0mA - - 960 mA 16-bit mode ICC16 As Above. - - 640 mA 8-bit mode ICC8 As Above. - - 480 mA TTL levels ISB1 CS = VIH, f=fMAX - - 320 mA CMOS levels ISB2 CS > VCC-0.2V, 0.2<VIN<VCC-0.2V, f=0 - - 100 mA VOL IOL = 8.0mA - - 0.4 V VOH IOH = -4.0mA 2.4 - - V Notes : 1/ Typical values are at VCC=5.0V,TA=25oC and specified loading. 2/ CS above refers to CS1~4 / CS5~8 for 32 bit mode 3/ V V V o C o C (Suffix I) ILI Address,OE,WE Operating Supply Current Unit (VCC=5V±10%, -40 to 85 C) Symbol Test Condition Output Leakage Current Output Voltage Symbol At f=fMAX address and data inputs are cycling at maximum frequency. 2 PUMA 84S32000 - 012/015/020 Issue 2.0 : March 2002 Capacitance (VCC=5V±10%,TA=25oC) Note: Capacitance calculated, not measured. Parameter Symbol Test Condition Input Capacitance I/P Capacitance I/O Capacitance CIN1 CIN2 CI/O (Address,OE,WE) (Other) Worst case (8-bit) max Unit 70 12 62 pF pF pF VIN = 0V VIN = 0V VI/O = 0V AC Test Conditions Output Load I/O Pin * Input pulse levels: 0V to 3.0V 166Ω * Input rise and fall times: 3ns 1.76V * Input and Output timing reference levels: 1.5V 30pF * Output load: see diagram * VCC=5V±10% Operation Truth Table CS OE WE DATA PINS SUPPLY CURRENT MODE H X X High Impedance ISB1 , ISB2 Standby L L H Data Out ICC32 , ICC16 , ICC8 Read L H L Data In ICC32 , ICC16 , ICC8 Write L L L Data In ICC32 , ICC16 , ICC8 Write L H H High-Impedance ISB1 , ISB2 High-Z Notes : H = VIH : L =VIL : X = VIH or VIL The above table reflects the operation of each of the RAM's on the module. Care should be taken to avoid bus contention on data lines using chip select signals. 3 PUMA 84S32000 - 012/015/020 Issue 2.0 : March 2002 AC OPERATING CONDITIONS Read Cycle 012 Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold from Address Change Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to O/P in High Z Output Disable to Output in High Z 015 020 Symbol min max min max min max Unit tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ 12 3 3 0 0 0 12 12 6 6 6 15 3 3 0 0 0 15 15 7 7 7 20 3 3 0 0 0 20 20 9 9 9 ns ns ns ns ns ns ns ns ns Write Cycle 012 Parameter Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output active from end of write 015 020 Symbol min max min max min max Unit tWC tCW tAW tAS tWP tWR tWHZ tDW tDH tOW 12 10 10 0 10 0 0 6 0 3 6 - 15 12 12 0 12 0 0 7 0 3 7 - 20 15 15 0 12 0 0 9 0 3 9 - ns ns ns ns ns ns ns ns ns ns 4 PUMA 84S32000 - 012/015/020 Issue 2.0 : March 2002 Read Cycle Timing Waveform (1,2) t RC Address t AA OE t OE t OH t OLZ CS t ACS Don't care. t OHZ (3) t CLZ (4,5) Dout Data Valid t CHZ (3,4,5) AC Read Characteristics Notes (1) WE is High for Read Cycle. (2) All read cycle timing is referenced from the last valid address to the first transition address. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. (4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module and from module to module. (5) These parameters are sampled and not 100% tested. Write Cycle No.1 Timing Waveform(1,4) tWC Address t WR(7) OE t AS(6) t AW t CW CS Don't Care WE t OHZ(3,9) t OW t WP(2) High-Z Dout t DW Din High-Z t DH Data Valid 5 (8) PUMA 84S32000 - 012/015/020 Issue 2.0 : March 2002 Write Cycle No.2 Timing Waveform (1,5) tWC Address t AS(6) t WR(7) t CW CS t AW t WP(2) WE tOH t WHZ(3,9) t OW High-Z Dout t DW Din (8) (4) Don't Care t DH High-Z Data Valid AC Write Characteristics Notes (1) All write cycle timing is referenced from the last valid address to the first transition address. (2) All writes occur during the overlap of CS and WE low. (3) If OE, CS, and WE are in the Read mode during this period, the I/O pins are low impedance state. Inputs of opposite phase to the output must not be applied because bus contention can occur. (4) Dout is the Read data of the new address. (5) OE is continuously low. (6) Address is valid prior to or coincident with CS and WE low, too avoid inadvertant writes. (7) CS or WE must be high during address transitions. (8) When CS are low : I/O pins are in the output state. Input signals of opposite phase leading to the output should not be applied. (9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested. 6 PUMA 84S32000 - 012/015/020 Package Information Issue 2.0 : March 2002 Dimensions in mm(inches) Plastic 84 Pin JEDEC Surface mount PLCC XXXXXX-X X X X X X X X X -X X X X X X X -X X XXXX 30.35 (1.195) 30.10 (1.185) 5.08 (0.200) max 29.20 (1.150) 28.20 (1.110) 7 0.90 (0.035) typ PUMA 84S32000 - 012/015/020 Issue 2.0 : March 2002 Ordering Information PUMA84S32000LI-012 Speed 012 015 020 = = = 12 ns 15 ns 20 ns Temperature Range Blank I = = Commercial Temperature Industrial Temperature Power Consumption Blank L = = Standard Low Power Organisation 32000 = 1M x 32 SRAM configurable as 2M x 16 and 4M x 8 S = Asynchronous SRAM 5V + 10% VCC PUMA 84 = Memory Stack 84 pin 'J' Leaded Memory Type Package Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed at any time without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. 8