QL8X12B pASIC 1 Family Very-High-Speed CMOS FPGA ® Rev B pASIC HIGHLIGHTS Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. …1,000 usable ASIC gates, 64 I/O pins High Usable Density – An 8-by-12 array of 96 logic cells provides 1,000 usable ASIC gates (2,000 PLD gates) in 44-pin and 68-pin PLCC, and 100-pin TQFP packages. Low-Power, High-Output Drive – Standby current typically 2 mA. A 16-bit counter operating at 100 MHz consumes less than 50 mA. Minimum IOL of 12 mA and IOH of 8 mA QL8x12B Block Diagram 96 Logic Cells = Up to 56 prog. I/O cells, 6 Input high-drive cells, 2 Input/Clk (high-drive) cells 4-5 4 pASIC 1 Low-Cost, Easy-to-Use Design Tools – Designs entered and simulated using QuickLogic's new QuickWorks development environment, or with third-party CAE tools including Viewlogic, Synopsys, Mentor, Cadence and Veribest. Fast, fully automatic place and route on PC and workstation platforms using QuickLogic software. QL8X12B PRODUCT SUMMARY The QL8x12B is a member of the pASIC 1 Family of very-high-speed CMOS user-programmable ASIC devices. The 96 logic cell fieldprogrammable gate array (FPGA) offers 1,000 usable “gate array” gates (equivalent to 2,000 usable PLD gates) of high-performance generalpurpose logic in 44-pin and 68-pin PLCC packages and 100-pin TQFP packages. Low-impedance, metal-to-metal, ViaLink interconnect technology provides nonvolatile custom logic capable of operating above 150 MHz. Logic cell delays under 2 ns, combined with input delays of under 1.5 ns and output delays under 3 ns, permit high-density programmable devices to be used with today’s fastest microprocessors and DSPs. Designs can be entered using QuickLogic’s QuickWorks Toolkit or most populart third-party CAE tools. QuickWorks combines Verilog/VHDL design entry and simulation tools with device-specific place & route and programming software. Ample on-chip routing channels allow fast, fully automatic place and route of designs using up to 100% of the logic and I/O cells, while maintaining fixed pin-outs. FEATURES Total of 64 I/O pins – 56 Bidirectional Input/Output pins – 6 Dedicated Input/High-Drive pins – 2 Clock/Dedicated input pins with fanout-independent, low-skew clock networks Input + logic cell + output delays under 6 ns Chip-to-chip operating frequencies up to 110 MHz Internal state machine frequencies up to 150 MHz Clock skew < 0.5 ns Input hysteresis provides high noise immunity Built-in scan path permits 100% factory testing of logic and I/O cells and functional testing with Automatic Test Vector Generation (ATVG) software after programming Available packages are 44- and 68-pin PLCC, and a 100-pin TQFP 68-pin PLCC compatible with QL12x16B 100-pin TQFP compatible with QL12x16B and QL16x24B 0.65µ CMOS process with ViaLink programming technology 4-6 QL8X12B Pinout Diagram 44-pin PLCC 4 Pins identified I/SCLK, SM, SO and SI are used during scan path testing operation. 4-7 pASIC 1 Pinout Diagram 68-pin PLCC QL8X12B Pinout Diagram 100-pin TQFP 4-8 QL8X12B ABSOLUTE MAXIMUM RATINGS Supply Voltage.................................. –0.5 to 7.0V Input Voltage ....................... –0.5 to VCC +0.5V ESD Pad Protection................................... ±2000V DC Input Current ...................................... ±20 mA Latch-up Immunity ................................ ±200 mA Storage Temperature....... –65°C to + 150°C Lead Temperature................................... 300°C OPERATING RANGE Symbol VCC TA TC K Parameter Supply Voltage Ambient Temperature Case Temperature -X Speed Grade Delay Factor -0 Speed Grade -1 Speed Grade -2 Speed Grade Military Min Max 4.5 5.5 -55 125 0.39 0.39 1.82 1.56 Industrial Min Max 4.5 5.5 -40 85 Commercial Min Max 4.75 5.25 0 70 0.4 0.4 0.4 0.4 0.46 0.46 0.46 0.46 2.75 1.67 1.43 1.35 Unit V °C °C 2.55 1.55 1.33 1.25 4 Symbol VIH VIL Parameter Input HIGH Voltage Input LOW Voltage VOH Output HIGH Voltage VOL Output LOW Voltage II IOZ CI IOS Input Leakage Current 3-State Output Leakage Current Input Capacitance [1] Output Short Circuit Current [2] ICC D.C. Supply Current [3] Conditions Min 2.0 Max 0.8 IOH = -4 mA IOH = -8 mA IOH = -10 µA IOL = 12 mA* IOL = 10 µA VI = VCC or GND VI = VCC or GND VO = GND VO = VCC VI, VIO = VCC or GND 3.7 2.4 VCC-0.1 -10 -10 -10 30 0.4 0.1 10 10 10 -80 140 10 Unit V V V V V V V µA µA pF mA mA mA *IOL = 12 mA for commercial range only. IOL = 8 mA for the industrial and military ranges. Notes: [1] [2] [3] [4] [5] Capacitance is sample tested only. CI = 20 pF max on I/(SI). Only one output at a time. Duration should not exceed 30 seconds. Commercial temperature grade only. Maximum Icc for industrial grade is 15mA and for military grade is 20 mA. For AC conditions use the formula described in the Section 9 — Power vs Operating Frequency. Stated timing for worst case Propagation Delay over process variation at VCC = 5.0V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range. These limits are derived from a representative selection of the slowest paths through the pASIC logic cell including net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design . 4-9 pASIC 1 DC CHARACTERISTICS over operating range QL8X12B AC CHARACTERISTICS at VCC = 5V, TA = 25°C (K = 1.00) Logic Cell Symbol tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Parameter 1 1.7 2.1 0.0 1.0 2.0 2.0 1.7 1.5 1.9 1.8 Combinatorial Delay [5] Setup Time [5] Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width Propagation Delays (ns) Fanout 2 3 4 2.1 2.6 3.0 2.1 2.1 2.1 0.0 0.0 0.0 1.5 1.9 2.3 2.0 2.0 2.0 2.0 2.0 2.0 2.1 2.6 3.0 1.8 2.2 2.5 1.9 1.9 1.9 1.8 1.8 1.8 8 4.8 2.1 0.0 4.2 2.0 2.0 4.8 3.9 1.9 1.8 Input Cells Symbol tIN tINI tIO tGCK tGCKHI tGCKLO Propagation Delays (ns) [4] Parameter 1 2.1 2.1 1.4 2.7 2.0 2.0 High Drive Input Delay [6] High Drive Input, Inverting Delay [6] Input Delay (bidirectional pad) Clock Buffer Delay [7] Clock Buffer Min High [7] Clock Buffer Min Low [7] 2 2.2 2.2 1.8 2.7 2.0 2.0 3 2.3 2.3 2.2 2.8 2.0 2.0 4 2.4 2.5 2.6 2.9 2.0 2.0 6 2.6 2.8 3.4 3.0 2.0 2.0 8 2.9 3.1 4.2 Output Cell Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Parameter 30 2.7 2.8 4.0 3.6 2.9 3.3 Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state [8] Output Delay Low to Tri-state [8] Propagation Delays (ns) [4] Output Load Capacitance (pF) 50 75 100 3.4 4.2 5.0 3.7 4.7 5.6 4.9 6.1 7.3 4.2 5.0 5.8 150 6.7 7.6 9.7 7.3 Notes: [6] [7] [8] See High Drive Buffer Table for more information. Clock buffer fanout refers to the maximum number of flip flops per half column. The number of half columns used does not affect clock buffer delay. tPHZ 1KΩ The following loads are used for tPXZ: 5 pF 1KΩ tPLZ 5 pF 4-10 QL8X12B High Drive Buffer Clock Drivers Wired Together Symbol Parameter tIN High Drive Input Delay tINI High Drive Input, Inverting Delay 1 2 3 4 1 2 3 4 Propagation Delays (ns) [4] Fanout 12 24 48 72 96 4.0 4.9 3.5 5.0 4.0 4.8 5.6 4.1 4.8 4.2 5.1 3.7 5.2 4.2 5.0 5.8 4.3 5.0 AC Performance ORDERING INFORMATION QL 8x12B - 1 PL68 C QuickLogic pASIC device Operating Range C = Commercial I = Industrial M = Military pASIC device part number B = 0.65 micron CMOS Package Code PL44 = 44-pin PLCC PL68 = 68-pin PLCC PF100 = 100-pin TQFP Speed Grade X = quick 0 = fast 1 = faster 2 = fastest 4-11 4 pASIC 1 Propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature, and process variation. The AC Characteristics are a design guide to provide initial timing estimates at nominal conditions. Worst case estimates are obtained when nominal propagation delays are multiplied by the appropriate Delay Factor, K, as specified in the Delay Factor table (Operating Range). The effects of voltage and temperature variation are illustrated in the graphs on page 4-47, K Factor versus Voltage and Temperature. The pASIC Development Tools incorporate data sheet AC Characteristics into the QDIF database for pre-place-and-route timing analysis. The SpDE Delay Modeler extracts specific timing parameters for precise path analysis or simulation results following place and route. QL8X12B 4-12