QT60160, QT60240
lQ
PRELIMINARY INFORMATION
16 AND 24 KEY QMATRIX™ TOUCH ICs
Y2B
SMP
SDA
SCL
/RST
Y0A
Y1A
Y2A
M_SYNC
DETECT
1
2
32 31 30 29 28 27 26 25
24
23
Y1B
Y0B
VSS
VDD
3
4
QT60240
QT60160
22
21
A0
VSS
VSS
VDD
X6
5
6
7
MLF-32
20
19
18
VDD
A1
VDD
X7
8
17
9 10 11 12 13 14 15 16
X5
X4
X3
X2
X1
X0
S_SYNC
VREF
LATCH
! Second generation QMatrix technology
! Keys individually adjustable for sensitivity, response
time, and many other critical parameters
! Panel thicknesses to 50mm through any dielectric
! 100% autocal for life - no adjustments required
! I2C slave interface or shift register output
! AKS™ - Patented Adjacent Key Suppression feature
! Spread-spectrum modulation for high noise immunity
! Mix and match key sizes and shapes in one panel
! Low power modes
! Low external component count
! Low cost per key
! +1.8V to +5V single supply operation
! 32-pin RoHS compliant MLF package
APPLICATIONS
! Security keypanels
! Industrial keyboards
! Appliance controls
! Outdoor keypads
! ATM machines
! Touchscreens
! Automotive panels
! Machine tools
These digital charge-transfer (“QT”) QMatrix™ ICs are designed to detect human touch on up to 16 or 24 keys when used with
a scanned, passive X-Y matrix. They will project touch keys through almost any dielectric, e.g. glass, plastic, stone, ceramic,
and even wood, up to thicknesses of 5cm or more. The touch areas are defined as simple two-part interdigitated electrodes of
conductive material, like copper or screened silver or carbon deposited on the rear of a control panel. Key sizes, shapes and
placement are almost entirely arbitrary; sizes and shapes of keys can be mixed within a single panel of keys and can vary by a
factor of 20:1 in surface area. The sensitivity of each key can be set individually via simple functions over the serial port by a
host microcontroller. Key setups are stored in an onboard EEPROM and do not need to be reloaded with each powerup.
These devices are designed specifically for appliances, electronic kiosks, security pan els, portable instruments, machine tools,
or similar products that are subject to environmental influences or even vandalism. They permit the construction of 100%
sealed, watertight control panels that are immune to humidity, temperature, dirt accumulation, or the physical deterioration of
the panel surface from abrasion, chemicals, or abuse. To this end they contain Quantum-pioneered adaptive auto
self-calibration, drift compensation , and digital filtering algorithms that make the sensing function robust and survivable.
Common PCB materials or flex circuits can be used as the circuit substrate; the overlying panel can be made of any
nonconducting material. External circuitry consists of only a few passive parts . Control and data transfer is via I 2C.
These devices make use of an important new variant of charge-transfer sensing, transverse charge-transfer, in a matrix format
that minimizes the number of required scan lines. Unlike older methods, it does not require one IC per key.
AVAILABLE OPTIONS
Part Number
QT60160-XSG
QT60240-XSG
LQ
Preliminary information; subject to change
Keys
16
24
TA
-400C to +850C
-400C to +850C
Copyright © 2006 QRG Ltd
QT60240-XSG X7.04/0706
Contents
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1.2 Part Differences
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2 Hardware and Functional . . . . . . . . . . . . . . . . . . . .
2.1 Matrix Scan Sequence . . . . . . . . . . . . . . . . . . . . . .
2.2 Disabling Keys - Burst Paring . . . . . . . . . . . . . . . . . .
2.3 Sample Capacitors - Saturation . . . . . . . . . . . . . . . . .
2.4 Sample Resistors . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Matrix Series Resistors . . . . . . . . . . . . . . . . . . . . .
2.7 Key Design . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 PCB Layout, Construction . . . . . . . . . . . . . . . . . . . .
2.8.1 Overview
..........................
2.8.2 LED Traces and Other Switching Signals
.............
2.8.3 PCB Cleanliness
.......................
2.9 Power Supply Considerations . . . . . . . . . . . . . . . . . .
2.10 Startup / Calibration Times . . . . . . . . . . . . . . . . . . .
2.11 Reset Input
..........................
2.12 Spread Spectrum Acquisitions . . . . . . . . . . . . . . . . .
2.13 Detection Integrators . . . . . . . . . . . . . . . . . . . . . .
2.14 Sleep
.............................
2.15 Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Shift Register Output
......................
3.3 I2C Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Control Commands . . . . . . . . . . . . . . . . . . . . . . .
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Writing Data to the Device . . . . . . . . . . . . . . . . . . . .
4.3 Reading Data From the Device
.................
4.4 Report Detections for All Keys . . . . . . . . . . . . . . . . . .
4.5 Raw Data Commands
.....................
4.6 Cal All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Setups
.............................
1 Overview
1.1 Introduction
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5.2 Transferring Data Bits . . . . . . . . . . . . . . . . . . . . . .
5.3 START and STOP Conditions . . . . . . . . . . . . . . . . . .
5.4 Address Packet Format . . . . . . . . . . . . . . . . . . . . .
5.5 Data Packet Format . . . . . . . . . . . . . . . . . . . . . . .
5.6 Combining Address and Data Packets Into a
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Negative Threshold - NTHR . . . . . . . . . . . . . . . . . . .
6.3 Positive Threshold - PTHR
...................
6.4 Positive Recalibration Delay - PRD
...............
6.5 Drift Compensation - NDRIFT, PDRIFT . . . . . . . . . . . . .
6.6 Detect Integrators - NDIL, FDIL . . . . . . . . . . . . . . . . .
6.7 Negative Recal Delay - NRD . . . . . . . . . . . . . . . . . . .
6.8 Burst Length - BL . . . . . . . . . . . . . . . . . . . . . . . .
6.9 Adjacent Key Suppression - AKS
................
6.10 Oscilloscope Sync - SSYNC . . . . . . . . . . . . . . . . . .
6.11 Mains Sync - MSYNC
.....................
6.12 Sleep Duration - SLEEP . . . . . . . . . . . . . . . . . . . .
6.13 Wake on Key Touch - WAKE . . . . . . . . . . . . . . . . . .
6.14 Awake Timeout - AWAKE
...................
6.15 Drift Hold Time - DHT
.....................
6.16 Setups Block
.........................
7 Specifications
..........................
7.1 Absolute Maximum Electrical Specifications . . . . . . . . . . .
7.2 Recommended Operating Conditions . . . . . . . . . . . . . .
7.3 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . .
7.4 Timing Specifications . . . . . . . . . . . . . . . . . . . . . .
7.5 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . .
7.6 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 I2C Operation
5.1 Interface Bus
2
Preliminary information; subject to change
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QT60240-XSG X7.04/0706
1 Overview
1.1 Introduction
QT60xx0 devices are digital burst mode charge-transfer (QT)
sensors designed specifically for matrix geometry touch
controls; they include all signal processing functions
necessary to provide stable sensing under a wide variety of
changing conditions. Only a few external parts are required
for operation. The entire circuit can be built within a few
square centimeters of single-sided PCB area. CEM-1 and
FR1 punched, single-sided materials can be used for the
lowest possible cost. The PCB’s rear can be mounted flush
on the back of a glass or plastic panel using a conventional
adhesive, such as 3M VHB two-sided adhesive acrylic film.
Figure 1.1 Field Flow Between X and Y Elements
overlying panel
X
element
Y
elem ent
Unused keys are always pared from the burst sequence in
order to optimize speed. Similarly, in a given part a lesser
number of enabled keys will cause any unused acquisition
burst timeslots to be pared from the sampling sequence to
optimize acquire speed. Thus, if only 14 keys are actually
enabled, only 14 timeslots are used for scanning.
2 Hardware and Functional
2.1 Matrix Scan Sequence
The circuit operates by scanning each key sequentially, key
by key. Key scanning begins with location X=0 / Y=0 (key #0).
X axis keys are known as rows while Y axis keys are referred
to as columns. Keys are scanned sequentially by row, for
example the sequence X0Y0 X1Y0 .... X7Y0, X0Y1, X1Y1...
etc. Keys are also numbered from 0.. .23. Key 0 is located at
X0Y0. Table 4.3, page 12 shows the key numbering.
Each key is sampled in a burst of acquisition pulses whose
length is determined by the Setups parameter BL (page 17),
which can be set on a per-key basis. A burst is completed
entirely before the next key is sampled; at the end of each
burst the resulting signal is converted to digital form and
processed. The burst length directly impacts key gain; each
key can have a unique burst length in order to allow tailoring
of key sensitivity on a key-by-key basis.
2.2 Disabling Keys - Burst Paring
QT60xx0 parts employ transverse charge-transfer ('QT')
sensing, a technology that senses changes in electrical
charge forced across an electrode by a pulse edge
(Figure 1.1). QT60xx0 devices allow a wide range of key sizes
and shapes to be mixed together in a single touch panel.
Keys that are disabled by setting NDIL =0 (Section 6.6, page
16) have their bursts pared from the scan sequence to save
time. This has the consequence of affecting the scan rate of
the entire matrix as well as the time required f or initial matrix
calibration.
The devices use an I2C interface to allow key data to be
extracted and to permit individual key parameter setup. The
command structure is designed to minimize the amount of
data traffic while maximizing the amount of information
conveyed.
Reducing the number of enabled keys also reduces the time
required to calibrate an individual key once the matrix is initially
calibrated after power-up or reset, since the total cycle time is
proportional to the number of enabled keys.
In addition to normal operating and setup functions the device
can also report back actual signal strengths .
QmBtn™ software for the PC can be used to program the
operation of the IC, as well as read back key status and
signal levels in real time.
1.2 Part Differences
The QT60160 and QT60240 are electrically identical, with the
exception of the number of keys which may be sensed.
Versions of the device are capable of a maximum of 16 or 24
keys (QT60160 and QT60240 respectively).
For QT60160, only Y0 and Y1 can be used to determine the
placement of a maximum of 16 keys. For QT60240, Y0, Y1
and Y2 can be used to determine the placement of a
maximum 24 keys.
The length of the setup blocks are different:
•
83 bytes on the QT60160
•
123 bytes on the QT60240
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2.3 Sample Capacitors - Saturation
The charge sampler capacitors on the Y pins should be the
values shown (Figure 2.7, page 9). They should be X7R or
NP0 ceramics or PPS film. The value of these capacitors is
not critical but 4.7nF is recommended for most cases.
Cs voltage saturation is shown in Figure 2.1. This nonlinearity
is caused by excessive negative voltage on Cs inducing
conduction in the pin protection diodes. This badly saturated
signal destroys key gain and introduces a strong thermal
coefficient which can cause 'phantom' detection. The cause of
this is usually from the burst length being too long, the Cs
value being too small, or the X-Y coupling being too large.
Solutions include loosening up the interdigitation of key
structures, separating X and Y lines on the PCB more,
increasing Cs, and decreasing the burst length.
Increasing Cs will make the part slower; decreasing burst
length will make it less sensitive. A better PCB layout and a
looser key structure (up to a point) have no negative effects.
Cs voltages should be observed on an oscilloscope with the
matrix layer bonded to the panel material; if the Rs side of
any Cs ramps more negative than -0.25 volts during any burst
(not counting overshoot spikes which are probe artifacts),
there is a potential saturation problem.
3
Preliminary information; subject to change
QT60240-XSG X7.04/0706
Figure 2.2 shows a defective waveform similar to that of 2.1,
but in this case the distortion is caused by excessive stray
capacitance coupling from the Y line to AC ground . For
example, from running too near and too far alongside a
ground trace, ground plane, or other traces. The excess
coupling causes the charge-transfer effect to dissipate a
significant portion of the received charge from a key into the
stray capacitance. This phenomenon is more subtle; it can be
best detected by increasing BL to a high count and watching
what the waveform does as it descends towards and below
-0.25V. The waveform will appear deceptively straight, but it
will slowly start to flatten even before the -0.25V level is
reached.
A correct waveform is shown in Figure 2.3. Note that the
bottom edge of the bottom trace is substantially straight
(ignoring the downward spikes).
Figure 2.1 VCs - Non-Linear During Burst
(Burst too long, or Cs too small, or X-Y capacitance too large)
Figure 2.2 VCs - Poor Gain, Non-Linear During
Burst
(Excess capacitance from Y line to Gnd)
Unlike other QT circuits, the Cs capacitor values on QT60xx 0
devices have no effect on conversion gain. However , they do
affect conversion time.
Unused Y lines should be left open.
2.4 Sample Resistors
There are three sample resistors (Rs) (two on the QT60160)
used to perform single-slope ADC conversion of the acquired
charge on each Cs capacitor. These resistors directly control
acquisition gain; larger values of Rs will proportionately
increase signal gain. Values of Rs can range from 380K ✡ to
1M✡. 470K✡ is a reasonable value for most purposes.
Figure 2.3 VCs - Correct
Unused Y lines do not require an Rs resistor.
2.5 Signal Levels
Quantum’s QmBtn software makes it is easy to observe the
absolute level of signal received by the sensor on each key.
The signal values should normally be in the range of 250 to
750 counts with properly designed key shapes and values of
Rs. However, long adjacent runs of X and Y lines can also
artificially boost the signal values, and induce signal
saturation; this is to be avoided. The X-to-Y coupling should
come mostly from intra-key electrode coupling, not from stray
X-to-Y trace coupling.
QmBtn software is available free of charge on Quantum’s
website www.qprox.com.
The signal swing from the smallest finger touch should
preferably exceed 10 counts, with 15 being a reasonable
target. The signal threshold setting (NTHR) should be set to a
value guaranteed to be less than the signal swing caused by
the smallest touch.
Figure 2.4 X-Drive Pulse Roll-off and Dwell Time
X drive
Lost charge due to
inadequate settling
before end of dwell time
Dwell time
Y gate
Increasing the burst length (BL) parameter will increase the
signal strengths as will increasing the sampling resistor (Rs)
values.
2.6 Matrix Series Resistors
The X and Y matrix scan lines should use series resistors
(referred to as Rx and Ry respectively) for improved EMI
performance (Figure 2.7, page 9).
X drive lines require them in most cases to reduce edge rates
and thus reduce RF emissions. Typical values range from
1K✡ to 20K✡.
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4
Preliminary information; subject to change
QT60240-XSG X7.04/0706
Figure 2.5 Probing X-Drive Waveforms With a
Coin
Figure 2.6 Recommended Key Structure
‘T’ should ideally be similar to the complete thickness the
fields need to penetrate to the touch surface. Smaller
dimensions will also work but will give less signal strength. If
in doubt, make the pattern coarser.
One way to determine X line settling time is to monitor the
fields using a patch of metal foil or a small coin over the key
(Figure 2.5). Only one key along a particular X line needs to
be observed, as each of the keys along that X line will be
identical. The 375ns dwell time should exceed the observed
95% settling of the X-pulse by 25% or more.
Y lines need them to reduce EMC susceptibility problems and
in some extreme cases, ESD. Typical Y values are about
1K✡. Y resistors act to reduce noise susceptibility problems
by forming a natural low-pass filter with the Cs capacitors.
In almost all case, Ry should be set equal to Rx, which will
ensure that the charge on the Y line is fully captured into the
Cs capacitor.
It is essential that the Rx and Ry resistors and Cs capacitors
be placed very close to the chip. Placing these parts more
than a few millimeters away opens the circuit up for high
frequency interference problems (above 20MHz) as the trace
lengths between the components and the chip start to act as
RF antennae.
2.7 Key Design
The upper limits of Rx and Ry are reached when the signal
level and hence key sensitivity are clearly reduced. The limits
of Rx and Ry will depend on key geometry and stray
capacitance, and thus an oscilloscope is required to
determine optimum values of both.
Dwell time is the duration in which charge coupled from X to
Y is captured. Increasing Rx values will cause the leading
edge of the X pulses to increasingly roll off, causing the loss
of captured charge (and hence loss of signal strength) from
the keys.
The dwell time of these parts is fixed at 375 ns. If the X pulses
have not settled within 375ns, key gain will be reduced; if this
happens, either the stray capacitance on the X line(s) should
be reduced (by a layout change, for example by reducing X
line exposure to nearby ground planes or traces), or, the Rx
resistor needs to be reduced in value (or a combination of
both approaches).
Circuits can be constructed out of a variety of materials
including flex circuits, FR4, and even inexpensive
single-sided CEM-1.
The actual internal pattern style is not as important as the
need to achieve regular X and Y widths and spacings of
sufficient size to cover the desired graphical key area or a
little bit more; ~3mm oversize is acceptable in most cases,
since the key’s electric fields drop off near the edges anyway.
The overall key size can range from 10mm x 10mm up to
100mm x 100mm but these are not hard limits. The keys can
be any shape including round, rectangular, square, etc. The
internal pattern can be as simple as a single bar of Y within a
solid perimeter of X, or (preferably) interdigitated as shown in
Figure 2.6.
For better surface moisture suppression, the outer perimeter
of X should be as wide as possible, and there should be no
ground planes near the keys. The variable ‘T’ in this drawing
represents the total thickness of all materials that the keys
must penetrate.
2.8 PCB Layout, Construction
2.8.1 Overview
It is best to place the chip near the touch keys on the same
PCB so as to reduce X and Y trace lengths, thereby reducing
the chances for EMC problems. Long conn ection traces act
as RF antennae. The Y (receive) lines are much more
susceptible to noise pickup than the X (drive) lines.
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5
Preliminary information; subject to change
QT60240-XSG X7.04/0706
Even more importantly, all signal related discrete parts
(resistors and capacitors) should be very close to the body of
the chip. Wiring between the chip and the various resistors
and capacitors should be as short and direct as possible to
suppress noise pickup.
A single ceramic 0.1uF bypass capacitor should be placed
very close to supply pins 3, 4, 5 and 6 of the IC. Pins 18, 20,
and 21 do not require bypassing.
Vdd can range from +1.8V to +5V nominal.
2.10 Startup / Calibration Times
Ground planes and traces should NOT
be used around the keys and the Y lines
from the keys. Ground areas, traces, and
other adjacent signal conductors that act
as AC ground (such as Vdd and LED drive
lines etc) will absorb the received key signals and
reduce signal-to-noise ratio (SNR) and thus will be
counterproductive. Ground planes around keys will also
make water film effects worse.
Ground planes, if used, should be placed under or around the
QT chip itself and the associated resistors and capacitors in
the circuit, under or around the power supply, and back to a
connector, but nowhere else.
2.8.2 LED Traces and Other Switching Signals
Digital switching signals near the Y lines will induce transients
into the acquired signals, deteriorating the SNR perfomance
of the device. Such signals should be routed away from the Y
lines, or the design should be such that these lines are not
switched during the course of signal acquisition (bursts).
LED terminals which are multiplexed or switched into a
floating state and which are within or physically very near a
key structure (even if on another nearby PCB) should be
bypassed to either Vss or Vdd with at least a 10nF capacitor
of any type, to suppress capacitive coupling effects which can
induce false signal shifts. L ED terminals which are constantly
connected to Vss or Vdd do not need further bypassing.
The devices require initialization times of <1ms. A calibration
takes one matrix scan.
Disabled keys are subtracted from the burst sequence and
thus the cal time is shortened. The scan time should be
measured on an oscilloscope.
2.11 Reset Input
The /RST pin can be used to reset the device to simulate a
power down cycle, in order to bring the part up into a known
state should communications with the part be lost. The pin is
active low, and a low pulse lasting at least 10µs must be
applied to this pin to cause a reset.
The reset pin has an internal 30K✡ - 60K✡ resistor. A 2.2µF
capacitor plus a diode to Vdd can be connected to this pin as
a traditional reset circuit, but this is not required.
If an external hardware reset is not used, the reset pin may
be connected to Vdd or left floating .
2.12 Spread Spectrum Acquisitions
QT60xx0 devices use spread-spectrum burst modulation.
This has the effect of drastically reducing the possibility of
EMI effects on the sensor keys, while simul taneously
spreading RF emissions. This feature is hard-wired into the
device and cannot be disabled or modified.
Spread spectrum is configured as a frequency chirp over a
wide range of frequencies for robust operation.
2.13 Detection Integrators
2.8.3 PCB Cleanliness
See also Section 6.6, page 16.
All capacitive sensors should be treated as highly sensitive
circuits which can be influenced by stray conductive leakage
paths. QT devices have a basic resolution in the femtofarad
range; in this region, there is no such thing as ‘no clean flux’.
Flux absorbs moisture and becomes conductive between
solder joints, causing signal drift and resultant false
detections or transient losses of sensitivity or instability.
Conformal coatings will trap in existing amounts of moisture
which will then become highly temperature sensitive.
The devices feature a detection integration mechanism, which
acts to confirm a detection in a robust fashion. A per-key
counter is incremented each time the key has exceeded its
threshold and stayed there for a number of acquisitions.
When this counter reaches a preset limit the key is finally
declared to be touched.
The designer should specify ultrasonic cleaning as part of the
manufacturing process, and in cases where a high level of
humidity is anticipated, the use of conformal coatings after
cleaning to keep out moisture.
2.9 Power Supply Considerations
As these devices use the power supply itself as an analog
reference, the power should be very clean and come from a
separate regulator. A standard inexpensive Low Dropout
(LDO) type regulator should be used that is not also used to
power other loads such as LEDs, relays, or other high current
devices. Load shifts on the output of the LDO can cause Vdd
to fluctuate enough to cause false detection or sensitivity
shifts.
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For example, if the limit value is 10, then the device has to
exceed its threshold and stay there for 10 acquisitions in
succession without going below the threshold level, before
the key is declared to be touched. If on any acquisition the
signal is not seen to exceed the threshold level, the counter is
cleared and the process has to start from the beginning.
The QT60xx0 uses a two-tier confirmation mechanism having
two such counters for each key. These can be thought of as
‘inner loop’ and ‘outer loop’ confirmation counters.
The ‘inner’ counter is referred to as the ‘fast-DI’; this acts to
attempt to confirm a detection via rapid successive
acquisition bursts, at the expense of delaying the sampling of
the next key. Each key has its own fast-DI counter and limit
value; these limits can be changed via the Setups block on a
per-key basis.
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Preliminary information; subject to change
QT60240-XSG X7.04/0706
The ‘outer’ counter is referred to as the ‘normal-DI’; this DI
counter increments whenever the fast-DI counter has reached
its limit value. If a fast-DI counter failed to reach its terminal
count, the corresponding normal-DI counter is also reset. The
normal-DI counter also has a limit value which is settable on
a per-key basis. If a normal-DI counter reaches its terminal
count, the corresponding key is declared to be touched and
becomes ‘active’. Note that the normal-DI can only be
incremented once per complete keyscan cycle, i .e. more
slowly, whereas the fast-DI is incremented ‘on the spot’
without interruption.
The net effect of this mechanism is a multiplication of the
inner and outer counters and hence a highly noise-resistance
sensing method. If the inner limit is set to 5, and the outer to
3, the net effect is 5x3=15 successive threshold crossings to
declare a key as active.
2.14 Sleep
The device will sleep whenever possible to conserve power.
Periodically, the part will wake automatically, scan the matrix,
and return to sleep unless there is activity which demands
further attention. The part will always return to sleep
automatically once all activity has ceased. The time for which
the part will sleep before automatically awakening can be
configured.
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A new communication with the device while it is asleep will
cause it to wake up, service the communication and scan the
matrix. At least one full matrix scan is always performed after
waking up and before returning to sleep.
At the end of each matrix scan, the part will return to sleep
unless recent activity demands further attention. If there has
been recent activity, the part will perform another complete
matrix scan and then attempt to sleep once again. This
process is repeated indefinitely until the activity stops and the
part returns to sleep.
Key touch activity will prevent the part from sleeping, as will
recent communications by the host. The part will not sleep if
any touch events were detected at any key in the most recent
scan of the key matrix.
A recent communication from the host will also prevent the
part from sleeping. The device tracks the time elapsed since
the last host communication and prevents the part from
sleeping while the elapsed time is less than the ‘Awake
Timeout’; this helps prevent the part from falling asleep part
way through a host communication. The ‘Awake Timeout’ can
be configured.
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Preliminary information; subject to change
QT60240-XSG X7.04/0706
2.15 Wiring
Table 2.1 Pin Listing
Pin
Function
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
M_SYNC
DETECT
Vss
Vdd
Vss
Vdd
X6
X7
LATCH
Vref
S_SYNC
X0
X1
X2
X3
X4
X5
Vdd
A1
Vdd
Vss
A0
Y0B
Y1B
Y2B
SMP
SDA
SCL
/RST
Y0A
Y1A
Y2A
I
O
P
P
P
P
O
O
O
I
O
O
O
O
O
O
O
P
I
P
P
I
I
I
I
O
I/O
I/O
I
I
I
I
lQ
Comments
Mains Sync input
Detect output
Supply ground
Power, +1.8V to +5V
Supply ground
Power, +1.8V to +5V
X matrix drive line
X matrix drive line
Shift Register Latch Output
Ground
Scope Sync: Synchronization test signal
X matrix drive line
X matrix drive line
X matrix drive line
X matrix drive line
X matrix drive line
X matrix drive line
Power, +1.8V to +5V
Com port address 1
Power, +1.8V to +5V
Supply ground
Com port address 0
Y line connection
Y line connection
Y line connection (QT60240 only)
Sample output.
Serial Interface Data
Serial Interface Clock
Reset low; has internal 20K - 100K pullup
Y line connection
Y line connection
Y line connection (QT60240 only)
8
Preliminary information; subject to change
If Unused, Connect To...
Vdd
Leave open
Leave open
Leave open
Leave open
Leave open
Leave open
Leave open
Leave open
Leave open
Leave open
Leave open
Leave open
Leave open
Leave open
Leave open or Vdd
Leave open
Leave open
Leave open
QT60240-XSG X7.04/0706
Figure 2.7 Wiring Diagram
See Table 2.1 for further connection information.
VDD
+1.8V to +5V
VREG
Vunreg
*RX6
1K
VDD
10K
10K
QT60240
QT60160
1K
*RX3
*RX4
1K
*RX2
1K
I2C
*RX5
1K
SDA
*RX1
1K
SCL
1K
MATRIX X DRIVE
*RX7
follow regulator manufacturers
recommended values for input and
output bypass capacitors; keep output
capacitor close to QT60xx0 pin 4 and 6.
If not possible, add a 100nF capacitor
next to those pins.
*RX0
1K
DETECT
MAINS SYNC
**RY0
SCOPE SYNC
1K
CS0
4.7nF
**RY1
1K
CS1
Note
4.7nF
1K
Note
CS2
lQ
**RY2
MATRIX Y SCAN IN
* optional - for emission suppression
** optional - for RF susceptibility improvement
LATCH
RS2
RS1
RS0
1M
1M
1M
9
Preliminary information; subject to change
4.7nF
Note: Leave Y2A, Y2B unconnected
for QT60160
QT60240-XSG X7.04/0706
3 Interfaces
The shift register data is output over the duration of a matrix
scan, as each key is being processed, and it is latched at the
end of the scan. The overall communication time depends on
the matrix scan time.
3.1 Introduction
The QT60xx0 can be configured to communicate either over
an I2C bus or a shift register type SPI. See Table 3.1 for
interface details.
Table 3.1 Interface Details
A1
Vss
Vss
Vdd
Vdd
A0
Vss
Vdd
Vss
Vdd
Interface
Shift Register
I2C Address 7
I2C Address 17
I2C Address 117
Pin 2 (DETECT) is a push-pull output and can be used in
conjunction with the I 2C interface to alert the host to key
touches. Every key can be configured to wake the host. This
output is set active when any key configured so confirms a
touch. The device will also set this output active to keep the
host advised of touch changes on any key if the host is
keeping the device awake by communicating. Pin 2 is set
inactive when the host performs a read from any location. Pin
2 is active high (Vdd) to alert the host. This output is useful
with the I2C interface only and should be ignored if the Shift
Register interface is selected.
Table 3.2 Shift Register
Parameter
SCL pulse width
LATCH pulse width
SDA data to SCL clock hold time
Units
250ns min
250ns min
250ns min
3.3 I2C Port
These devices use I2C communications, in slave mode only.
The QT60160/60240 will only respond to the correct address
match. I2C operating parameters are as follows:
Max Data Transfer:
Address:
100KHz
7-bit
The match address is selected via pins A0 and A1. Table 3.1
shows the address map.
3.2 Shift Register Output
The QT60160/60240 allows multiple byte transmissions to
provide a more efficient communication. This is particularly
useful to retrieve several information bytes at once. Every
time the host retrieves data from the QT60 160/60240, the
internal address is incremented.
When the option jumpers are both set at Vss, the device
disables the I 2C interface and instead generates output
suitable for driving a shift register.
Therefore, the host only needs to write the initial address of
interest (the lowest address), followed by read cycles for as
many bytes as required.
The shift register data is output at pin 27 (SDA). The clock is
output at pin 28 (SCL). The data is clocked on the
positive-going transition of SCL. Data is transferred from the
shift registers to the latched outputs on the positive-going
transition of LATCH. An example shift register connection is
shown in Figure 3.1.
Figure 3.1 Shift Register Output
74HC595
QT60240
SDA
SCL
Latch
74HC595
Q0
27
28
9
Q2
DS
Q3
SH_CP Q4
ST_CP Q5
Q6
Q7
QT60160
Outputs, keys 16 to 23
SDA
SCL
Latch
Q0
27
28
9
Q2
DS
Q3
SH_CP Q4
ST_CP Q5
Q6
Q7
/Q7
/Q7
74HC595
74HC595
Q0
Q2
DS
Q3
SH_CP Q4
ST_CP Q5
Q6
Q7
Outputs, keys 8 to 15
Q0
Outputs, keys 8 to 15
DS
ST_CP
/Q7
Q2
Q3
SH_CP Q4
Outputs, keys 0 to 7
Q5
Q6
Q7
/Q7
74HC595
Q0
Q2
DS
Q3
SH_CP Q4
ST_CP Q5
Q6
Q7
Outputs, keys 0 to 7
/Q7
lQ
10
Preliminary information; subject to change
QT60240-XSG X7.04/0706
4 Control Commands
4.1 Introduction
The devices feature a set of commands which are used for
control and status reporting.
As well as Tables 4.1 and 4.2, refer to Table 6.1, page 19 and
Table 6.2, page 20 for further details.
Table 4.1 Memory Map for QT60160
Address
0
1
2
4 to 84
125
130
131 to
213
Use
Part Revision
Detect status for keys 0 to 7, one bit
per key
Detect status for keys 8 to 15, one bit
per key
Data for keys 0 to 15, in sequence.
Refer to Table 4.4 for details
Recalibrate all keys. Write 0x55 to
this address location to recalibrate all
the keys
Setups write-unlock. Write 0x55
immediately before writing setups
Setups - refer to Table 5.1 for details
Access
Read
Read
Read
Read
Write
2
3
4 to 124
125
130
131 to
253
Use
Part Revision
Detect status for keys 0 to 7, one bit
per key
Detect status for keys 8 to 15, one bit
per key
Detect status for keys 16 to 23, one
bit per key
Data for keys 0 to 23, in sequence.
Refer to Table 4.4 for details
Recalibrate all keys. Write 0x55 to
this address location to recalibrate all
the keys
Setups write-unlock. Write 0x55
immediately before writing setups
Setups - refer to Table 5.2 for details
Read/Write
Access
Read
Read
Read
Read
Write
Write
Read/Write
The sequence of events required to write data to the device is
shown next.
S
SLA+W
A
Key
S
SLA+W
A
MemAddress
Data
P
MemAddress
Device Tx to Host
A
Data
A
Start condition
Slave address plus write bit
Acknowledge bit
Target memory address within
device
Data to be written
Stop condition
lQ
The host should not try to write beyond address 255 because
the device will not increment the internal memory address
beyond this.
4.3 Reading Data From the Device
The sequence of events required to read data from the device
is shown next.
Host to Device
S
SLA+W
A
Data 1
A
P
Device Tx to Host
MemAddress A P
Data 2
Key
S
SLA+W
A
MemAddress
Read
4.2 Writing Data to the Device
Host to Device
If the host sends more than one data byte, they will be written
to consecutive memory addresses. The device automatically
increments the target memory address after writing each data
byte. After writing the last data byte, the host should send the
STOP condition.
Write
Table 4.2 Memory Map for QT60240
Address
0
1
The host initiates the transfer by sending the START
condition, and follows this by sending the slave address of
the device together with the Write-bit. The device sends an
ACK. The host then sends the memory address within the
device it wishes to write to. The device sends an ACK. The
host transmits one or more data bytes; each will be
acknowledged by the device.
Data
P
SLA+R
/A
A
S
SLA+R
A
Data n
/A P
Start condition
Slave address plus write bit
Acknowledge bit
Target memory address within
device
Data from device
Stop condition
Slave address plus read bit
Not Acknowledge bit/indicates
last byte transmission
The host initiates the transfer by sending the START
condition, and follows this by sending the slave address of
the device together with the Write-bit. The device sends an
ACK. The host then sends the memory address within the
device it wishes to read from. The device sends an ACK.
The host must then send a STOP and a START condition
followed by the slave address again but this time
accompanied by the Read-bit. The device will return an ACK,
followed by a data byte. The host must return either an ACK
or NACK. If the host returns an ACK, the device will
subsequently transmit the data byte from the next address.
Each time a data byte is transmitted, the device automatically
increments the internal address. The device will continue to
return data bytes until the host responds with a NACK. The
host should terminate the transfer by issuing the STOP
condition.
4.4 Report Detections for All Keys
Address 1: detect status for keys 0 to 7
Address 2: detect status for keys 8 to 15
Address 3: detect status for keys 16 to 23 (QT60240 only)
Each location indicates all keys in detection, if any, as a
bitfield; active keys report as 1’s, disabled keys report as
inactive (0).
11
Preliminary information; subject to change
QT60240-XSG X7.04/0706
Table 4.3 Bits for Key Reporting and Numbering
Address
1
2
3
7
7
15
23
6
6
14
22
Bit Number
5
4
3
2
5
4
3
2
13
12
11
10
21
20
19
18
1
1
9
17
0
0
8
16
4.6 Cal All
A value of 0x55 must be written to the address 125. Upon
receiving this command the QT60xx0 will recalibrate all of the
keys. Recalibration will start at the beginning of the next full
matrix scan. The device will not sleep during the calibration
period.
4.7 Setups
4.5 Raw Data Commands
Addresses 4 to 84 inclusive for the QT60160 and 4 to 124 for
the QT60240 allow data to be read for each key. The
QT60160 has a total of 16 keys and 5 bytes of data per key,
yielding a total of 80 addresses . The QT60240 has a total of
24 keys and 5 bytes of data per key, yielding a total of 120
addresses. These addresses are read-only.
The data for the keys is mapped in sequence, starting with
key 0 at addresses 4 to 8. The data for key 15 is located at
addresses 80 to 84, and that for key 23 is located at
addresses 120 to 124. Table 4.4 summarizes this.
There are five bytes of data for each key. The first two are the
key’s 16-bit signal, and the second two are the key’s 16-bit
reference. These are followed by the Detect Integrator Count,
which is a 4-bit value stored in the lower nibble. In the case of
both the signal and reference, the 16-bit values are accessed
as two 8-bit bytes, stored LSB first.
The location “Setups write-unlock”, address 130, allows write
access to the setups. Normally the setups are write-protected;
the write protection is engaged as soon as a read operation is
performed at any address. By writing a value of 0x55 to this
address, the write-protection is disengaged. This address is
located conveniently immediately before the setups so that
the write protection may be disengaged and the setups
written in a single I 2C communication sequence. Reading this
address is undefined.
Addresses 131 to 212 on the QT60160 and addresses 131 to
252 on the QT60240 provide read/write access to the setups.
Details of different setups can be found in Section 5.
When the host is writing a new setup block the values are
being recorded into EEPROM as they arrive from the host.
Table 4.4 Key Data
Address
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 to 119
120
121
122
123
124
Key #
0
0
0
0
0
1
1
1
1
1
2
2
2
2
2
3 to 22
23
23
23
23
23
lQ
Use
Signal LSB
Signal MSB
Reference LSB
Reference MSB
DetectCount (lower nibble)
Signal LSB
Signal MSB
Reference LSB
Reference MSB
DetectCount (lower nibble)
Signal LSB
Signal MSB
Reference LSB
Reference MSB
DetectCount (lower nibble)
Range of values
Signal LSB
Signal MSB
Reference LSB
Reference MSB
DetectCount (lower nibble)
12
Preliminary information; subject to change
QT60240-XSG X7.04/0706
5 I2C Operation
5.3 START and STOP Conditions
5.1 Interface Bus
More detailed information about I 2C is available from
www.i2C-bus.org. Devices are connected onto the I 2C bus as
shown in Figure 5.1. Both bus lines are connected to V dd via
pull-up resistors. The bus drivers of all I 2C devices must be
open-drain type. This implements a wired-AND function which
allows any and all devices to drive the bus, one at a time. A
low level on the bus is generated when a device outputs a
zero.
The host initiates and terminates a data transmission. The
transmission is initiated when the host issues a START
condition on the bus, and is terminated when the host issues
a STOP condition. Between START and STOP conditions, the
bus is considered busy. As shown below, START and STOP
conditions are signaled by changing the level of the SDA line
when the SCL line is high.
Figure 5.3 START and STOP Conditions
Figure 5.1 I2C Interface Bus
SDA
Vcc
SCL
Device 1
Device 2
Device 3
Device n
R1
R2
START
SDA
STOP
5.4 Address Packet Format
SCL
Table 5.1 I2C Bus Specifications
Parameter
Unit
Address space
Maximum bus speed (SCL)
Hold time START condition
Setup time for STOP condition
Bus free time between a STOP and START
condition
7-bit
100 kHz
4µs min.
4µs min.
4.7µs min.
All address packets are 9 bits long, consisting of 7 address
bits, one READ/WRITE control bit and an acknowledge bit. If
the READ/WRITE bit is set, a read operation is performed,
otherwise a write operation is performed. When the device
recognizes that it is being addressed, it will acknowledge by
pulling SDA low in the ninth SCL (ACK) cycle. An address
packet consisting of a slave address and a READ or a
WRITE bit is called SLA+R or SLA+W, respectively.
The most significant bit of the address byte is transmitted
first. The address sent by the host must be consistent with
that selected with the option jumpers.
Figure 5.4 Address Packet Format
Addr MSB
5.2 Transferring Data Bits
Each data bit transferred on the bus is accompanied by a
pulse on the clock line. The level of the data line must be
stable when the clock line is high; The only exception to this
rule is for generating start and stop conditions.
Figure 5.2 Data Transfer
Addr LSB
R/W
ACK
7
8
9
SDA
SCL
1
2
START
5.5 Data Packet Format
SDA
SCL
Data Stable
Data Stable
All data packets are 9 bits long, consisting of one data byte
and an acknowledge bit. During a data transfer, the host
generates the clock and the START and STOP conditions,
while the Receiver is responsible for acknowledging the
reception. An acknowledge (ACK) is signaled by the Receiver
pulling the SDA line low during the ninth SCL cycle. If the
Receiver leaves the SDA line high, a NACK is signaled.
Data Change
lQ
13
Preliminary information; subject to change
QT60240-XSG X7.04/0706
5.6 Combining Address and Data Packets
Into a Transmission
A transmission consists of a START condition, an SLA+R/W,
one or more data packets and a STOP condition. The
wired-ANDing of the SCL line is used to implement
handshaking between the host and the device. The device
extends the SCL low period by pulling the SCL line low
whenever it needs extra time for processing between the data
transmissions.
Figure 5.6 shows a typical data transmission. Note that
several data bytes can be transmitted between the SLA +R/W
and the STOP.
Figure 5.5 Data Packet Format
Data MSB
Data LSB
ACK
Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
1
2
SLA+R/W
7
Data Byte
8
9
STOP,
or
Next Data Byte
Figure 5.6 Packet Transmission
Addr MSB
Addr LSB
R/W
ACK
Data MSB
7
8
9
1
Data LSB
ACK
8
9
SDA
SCL
1
2
START
lQ
SLA+R/W
2
7
Data Byte
14
Preliminary information; subject to change
STOP
QT60240-XSG X7.04/0706
6 Setups
6.3 Positive Threshold - PTHR
The positive threshold is used to provide a mechanism for
recalibration of the reference point when a key's signal
moves abruptly to the positive. This condition is not
normal, and usually occurs only after a recalibration when
an object is touching the key and is subsequently removed.
The desire is normally to recover from these events
quickly.
6.1 Introduction
The devices calibrate and process all signals using a
number of algorithms specifically designed to provide for
high survivability in the face of adverse environmental
challenges. They provide a large number of processing
options which can be user-selected to implement very
flexible, robust keypanel solutions.
Positive hysteresis: PHYST is fixed at 12.5% of the
positive threshold value and cannot be altered.
User-defined Setups are employed to alter these
algorithms to suit each application. These setups are
loaded into the device over the I 2C serial interfaces. The
Setups are stored in an onboard EEPROM array.
Positive threshold levels are all fixed at 6 counts of signal
and cannot be modified.
Many setups employ lookup-table value translation.
Table 6.3, the Setups Lookup Table on page 21 shows all
translation values. The default values are the factory
defaults.
Refer to Table 6.1, page 19 and Table 6.2, page 20 for all
Setups.
6.2 Negative Threshold - NTHR
The negative threshold value is established relative to a
key’s signal reference value. The threshold is used to
determine key touch when crossed by a negative-going
signal swing after having been filtered by the detection
integrator. Larger absolute values of threshold desensitize
keys since the signal must travel farther in order to cross
the threshold level. Conversely, lower thresholds make
keys more sensitive.
As Cx and Cs drift, the reference point drift-compensates
for these changes at a user-set table rate; the threshold
level is recomputed whenever the reference point moves,
and thus it also is drift compen sated.
The amount of NTHR required depends on the amount of
signal swing that occurs when a key is touched. Thicker
panels or smaller key geometries reduce ‘key gain’, i .e.
signal swing from touch, thus requiring smaller NTHR
values to detect touch.
6.4 Positive Recalibration Delay - PRD
A recalibration occurs automatically if the signal swings
more positive than the positive threshold level. This
condition can occur if there is positive drift but insufficient
positive drift compensation , or, if the reference moved
negative due to a NRD auto-recalibration, and thereafter
the signal rapidly returned to normal (positive excursion).
As an example of the latter, if a foreign object or a finger
contacts a key for period longer than the Negative Recal
Delay (NRD), the key is by recalibrated to a new lower
reference level. Then, when the condition causing the
negative swing ceases to exist (e.g. the object is removed)
the signal suddenly swings positive to its normal reference.
It is almost always desirable in these cases to cause the
key to recalibrate quickly so as to restore normal touch
operation. The time required to do this is governed by
PRD. In order for this to work, the signal must rise through
the positive threshold level PTHR continuously for the PRD
period.
After the PRD interval has expired and the autorecalibration has taken place, the affected key will once
again function normally. PRD is fixed at 1 second for all
keys, and cannot be altered.
PRD Accuracy:
to within ± 50ms
The negative threshold is programmed on a per-key basis
using the Setup process. See Table 6.3, page 21.
Negative hysteresis: NHYST is fixed at 12.5% of the
negative threshold value and cannot be altered .
Typical values:
3 to 8
(7 to 12 counts of threshold; 4 is internally added to
NTHR to generate the threshold).
Default value:
6
(10 counts of threshold)
Figure 6.1 Thresholds and Drift Compensation
Reference
Hysteresis
Threshold
Signal
Output
lQ
15
QT60240-XSG X7.04/0706
Preliminary information; subject to change
6.5 Drift Compensation - NDRIFT, PDRIFT
Signals can drift because of changes in Cx and Cs over
time and temperature. It is crucial that such drift be
compensated, else false detections and sensitivity shifts
can occur.
Drift compensation (Figure 6.1) is performed by making the
reference level track the raw signal at a slow rate, but only
while there is no detection in effect. The rate of adjustment
must be performed slowly, otherwise legitimate detections
could be ignored. The devices drift compensate using a
slew-rate limited change to the reference level; the
threshold and hysteresis values are slaved to this
reference.
To suppress false detections caused by spurious events
like electrical noise, the device incorporates a 'detection
integrator' or DI counter mechanism that acts to confirm a
detection by consensus (all detections in sequence must
agree). The DI mechanism counts sequential detections of
a key that appears to be touched, after each burst for the
key. For a key to be declared touched, the DI mechanism
must count to completion without even one detection
failure.
When a finger is sensed, the signal falls since the human
body acts to absorb charge from the cross-coupling
between X and Y lines. An isolated, untouched foreign
object (a coin, or a water film) will cause the signal to rise
very slightly due to an enhancement of coupling. This is
contrary to the way most capacitive sensors operate.
The DI mechanism uses two counters. The first is the ‘fast
DI’ counter FDIL. When a key’s signal is first noted to be
below the negative threshold, the key enters ‘fast burst’
mode. In this mode the burst is rapidly repeated for up to
the specified limit count of the fast DI counter. Each key
has its own counter and its own specified fast-DI limit
(FDIL), which can range from 1 to 15. When fast-burst is
entered the QT device locks onto the key and repeats the
acquire burst until the fast-DI counter reaches FDIL, or, the
detection fails beforehand. After this the device resumes
normal keyscanning and goes on to the next key.
Once a finger is sensed, the drift compensation
mechanism ceases since the signal is legitimately
detecting an object. Drift compensati on only works when
the signal in question has not crossed the neg ative
threshold level.
The ‘Normal DI’ counter counts the number of times the
fast-DI counter reached its FDIL value. The Normal DI
counter can only increment once per complete scan of all
keys. Only when the Normal DI counter reaches NDIL does
the key become formally ‘active’.
The drift compensation mechanism can be asymmetric; the
drift-compensation can be made to occur in one direction
faster than it does in the other simply by changing the
NDRIFT and PDRIFT Setup parameters. This can be done
on a per-key basis.
The net effect of this is that the sensor can rapidly lock
onto and confirm a detection with many confirmations,
while still scanning other keys. The ratio of ‘fast’ to ‘normal’
counts is completely user-settable via the Setups process.
The total number of required confirmations is equal to FDIL
times NDIL.
Specifically, drift compensation should be set to compensate
faster for increasing signals than for decreasing signals.
Decreasin g signals should not be compensated quickly,
since an approaching finger could be compensated for
partially or entirely before even touching the touch pad.
However, an obstruction over the sense pad, for which the
sensor has already made full allowance, could suddenly be
removed leaving the sensor with an artificially suppressed
reference level and thus become insensitive to touch. In
this latter case, the sensor should compensate for the
object's removal by raising the reference level relatively
quickly.
Drift compensation and the detection time-outs work
together to provide for robust, adaptive sensing. The
time-outs provide abrupt changes in reference calibration
depending on the duration of the signal 'event'.
If FDIL = 5 and NDIL = 2, the total detection confirmations
required is 10, even though the device only scanned
through all keys only twice.
The DI is extremely effective at reducing false detections at
the expense of slower reaction times. In some applications
a slow reaction time is desirable . The DI can be used to
intentionally slow down touch response in order to require
the user to touch longer to operate the key.
If FDIL = 1, the device functions conventionally . Each
channel acquires only once in rotation , and the normal
detect integrator counter (NDIL) operates to confirm a
detection. Fast-DI is in essence not operational.
If FDIL m 2, then the fast-DI counter also operates in
addition to the NDIL counter.
NDRIFT Typical values:
9 to 11
(2 to 3.3 seconds per count of drift compensation)
NDRIFT Default value:
10
(2.5s / count of drift compensation)
PDRIFT Typical values:
3 to 5
(0.4 to 0.8 seconds per count of drift compensation;
translation via LUT, page )
PDRIFT Default value:
4
(0.6s / count of drift compensation)
If Signal [ NTHR: The fast-DI counter is incremented
towards FDIL due to touch.
6.6 Detect Integrators - NDIL, FDIL
NDIL Typical values:
NDIL Default value:
FDIL Typical values:
FDIL Default value:
NDIL is used to enable or disable keys and to provide
signal filtering. To enable a key, its NDIL parameter should
be nonzero (ie NDIL=0 disables a key). See Section 2.2.
lQ
If Signal >NTHR then the fast-DI counter is cleared due to
lack of touch.
Disabling a key: If NDIL =0, the key becomes disabled.
Keys disabled in this way are pared from the burst
sequence in order to improve sampling rates and thus
response time. See Section 2.2, page 3.
2, 3
2
4 to 6
5
16
QT60240-XSG X7.04/0706
Preliminary information; subject to change
6.7 Negative Recal Delay - NRD
6.9 Adjacent Key Suppression - AKS
If an object unintentionally contacts a key resulting in a
detection for a prolonged interval it is usually desirable to
recalibrate the key in order to restore its function , perhaps
after a time delay of some seconds.
These devices incorporate adjacent key suppression
(‘AKS’ - patent pending) that can be selected on a per-key
basis. AKS permits the suppression of multiple key
presses based on relative signal strength. This feature
assists in solving the problem of surface moisture which
can bridge a key touch to an adjacent key, causing multiple
key presses. This feature is also useful for panels with
tightly spaced keys, where a fingertip might in advertently
activate an adjacent key.
The Negative Recal Delay timer monitors such detections;
if a detection event exceeds the timer's setting, the key will
be automatically recalibrated. After a recalibration has
taken place, the affected key will once again function
normally even if it is still being contacted by the foreign
object. This feature is set on a per-key basis using the
NRD setup parameter.
NRD can be disabled by setting it to zero (infinite timeout)
in which case the key will never auto-recalibrate during a
continuous detection (but the host could still command it).
NRD is set using one byte per key, which can range in
value from 0...254. NRD above 0 is expressed in 0.5s
increments. Thus if NRD =120, the timeout value will
actually be 60 seconds. 255 is not a legal number to use.
NRD Typical values:
NRD Default value:
NRD Range:
NRD Accuracy:
20 to 60 (10 to 30 seconds)
20 (10 seconds)
0..254 (∞, 0.5...127s)
to within ± 250ms
6.8 Burst Length - BL
The signal gain for each key is controlled by circuit
parameters as well as the burst length.
The burst length is simply the number of times the
charge-transfer (‘QT’) process is performed on a given key.
Each QT process is simply the pulsing of an X line once,
with a corresponding Y line enabled to capture the
resulting charge passed th rough the key’s capacitance Cx.
QT60xx0 devices use a fixed number of QT cycles which
are executed in burst mode. There can be up to 64 QT
cycles in a burst, in accordance with the list of permitted
values shown in Table 6.3, page 21.
Increasing burst length directly affects key sensitivity. This
occurs because the accumulation of charge in the charge
integrator is directly linked to the burst length. The burst
length of each key can be set indiv idually, allowing for
direct digital control over the signal gains of each key
individually.
Apparent touch sensitivity is also controlled by the
Negative Threshold level (NTHR). Burst length and NTHR
interact; normally burst lengths should be kept as short as
possible to limit RF emissions, but NTHR should be kept
above 6 to reduce false detections due to external noise.
The detection integrator mechanism also helps to prevent
false detections.
BL Typical values:
BL Default value:
BL Possible values:
2, 3 (48, 64 pulses / burst)
2 (48 pulses / burst)
0, 1, 2, 3 (16, 32, 48, 64
pulses/burst)
AKS works for keys that are AKS-enabled anywhere in the
matrix and is not restricted to physically adjacent keys; the
device has no knowledge of which keys are actually
physically adjacent. When enabled for a key, adjacent key
suppression causes detections on that key to be
suppressed if any other AKS-enabled key in the panel has
a more negative signal deviation from its reference.
This feature does not account for varying key gains (burst
length) but ignores the actual negative detection threshold
setting for the key. If AKS-enabled keys in a panel have
different sizes, it may be necessary to reduce the gains of
larger keys relative to smaller ones to equalize the effects
of AKS. The signal threshold of the larger keys can be
altered to compensate for this without causing problems
with key suppression.
Adjacent key suppression works to augment the natural
moisture suppression of narrow gated transfer switches
creating a more robust sensing method.
AKS Default value:
0 (Off)
6.10 Oscilloscope Sync - SSYNC
Pin 11 (S_SYNC) can output a positive pulse oscilloscope
sync that brackets the burst of a selected key. More than one
burst can output a sync pulse as determined by the Setups
parameter SSYNC for each key.
This feature is invaluable for diagnostics; without it,
observing signals clearly on an oscilloscope for a particular
burst is very difficult.
This function is supported in Quantum’s QmBtn PC software.
SSYNC Default value:
0 (Off)
6.11 Mains Sync - MSYNC
The Mains Sync feature uses M_SYNC pin 1.
External fields can cause interference leading to false
detections or sensitivity shifts. Most fields come from AC
power sources. RFI noise sources are heavily suppressed
by the low impedance nature of the QT circuitry itsel f.
Noise such as from 50Hz or 60Hz fields becomes a
problem if it is uncorrelated with acquisition signal
sampling; uncorrelated noise can cause aliasing effects in
the key signals. To suppress this problem the M_SYNC
input allows bursts to synchronize to the noise source.
The noise synchronization operating mode is set by
parameter MSYNC in Setups.
The synchronization occurs only at the burst for the lowest
numbered enabled key in the matrix. The device waits for
the synchronization signal for up to 100ms after the end of
a preceding full matrix scan, then when a negative
synchronization edge is received, the matrix is scanned in
its entirety again.
lQ
17
QT60240-XSG X7.04/0706
Preliminary information; subject to change
The sync signal drive should be a buffered logic signal, or
perhaps a diode-clamped signal, but never a raw AC signal
from the mains. The device will synchronize to the falling
edge.
6.14 Awake Timeout - AWAKE
Since Noise synchronization is highly effective and
inexpensive to implement, it is strongly advised to take
advantage of it anywhere there is a possibility of
encountering low frequency (i.e. 50/60Hz) electric fields.
Quantum’s QmBtn software can show such noise effects
on signals, and will hence assist in determining the need to
make use of this feature.
If the I2C interface is selected, a recent communication
from the host will prevent the part from sleeping. The
device tracks the time elapsed since the last host
communication and prevents the part from sleeping while
the elapsed time is less than the 'Awake Timeout'; this
helps prevent the part from falling asleep partway through
a host communication. In other words, the Awake Timeout
interval defines the minimum period since the last
communication before the part will automatically return to
sleep.
If the synchronization feature is enabled but no
synchronization signal exists, the sensor will continue to
operate but with a delay of 100ms before the start of each
matrix scan, and hence will have a slow response time. All
synchronization signals are ignored during sleep.
SYNC Default value:
SYNC Possible range:
0 (Off)
0, 1 (Off, On)
6.12 Sleep Duration - SLEEP
The QT60xx0 is designed to sleep as much as possible to
conserve power. Periodically, the part wakes automatically,
scans the keyboard matrix and then returns to sleep. The
length of time the part sleeps before automatically waking
up can be configured to one of eight different values, via a
look-up table. The look-up table index must be written to
the setups (see Table 6.3, page 21).
SLEEP default value:
SLEEP range:
3 (125ms)
0...7 (16ms...2s)
6.13 Wake on Key Touch - WAKE
The device can be configured for wakeup when specific
keys are touched. Each key has its own configuration bit
so that any combination of keys can be configured for this
purpose. The behavior is different depending on the
selected interface.
When the I 2C interface is selected, the part will set the
detect output when a key with WAKE option enabled
confirms a touch.
With the shift register interface selected, touches on keys
with WAKE option enabled prolong the period the part
remains awake before automatically returning to sleep.
This results in a fast response time to subsequent key
touches once the part has detected the first key touch after
waking up.
After each matrix scan, the part will automatically go to
sleep whenever possible, to conserve power, but the
awake timeout can be used to force the part to stay awake.
A touch on a key marked to self-wake will cause the part to
remain awake for a longer period than would otherwise be
the case. The part then has a much faster key response
time because it continually scans the matrix rather than
returning to sleep immediately after the key touch has
finished. Subsequent key touches further prolong the
awake time. In other words, once the part has been woken
by touching a wake key, the key response time will be fast
while the keyboard is in use. Once key touches have
finished and there have been no key touches for the
Awake Timeout, the part will return to sleep.
The awake period can be configured to a value between
100ms and 25.5s, in increments of 100ms.
AWAKE default value:
25 (2.5s)
AWAKE range:
1...255 (100ms...25.5s)
AWAKE Timeout accuracy: to within ±50ms
6.15 Drift Hold Time - DHT
Drift Hold Time (DHT) is used to restrict drift on all keys
when one or more keys are activated. DHT also defines
the length of time the drift is halted after a key detection.
This feature is particularly useful in cases of high-density
keypads where touching a key or hovering a finger over the
keypad would cause keys to drift, and therefore create
sensitivity shift, and ultimately inhibit detection.
The DHT can be configured to a value of between 100ms
and 25.5s, in increments of 100ms. Setting this parameter
to 0 will disable this feature and the drift compensation on
any key will not be dependent on the state of other keys.
DHT default value:
DHT range:
10 (1s)
0...255 (Off, 100ms...25.5s)
The time the part will remain awake after each key touch
can be configured (see 6.14. All keys prolong the time the
part remains awake once a key confi gured with the WAKE
option has confirmed detect.
WAKE Default value:
WAKE Possible range:
lQ
1 (On)
0, 1 (Off, On)
18
QT60240-XSG X7.04/0706
Preliminary information; subject to change
6.16 Setups Block
Setups data is sent from the host to the QT using the I 2C interface. The setups block is memory mapped onto this interface. Thus each setup can be accessed by
reading/writing the appropriate address. Setups can be accessed individually or as a block. Before writing to any setup, an unlock code (value 0x55) must be written to the
setups write unlock address (130). Refer also to Table 6.3, page 21 for further details, and all of Section 6.
Table 6.1 QT60160 Setups Table
(see next page for QT60240)
Item Address
Bytes
Parameter
Bits
Key
Scope
Default
Value
NTHR NTHR = 0...15
NDRIFT NDRIFT = 0...15
4
4
1
1
6
10
Lower nibble = Neg Threshold - take operand and add 4 to get value
Upper nibble = Neg Drift comp - via LUT (Table 6.3, page 21)
15
16
PDRIFT PDRIFT = 0...15
4
1
4
Upper nibble = Pos Drift comp - via LUT (Table 6.3, page 21)
16
Symbol
Valid Range
Description
Page
1
131...146
16
Neg thresh
Neg Drift Comp
2
147...162
16
Pos Drift Comp
3
163...178
16
Normal DI Limit
Fast DI Limit
NDIL
FDIL
NDIL = 0...15
FDIL = 0...15
4
4
1
1
2
5
Lower nibble = Normal DI Limit, values same as operand (0 = disabled burst)
Upper nibble = Fast DI Limit, values same as operand (0 invalid)
16
4
179...194
16
Neg recal delay
NRD
0...254
8
1
20
Range is in 0.5 sec increments; 0 = infinite; default = 10s
Range is { infinite, 0.5...127s }; 255 is illegal to use
17
WAKE
BL
AKS
SSYNC
WAKE = 0,1
BL = 0..3
AKS = 0,1
SSYNC = 0,1
1
2
1
1
1
1
1
1
0
2
0
0
Bit 3 = WAKE, 1 - enabled
Bits 5, 4: = BL, via LUT (Table 6.3, page 21), default = 48
Bit 6 = AKS, 1 = enabled
Bit 7 = Scope sync, 1 = enabled
18
17
17
17
5
195...210
16
Wake On Touch
Burst Length
AKS
Scope Sync
6
211
1
Sleep Duration
Mains Sync
SLEEP SLEEP = 0...7
MSYNC MSYNC = 0,1
3
1
16
16
3
0
Bits 2,1,0 = Sleep Duration, via LUT (Table 6.3, page 21), default = 125ms
Bits 6 = Mains sync, negative edge, 1 = enabled; default = off
18
17
7
212
1
Awake Timeout
AWAKE
1...255
8
16
25
Range is in 100ms increments; 1 = 100ms. Default = 2.5s. 0 is illegal to use
18
8
213
1
Drift Hold Time
DHT
0...255
8
16
10
Range is in 100ms increments; 0 = disable, 1 = 100ms, default = 1s
18
lQ
19
Preliminary information; subject to change
QT60240-XSG X7.04/0706
Table 6.2 QT60240 Setups Table
(see prior page for QT60160)
Bits
Key
Scope
Default
Value
NThr = 0...15
NDrift = 0...15
4
4
1
1
6
10
Lower nibble = Neg Threshold - take operand and add 4 to get value
Upper nibble = Neg Drift comp - via LUT (Table 6.3, page 21)
15
16
PDrift = 0...15
4
1
4
Upper nibble = Pos Drift comp - via LUT (Table 6.3, page 21)
16
NDIL
FDIL
Ndil = 0...15
FDil = 0...15
4
4
1
1
2
5
Lower nibble = Normal DI Limit, values same as operand (0 = disabled burst)
Upper nibble = Fast DI Limit, values same as operand (0 does not work)
16
Neg recal delay
NRD
0...254
8
1
20
Range is in 0.5 sec increments; 0 = infinite; default = 10s (operand = 20)
Range is { infinite, 0.5...127s }; 255 is illegal to use
17
WAKE
BL
AKS
SSYNC
WAKE = 0,1
BL = 0...3
AKS = 0,1
SSYNC = 0,1
1
2
1
1
1
1
1
1
0
2
0
0
Bit 3 = WAKE, 1 - enabled
Bits 5, 4: = BL, via LUT (Table 6.3, page 210), default = 48 (setting =2)
Bit 6 = AKS, 1 - enabled
Bit 7 = Scope sync, 1 = enabled
18
17
17
17
Item
Address
Bytes
Parameter
Symbol
1
131...154
24
Neg thresh
Neg Drift Comp
NTHR
NDRIFT
2
155...178
24
Pos Drift Comp
PDRIFT
3
179...202
24
Normal DI Limit
Fast DI Limit
4
203...226
24
Valid Range
Description
Page
5
227...250
24
Wake On Touch
Burst Length
AKS
Scope Sync
6
251
1
Sleep Duration
Mains Sync
SLEEP
MSYNC
SLEEP = 0...7
Msync = 0,1
3
1
24
24
3
0
Bits 2,1,0 = Sleep Duration, 7 values via LUT, default = 125ms
Bits 6 = Mains sync, negative edge, 1 = enabled; default = 0 (off)
18
17
7
252
1
Awake Timeout
AWAKE
1...255
8
24
25
Range is in 100ms increments; 1 = 100ms. Default = 2.5s. 0 is illegal to use
18
8
253
1
Drift Hold Time
DHT
0...255
8
24
10
Range is in 100ms increments; 0 = disable, 1 = 100ms, default = 1s
18
lQ
20
Preliminary information; subject to change
QT60240-XSG X7.04/0706
Table 6.3 Setups Lookup Table
Applies to both QT60160 and QT60240
Typical values: For most touch applications, use the values shown in the outlined cells. Bold text items indicate default settings. The number to send to the QT is the number in
the leftmost column (0...15), not numbers from within the table. The QT uses lookup tables to translate the 0.. .15 to the parameters for each function.
NRD is an exception: it can range from 0...254 which is translated from 1= 0.5s to 254= 127s with zero = infinity. 255 is illegal.
AWAKE is an exception: it can range from 0...255 which is translated from 1= 0.1s to 255s= 25.5s. Zero is illegal.
Parameter
Index
Number
NTHR
counts
NDRIFT
secs
PDRIFT
secs
NDIL
counts
FDIL
counts
NRD
secs
WAKE
BL
pulses
AKS
SSYNC
SLEEP
ms
MSYNC
AWAKE
secs
DHT
secs
Per key
Per key
Per key
Per key
Per key
Per key
Per key
Per key
Per key
Per key
Global
Global
Global
Global
0
4
0.1
0.1
Key off
unused
0 (Infinite)
Off
16
- Off -
- Off -
16
- Off -
unused
Off
1
5
0.2
0.2
1
1
0.5 .. 127s
- On -
32
On
On
32
On
2
6
0.3
0.3
-2-
2
3
7
0.4
0.4
3
3
4
8
0.6
- 0.6 -
4
4
250
5
9
0.8
0.8
5
-5-
500
6
- 10 -
1
1
6
6
1,000
7
11
1.2
1.2
7
7
2,000
8
12
1.5
1.5
8
8
9
13
2
2
9
9
10
14
- 2.5 -
- 2.5 -
10
10
11
15
3.3
3.3
11
11
12
16
4.5
4.5
12
12
13
17
6
6
13
13
14
18
7.5
7.5
14
14
15
19
10
10
15
15
lQ
Default=
10s
- 48 -
64
64
-125-
21
Preliminary information; subject to change
0.1...25.5s 0.1...25.5s
Default=
2.5s
Default=
1s
QT60240-XSG X7.04/0706
7 Specifications
7.1 Absolute Maximum Electrical Specifications
Operating temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40OC to +85OC
Storage temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55OC to +125OC
Vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +5.5V
Max continuous pin current, any control or drive pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mA
Short circuit duration to ground, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite
Short circuit duration to Vdd, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite
Voltage forced onto any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to (Vdd + 0.6) Volts
EEPROM setups maximum writes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100,000 write cycles
7.2 Recommended Operating Conditions
Vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.8V to 5.25V
Supply ripple+noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mV p-p max
Cx transverse load capacitance per key. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 20pF
7.3 DC Specifications
Vdd = 5.0V, Cs = 4.7nF, Rs = 470K; Ta = recommended range, unless otherwise noted
Parameter
Description
Min
Typ
Max
Iddr
Supply current, running
Vil
Low input logic level
Vhl
High input logic level
Vol
Low output voltage
Voh
High output voltage
Iil
Input leakage current
Ar
Acquisition resolution
Rrst
Units
Notes
mA
0.2Vdd
0.6Vdd
0.2
4.2
V
1.8V <Vdd <5V
V
1.8V <Vdd <5V
V
V
1
10
Internal /RST pullup resistor
µA
bits
60
k✡
Max
Units
7.4 Timing Specifications
Parameter
Description
Min
TBS
Burst spacing
Fc
Burst center frequency
Fm
Burst modulation, percent
lQ
Typ
Notes
µs
kHz
%
22
QT60240-XSG X7.04/0706
Preliminary information; subject to change
7.5 Mechanical Dimensions
B
F
PIN 1
e
G
C
Symbol
A
A1
A2
A3
B
C
D
E
F
G
e
Dimensions in Millimeters
Minimum
Nominal
Maximum
0.80
0.90
1.00
0.02
0.05
0.65
1.00
0.20 REF
5.00 BSC
5.00 BSC
0.18
0.23
0.30
0.30
0.40
0.50
2.95
3.10
3.25
2.95
3.10
3.25
0.50 BSC
E
D
A
A2
A3
A1
7.6 Marking
TA
-400C to +850C
-400C to +850C
lQ
MLF Part Number
QT60160-XSG
QT60240-XSG
Keys
16
24
Marking
6160
6240
23
QT60240-XSG X7.04/0706
Preliminary information; subject to change
lQ
Copyright © 2006 QRG Ltd. All rights reserved
Patented and patents pending
Corporate Headquarters
1 Mitchell Point
Ensign Way, Hamble SO31 4RF
Great Britain
Tel: +44 (0)23 8056 5600 Fax: +44 (0)23 8045 3939
www.qprox.com
North America
651 Holiday Drive Bldg. 5 / 300
Pittsburgh, PA 15220 USA
Tel: 412-391-7367 Fax: 412-291-1015
This device is covered under one or more United States and corresponding international patents. QRG patent numbers can be found online
at www.qprox.com. Numerous further patents are pending, which may apply to this device or the applications thereof.
The specifications set out in this document are subject to change without notice. All products sold and services supplied by QRG are subject
to our Terms and Conditions of sale and supply of services which are available online at www.qprox.com and are supplied with every order
acknowledgement. QRG trademarks can be found online at www.qprox.com. QRG products are not suitable for medical (including lifesaving
equipment), safety or mission critical applications or other similar purposes. Except as expressly set out in QRG's Terms and Conditions, no
licenses to patents or other intellectual property of QRG (express or implied) are granted by QRG in connection with the sale of QRG
products or provision of QRG services. QRG will not be liable for customer product design and customers are entirely responsible for their
products and applications which incorporate QRG's products.
Development Team: Dr. Tim Ingersoll, Samuel Brunet