www.fairchildsemi.com RC5052 High Performance Programmable Synchronous DC-DC Controller for Low Voltage Microprocessors Features Description • Optimized for 12V main power • Programmable output from 1.3V to 3.5V using an integrated 5-bit DAC • Remote sense • Active Droop • 85% efficiency typical at full load • Integrated Power Good and Enable/Soft Start functions • Drives N-channel MOSFETs • Overcurrent protection using MOSFET sensing • 20 pin SOIC package • Meets Intel Pentium II & III specifications using minimum number of external components • Adjustable deadtime, frequency • Crowbar protection for overvoltage The RC5052 is a synchronous mode DC-DC controller IC, optimized for 12V main power, which provides a highly accurate, programmable output voltage for all Pentium II & III CPU applications and other high-performance processors. The RC5052 features remote voltage sensing, adjustable current limit, and active droop for optimal converter transient response. The RC5052 uses a 5-bit D/A converter to program the output voltage from 1.3V to 3.5V. The RC5052 uses a high level of integration to deliver load currents in excess of 16A from a 12V source with minimal external circuitry. Synchronous-mode operation offers optimum efficiency over the entire specified output voltage range. An on-board precision low TC reference achieves tight tolerance voltage regulation without expensive external components, while active droop permits exact tailoring of voltage for the most demanding load transients. The RC5052 also offers integrated functions including Power Good, Output Enable/Soft Start, current limiting, adjustable frequency, adjustable deadtime and overvoltage crowbar protection, and is available in a 20 pin SOIC package. Applications • • • • • Power supply for Pentium® II & III VRM for Pentium II & III processor Telecom line cards Routers, switches & hubs Programmable step-down power supply Block Diagram +12V +5V DTA 15 Rosc 1 VCCA 6 4 RS 13 + OSC 5 11 VCCP 12 HIDRV + Digital Control + +12V + VO 10 9 LODRV 8 5-Bit DAC GNDP 1.24V Reference Power Good 20 19181716 VID0 VID2 VID4 VID1 VID3 14 GNDA 2 ENABLE/SS 3 PWRGD 7 OVP Pentium is a registered trademark of Intel Corporation REV. 1.3.2 8/27/01 RC5052 PRODUCT SPECIFICATION Pin Assignments ROSC ENABLE/SS PWRGD IFB VFB VCCA OVP GNDP LODRV VCCP 1 2 3 4 5 6 7 8 9 10 20 17 16 VID0 VID1 VID2 VID3 VID4 15 14 DTA GNDA 13 12 11 SW HIDRV 19 18 RC5052 VCCQP Pin Definitions 2 Pin Number Pin Name Pin Function Description 1 ROSC Oscillator Resistor Connection. Connect an external resistor to this pin to set the internal oscillator frequency. Layout of this pin is critical to system performance. See Application Information for details. 2 ENABLE/SS Output Enable/Softstart. A logic LOW on this pin will disable the output. An internal current source allows for open collector control. This pin also doubles as soft start. 3 PWRGD Power Good Flag. An open collector output that will be logic LOW if the output voltage is not within ±12% of the nominal output voltage setpoint. 4 IFB Current Feedback. Pin 4 is used in conjunction with pin 13, as the input for the current feedback control loop. Layout of these traces is critical to system performance. See Application Information for details. 5 VFB Voltage Feedback. Pin 5 is used as the input for the voltage feedback control loop. See Application Information for details regarding correct layout. 6 VCCA Analog VCC. Connect to system 5V supply and decouple with a 0.1µF ceramic capacitor. 7 OVP 8 GNDP Power Ground. Return pin for high currents flowing in pins 10 and 11. Connect to a low impedance ground. 9 LODRV Low Side FET Driver. Connect this pin to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should be <0.5". 10 VCCP 11 VCCQP High Side Power VCC. For high side FET driver. Connect to system 12V supply and decouple with a 10Ω resistor, 4.7µF tantalum and a 0.1µF ceramic capacitor. 12 HIDRV High Side FET Driver. Connect this pin to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should be <0.5". 13 SW High side driver source and low side driver drain switching node. Together with IFB pin allows FET sensing for current. 14 GNDA Analog Ground. Return path for low power analog circuitry. This pin should be connected to a low impedance system ground plane to minimize ground loops. 15 DTA Dead Time Adjust. Connect an external resistor to this pin to set the dead time. 16–20 VID0-4 Voltage Identification Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 2. Pull-up resistors are internal to the controller. Over Voltage Protection. This pin triggers the gate of an external SCR. Power VCC. For low side FET driver. Connect to system 12V supply and decouple with a 10Ω resistor, 4.7µF tantalum and a 0.1µF ceramic capacitor. REV. 1.3.2 8/27/01 PRODUCT SPECIFICATION RC5052 Absolute Maximum Ratings Supply Voltage VCCA to GND 13.5V Supply Voltages VCCP, VCCQP to GND 15V Supply Voltage (VCCQP, Charge Pump) 18V Voltage Identification Code Inputs, VID0-VID4 VCCA Junction Temperature, TJ 150°C Storage Temperature -65 to 150°C Lead Soldering Temperature, 10 seconds 300°C Power Dissipation, PD 750mW Thermal Resistance Junction-to-case, ΘJC 105°C/W Recommended Operating Conditions Parameter Conditions Min. Typ. Max. Units Supply Voltage VCCA 4.5 5 5.25 V Input Logic HIGH 2.0 V Input Logic LOW Ambient Operating Temperature Output Driver Supply, VCCP & VCCQP REV. 1.3.2 8/27/01 0 11.4 12 0.8 V 70 °C 13.2 V 3 RC5052 PRODUCT SPECIFICATION Electrical Specifications (VCCA = 5V, VCCP = VCCQP = 12V, VOUT = 2.0V, and TA = +25°C using circuit in Figure 1, unless otherwise noted.) The • denotes specifications which apply over the full operating temperature range. Parameter Output Voltage Conditions See Table 1 Min. • Typ. 1.3 Output Current Max. Units 3.5 V 2.454 2.040 1.580 V V V 18 ILOAD = 0.8A, VOUT = 2.400V VOUT = 2.000V VOUT = 1.550V Output Temperature Drift TA = 0 to 70°C, VOUT = 2.000V VOUT = 1.550V • • +8 +6 mV mV Line Regulation VCCA = 4.75V to 5.25V, VOUT = 2.000V • ±2 mV Internal Droop3 2.397 2.000 1.550 A Initial Voltage Setpoint VOUT at ILOAD = 0.8A to Imax -44 2.424 2.020 1.565 -40 -36 Output Ripple 20MHz BW, ILOAD = Imax Total Output Variation, Steady State1 VOUT = 2.000V VOUT = 1.550V3 • • 1.940 1.480 2.070 1.590 V Total Output Variation, Transient2 ILOAD = 0.8A to Imax,VOUT = 2.000V VOUT = 1.550V3 • • 1.900 1.480 2.100 1.590 V • 45 60 µA Short Circuit Detect Current 11 mV mVpk Efficiency ILOAD = Imax, VOUT = 2.0V 85 % Output Driver Rise & Fall Time See Figure 5 for tR and tF 50 nsec Output Driver Deadtime RDTA = OPEN. See Figure 3 for tDT 50 nsec Oscillator Frequency ROSC = OPEN 345 kHz Oscillator Range 80 1000 MHz Duty Cycle 0 100 % Dead Time Range 50 120 nsec • • 93 88 107 112 %Vout VCCA UVLO • 3.74 4 4.26 V VCCP UVLO • 7.65 8.5 9.35 V PWRGD Threshold Logic HIGH Logic LOW • 255 VCCA Supply Current VCCP Supply 19 Current4 OVP Trigger Threshold mA 40 Soft Start Current OVP Ouput High Current 300 • V = 1.5V 5 10 mA 17 37.5 115 µA mA 120 125 %Vout Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Droop, Output Ripple and Output Temperature Drift and is measured at the converter’s VFB sense point. 2. As measured at the converter’s VFB sense point. For motherboard applications, the PCB layout should exhibit no more than 0.5mΩ trace resistance between the converter’s output capacitors and the CPU. Remote sensing should be used for optimal performance. 3. Using the VFB pin for remote sensing of the converter’s output at the load, the converter will be in compliance with Intel’s VRM 8.4 specification of +50, -80mV. If Intel specifications on maximum plane resistance from the converter’s output capacitors to the CPU are met, the specification of +40, -70mV at the capacitors will also be met. 4. Includes gate current. 4 REV. 1.3.2 8/27/01 PRODUCT SPECIFICATION RC5052 Table 1. Output Voltage Programming Codes VID4 VID3 VID2 VID1 VID0 Nominal VOUT 0 1 1 1 1 1.30V 0 1 1 1 0 1.35V 0 1 1 0 1 1.40V 0 1 1 0 0 1.45V 0 1 0 1 1 1.50V 0 1 0 1 0 1.55V 0 1 0 0 1 1.60V 0 1 0 0 0 1.65V 0 0 1 1 1 1.70V 0 0 1 1 0 1.75V 0 0 1 0 1 1.80V 0 0 1 0 0 1.85V 0 0 0 1 1 1.90V 0 0 0 1 0 1.95V 0 0 0 0 1 2.00V 0 0 0 0 0 2.05V 1 1 1 1 1 2.0V 1 1 1 1 0 2.1V 1 1 1 0 1 2.2V 1 1 1 0 0 2.3V 1 1 0 1 1 2.4V 1 1 0 1 0 2.5V 1 1 0 0 1 2.6V 1 1 0 0 0 2.7V 1 0 1 1 1 2.8V 1 0 1 1 0 2.9V 1 0 1 0 1 3.0V 1 0 1 0 0 3.1V 1 0 0 1 1 3.2V 1 0 0 1 0 3.3V 1 0 0 0 1 3.4V 1 0 0 0 0 3.5V Note: 1. 0 = processor pin is tied to GND. 1 = processor pin is open. REV. 1.3.2 8/27/01 5 RC5052 PRODUCT SPECIFICATION Typical Operating Characteristics (VCCA = 5V, VCCP = VCCQP = 12V, and TA = +25°C using circuit in Figure 1, unless otherwise noted.) Efficiency vs. Output Current Droop, VOUT = 2.0V 2.04 88 2.02 2.01 82 80 VOUT (V) Efficiency (%) 2.03 VOUT = 2.000V 86 84 VOUT = 1.550V 78 76 1.99 1.98 1.97 74 72 70 68 66 64 2.00 1.96 1.95 1.94 0 3 6 9 12 15 18 Output Current (A) 0 3 6 9 12 15 18 Output Current (A) Output Voltage vs. Output Current 3.5 3.0 VOUT (V) 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 Output Current (A) Output Programming, VID4 = 1 2.1 3.5 1.9 3.0 1.7 2.5 VOUT (V) VOUT (V) Output Programming, VID4 = 0 1.5 1.3 1.1 1.30 1.5 1.0 1.40 1.50 1.60 1.70 DAC Setpoint 6 2.0 1.80 1.90 2.00 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 DAC Setpoint REV. 1.3.2 8/27/01 PRODUCT SPECIFICATION RC5052 Typical Operating Characteristics (continued) Transient Res p onse, 12.5A to 0.5A VOUT (20mV/div) VOUT (50mV/div) Output Ripple, 2.0V @ 18A 1.590V 1.550V 1.480V Time (1µs/division) Time (20µs/division) VOUT (50mV/div) Transient Response, 0.5A to 12.5A 1.590V 1.550V 1.480V Time (20µs/division) 5V/ div LODRV pin VIN (2V/div) HIDRV pin Time (1µs/division) REV. 1.3.2 8/27/01 Output Startup, System Power-up VOUT (1V/div) 5V/div Switching Waveforms, 18A Load Time (10ms/division) 7 RC5052 PRODUCT SPECIFICATION Typical Operating Characteristics (continued) VOUT Temperature Variation Output Startup from Enable VOUT (1V/div) ENABLE (2V/div) 2.042 2.040 VOUT (V) 2.038 2.036 2.034 2.030 2.028 2.026 0 25 Time (10ms/division) 70 100 Temperature (°C) Application Circuit +5V F1* L1 (Optional) 2.5µH +12V CIN* C2 1µF R6 10Ω Q3 2N6394 C5 1µF R2 4.7Ω Q1 C1 1µF R11 200Ω Optional R8 (Optional) VID4 VID3 VID2 VID1 VID0 D2 6.2V R1 33Ω 10 9 8 7 6 5 4 3 2 1 U1 RC5052 R9 3mΩ VO R3 4.7Ω 11 12 13 14 15 16 17 18 19 20 C3 0.1µF R10 10Ω L2 1.3µH Q2 D1 MBRD835L COUT* R5 6.24KΩ VCC R4 10KΩ ENABLE/SS *Refer to Table 3 for values of COUT F1, and CIN. PWRGD C4 0.1µF C6 0.1µF R7 (Optional) Figure 1. 12V Main Power Application Circuit for Coppermine/Camino Processors, Including Crowbar (Typical Design) 8 REV. 1.3.2 8/27/01 PRODUCT SPECIFICATION RC5052 Table 2. RC5052 Application Bill of Materials for Coppermine/Camino Processors, Including Crowbar (Typical Design) Reference Manufacturer Part # C1-2, C5 AVX TAJB475M010R5 Quantity 3 1µF, 16V Capacitor C3-4,6 Panasonic ECU-V1H104ZFX 3 100nF, 50V Capacitor CIN Sanyo 10MV1200GX 3 1200µF, 10V Electrolytic IRMS = 2A COUT Sanyo 6MV1500GX 8 1500µF, 6.3V Electrolytic D1 Fairchild MBRS320 1 8A Schottky Diode D2 Fairchild MMSZ5233B 1 6.2V Zener L1 Any L2 Any 1 1.3µH, 20A Inductor DCR ~ 2mΩ Q1-2 Fairchild FDP6030L or FDB6030L 2 N-Channel MOSFET (TO-220 or TO-263) RDS(ON) = 20mΩ @ VGS = 4.5V See Note 2. Q3 Motorola 2N6394 R1 Optional Description 2.5µH, 10A Inductor Requirements/Comments ESR ≤ 44mΩ DCR ~ 6mΩ See Note 1. Optional SCR Any 1 33Ω R2-3 Any 2 4.7Ω R4 Any 1 10KΩ R5 Any 1 6.24KΩ R6, R10 Any 2 10Ω R7 Any Optional Sets frequency. R8 Any Optional Sets deadtime. R9 Any 1 R11 Any F1 Littelfuse R251 005 U1 Fairchild RC5052M 1 3.0mΩ PCB Trace Resistor Optional 200Ω Must be used when Q3 present. Optional 5A Fast Fuse DC/DC Controller Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For designs using the TO-220 MOSFETs, heatsinks with thermal resistance ΘSA < 20°C/W should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8. REV. 1.3.2 8/27/01 9 RC5052 PRODUCT SPECIFICATION +12V F1* L1 (Optional) 2.5µH +5V R1 33Ω CIN* R6 10Ω Q3 2N6394 C5 1µF C1 4.7µF R10 200Ω Optional R8 (Optional) VID4 VID3 VID2 VID1 VID0 C2 1µF R2 4.7Ω 10 9 8 7 6 5 4 3 2 1 U1 RC5052 L2 1.3µH Q2 D1 MBRD835L R9 3mΩ VO R3 4.7Ω 11 12 13 14 15 16 17 18 19 20 Q1 COUT* C3 0.1µF R5* 6.24KΩ VCC R4 10KΩ ENABLE/SS *Refer to Table 3 for values of COUT, R5, and CIN. PWRGD C6 0.1µF C4 0.1µF R7 (Optional) Figure 2. Typical 5V Main Power Application Circuit, Including Crowbar 10 REV. 1.3.2 8/27/01 PRODUCT SPECIFICATION RC5052 Table 3. RC5052 Application Bill of Materials for Coppermine/Camino Processors (Typical Design) Reference Manufacturer Part # Quantity Description C1 AVX TAJB475M010R5 1 4.7µF, 10V Capacitor C2, C5 Panasonic ECU-V1C105ZFX 2 1µF, 16V Capacitor C3-4,6 Panasonic ECU-V1H104ZFX 3 100nF, 50V Capacitor CIN Sanyo 10MV1200GX 3 1200µF, 10V Electrolytic IRMS = 2A COUT Sanyo 6MV1500GX 8 1500µF, 6.3V Electrolytic D1 Fairchild MBRD835L 1 8A Schottky Diode L1 Any Optional 2.5µH, 10A Inductor DCR ~ 6mΩ See Note 1. L2 Any 1 1.3µH, 20A Inductor DCR ~ 2mΩ Q1-2 Fairchild FDP6030L or FDB6030L 2 N-Channel MOSFET (TO-220 or TO-263) RDS(ON) = 20mΩ @ VGS = 4.5V See Note 2. Q3 Motorola 2N6394 R1 Any Optional SCR 1 33Ω R2-3 Any 2 4.7Ω R4 Any 1 10KΩ R5 Any 1 6.24KΩ R6 Any 1 10Ω R7 Any Optional R8 N/A Optional R9 Any 1 3.0mΩ R10 Any Optional 200Ω F1 Littelfuse R251 005 Optional 5A Fast Fuse U1 Fairchild RC5052M 1 Requirements/Comments ESR ≤ 44mΩ Sets frequency. Sets deadtime. PCB Trace Resistor DC/DC Controller Notes: 1. Inductor L1 is recommended to isolate the 5V input supply from noise generated by the MOSFET switching, and to comply with Intel dI/dt requirements. L1 may be omitted if desired. 2. For designs using the TO-220 MOSFETs, heatsinks with thermal resistance ΘSA < 20°C/W should be used. For designs using the TO-263 MOSFETs, adequate copper area should be used. For details and a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8. REV. 1.3.2 8/27/01 11 RC5052 PRODUCT SPECIFICATION Test Parameters tR tF 90% 2V 10% 90% HIDRV 2V 10% tDT tDT 2V 2V LODRV Figure 3. Output Drive Timing Diagram Application Information The RC5052 Controller The RC5052 is a programmable synchronous DC-DC controller IC optimized for 12V main power. It may also be used in a 5V main power circuit when the crowbar and additional programmability of the RC5052 are desired. When designed around the appropriate external components, the RC5052 can be configured to deliver more than 16A of output current, as appropriate for the Katmai and Coppermine and other processors. The RC5052 functions as a fixed frequency PWM step down regulator. Main Control Loop Refer to the RC5052 Block Diagram on page 1. The RC5052 implements “summing mode control”, which is different from both classical voltage-mode and current-mode control. It provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a comparator which provides the input to the digital control block. The signal conditioning section accepts input from the IFB (current feedback) and VFB (voltage feedback) pins and sets up two controlling signal paths. The first, the voltage control path, amplifies the difference between the VFB signal and the reference voltage from the DAC and presents the output to one of the summing amplifier inputs. The second, current control path, takes the difference between the IFB and SW pins when the high-side MOSFET is on, reproducing the voltage across the MOSFET and thus the input current; it presents the resulting signal to another input of the summing amplifier. These two signals are then summed together. This output is then presented to a comparator looking at the oscillator ramp, which provides the main PWM control signal to the digital control block. The digital control block takes the analog comparator input and the main clock signal from the oscillator to provide the appropriate pulses to the HIDRV and LODRV output pins. These two outputs control the external power MOSFETs. 12 There is an additional comparator in the analog control section whose function is to set the point at which the RC5052 current limit comparator disables the output drive signals to the external power MOSFETs. High Current Output Drivers The RC5052 contains two identical high current output drivers that utilize high speed bipolar transistors in a push-pull configuration. The drivers’ power and ground are separated from the chip’s power and ground for switching noise immunity. The high-side driver’s power supply pin, VCCQP, is supplied from an external 12V source through a series resistor. The resulting voltage is sufficient to provide the gate to source drive to the external MOSFETs required in order to achieve a low RDS,ON. The low-side driver’s power supply pin, VCCP, is supplied from the same source as VCCQP. The VCCQP pin should be run as a charge pump for +12V Main Power, as shown in Figure 1. Internal Voltage Reference The reference included in the RC5052 is a precision band-gap voltage reference. Its internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Based on the reference is the output from an integrated 5-bit DAC. The DAC monitors the 5 voltage identification pins, VID0-4. When the VID4 pin is at logic HIGH, the DAC scales the reference voltage from 2.0V to 3.5V in 100mV increments. When VID4 is pulled LOW, the DAC scales the reference from 1.30V to 2.05V in 50mV increments. All VID codes are available, including those below 1.80V. The output voltage may be changed while the converter is on by changing the VID codes; however, it is necessary to do so in 1-bit steps, to avoid triggering the overvoltage protection. Power Good (PWRGD) The RC5052 Power Good function is designed in accordance with the Pentium II DC-DC converter specifications and provides a continuous voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage deviate more than ±12% of its nominal setpoint. The output is guaranteed open-collector high when the power supply voltage is within ±7% of its nominal setpoint. REV. 1.3.2 8/27/01 PRODUCT SPECIFICATION RC5052 The Power Good flag provides no other control function to the RC5052. Design Considerations and Component Selection Output Enable/Soft Start (ENABLE/SS) Additional information on design and component selection may be found in Fairchild’s Application Note 57. The RC5052 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the low state. MOSFET Selection Even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nF) to softstart the switching. A larger value may occasionally be required if the converter has a very large capacitor at its output. Over-Voltage Protection The RC5052 constantly monitors the output voltage for protection against over-voltage conditions. If the voltage at the VFB pin exceeds the selected program voltage, an over-voltage condition is assumed and the RC5052 disables the output drive signal to the external high-side MOSFET, and drives the OVP pin high. This is designed to drive the gate of an external SCR, which blows a fuse, disconnecting the short from the power bus. See Figures 1-2 for the suggested implementation. This application requires N-channel Logic Level Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: • Low Static Drain-Source On-Resistance, RDS,ON < 20mΩ (lower is better) • Low gate drive voltage, VGS = 4.5V rated • Power package with low Thermal Resistance • Drain-Source voltage rating > 15V. The on-resistance (RDS,ON) is the primary parameter for MOSFET selection. The on-resistance determines the power dissipation within the MOSFET and therefore significantly affects the efficiency of the DC-DC Converter. For details and a spreadsheet on MOSFET selection, refer to Applications Bulletin AB-8. Inductor Selection Oscillator The RC5052 oscillator free runs at 300 MHz, and may be adjusted from 80KHz to 1MHz as desired. Higher frequencies will permit smaller components, while decreasing efficiency. A typical operating frequency is 300KHz. The frequency may be adjusted up with a resistor to ground on pin 1, according to the formula: Choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. The system designer can choose any value within the allowed minimum to maximum range in order to either minimize ripple or maximize transient performance. The first order equation (close approximation) for minimum inductance is: Lmin = 40KΩ f = 300kHz * 1+ (Vin – Vout) f x Vout ESR x Vin Vripple ROSC where: and may be adjusted down with a resistor to 5V on pin 1, according to the formula: 160KΩ f = 300kHz * 1- ROSC The RC5052 can control the deadtime, that is, the time between when the high-side MOSFET is turned off and the low-side MOSFET is turned on, and vice versa. Longer dead times are appropriate when using multiple MOSFETs in parallel, or when MOSFETs with larger gate capacitance are used. The dead time may be adjusted with a resistor to ground on pin 15, according to the formula: REV. 1.3.2 8/27/01 Vout = Output Voltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel Dead Time TDT = 15nsec + Vin = Input Power Supply Vripple = Maximum peak to peak output ripple voltage budget. The first order equation for maximum allowed inductance is: Lmax = 2C0 (Vin – Vout) Dm Vtb Ipp2 40KΩ * RDTA 10nsec * 10KΩ Ω+ KΩ 40KΩ + RDTA 13 RC5052 PRODUCT SPECIFICATION where: The converter exhibits a normal load regulation characteristic until the voltage across the MOSFET exceeds the internal short circuit threshold of 50µA * 8.2KΩ = 410mV, which occurs at 410mV/25mΩ = 16.4A. (Note that this current limit level can be as high as 410mV/15mΩ = 27A, if the MOSFET has typical RDS,on rather than maximum, and is at 25°C. This is the reason for using the external sense resistor.) At this point, the internal comparator trips and signals the controller to reduce the converter’s duty cycle to approximately 20%. This causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit control mode. With a 40mΩ output short, the voltage is reduced to 16.4A * 40mΩ = 650mV. The output voltage does not return to its nominal value until the output current is reduced to a value within the safe operating range for the DC-DC converter. Co = The total output capacitance Ipp = Maximum to minimum load transient current Vtb = The output voltage tolerance budget allocated to load transient Dm = Maximum duty cycle for the DC/DC converter (usually 95%). Some margin should be maintained away from both Lmin and Lmax. Adding margin by increasing L almost always adds expense since all the variables are predetermined by system performance except for Co, which must be increased to increase L. Adding margin by decreasing L can be done by purchasing capacitors with lower ESR. The RC5052 provides significant cost savings for the newer CPU systems that typically run at high supply current. RC5052 Short Circuit Current Characteristics The RC5052 short circuit current characteristic includes a hysteresis function that prevents the DC-DC converter from oscillating in the event of a short circuit. The short circuit limit is set with the R5 resistor, as given by the formula RS IFB RSENSE SW VOUT ISC RDS, on R5 = IDetect Figure 5. Precision Current Sensing with IDetect ≈ 50µA, ISC the desired current limit, and RDS,on the high-side MOSFET’s on resistance. Remember to make the R5 large enough to include the effects of initial tolerance and temperature variation on the MOSFET’s RDS,on. However, the value of R5 must be < 8.3KΩ. Alternately, use of a sense resistor in series with the source of the MOSFET, as shown in Figure 5, eliminates this source of inaccuracy in the current limit. Note the addition of one diode, which is necessary for proper operation of this circuit. As an example, Figure 4 shows the typical characteristic of the DC-DC converter circuit with an FDB6030L high-side MOSFET (RDS = 20mΩ maximum at 25°C * 1.25 at 75°C = 25mΩ) and a 8.2KΩ RS. Schottky Diode Selection The application circuit of Figure 1 shows a Schottky diode, D1, which is used as a free-wheeling diode to assure that the body-diode in Q2 does not conduct when the upper MOSFET is turning off and the lower MOSFET is turning on. It is undesirable for this diode to conduct because its high forward voltage drop and long reverse recovery time degrades efficiency, and so the Schottky provides a shunt path for the current. Since this time duration is very short, the selection criterion for the diode is that the forward voltage of the Schottky at the output current should be less than the forward voltage of the MOSFET’s body diode. Output Filter Capacitors 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 Output Current (A) 25 The output bulk capacitors of a converter help determine its output ripple voltage and its transient response. It has already been seen in the section on selecting an inductor that the ESR helps set the minimum inductance, and the capacitance value helps set the maximum inductance. For most converters, however, the number of capacitors required is determined by the transient response and the output ripple voltage, and these are determined by the ESR and not the capacitance value. That is, in order to achieve the necessary ESR to meet the transient and ripple requirements, the capacitance value required is already very large. Figure 4. RC5052 Short Circuit Characteristic 14 REV. 1.3.2 8/27/01 PRODUCT SPECIFICATION RC5052 The most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low ESR. The only type of aluminum capacitor used should be those that have an ESR rated at 100kHz. Consult Application Bulletin AB-14 for detailed information on output capacitor selection. The output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1µF and 0.01µF are recommended values. Input Filter The DC-DC converter design may include an input inductor between the system +5V supply and the converter input as shown in Figure 6. This inductor serves to isolate the +5V supply from the noise in the switching portion of the DC-DC converter, and to limit the inrush current into the input capacitors during power up. A value of 2.5µH is recommended. It is necessary to have some low ESR aluminum electrolytic capacitors at the input to the converter. These capacitors deliver current when the high side MOSFET switches on. Figure 6 shows 3 x 1000µF, but the exact number required will vary with the speed and type of the processor. For the top speed Katmai and Coppermine, the capacitors should be rated to take 9A and 6A RMS of ripple current respectively. Capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to find out the ripple current rating at the expected operational temperature. For details on the design of an input filter, refer to Applications Bulletin AB-15. 2.5µH Vin 5V 1000µF, 10V Electrolytic 0.1µF Figure 6. Input Filter Active Droop The RC5052 includes active droop: as the output current increases, the output voltage drops. This is done in order to allow maximum headroom for transient response of the converter. The current is sensed by measuring the voltage across the high-side MOSFET during its on time. Note that this makes the droop dependent on the temperature of the MOSFET. However, when the formula given for selecting RS (current limit) is used, there is a maximum droop possible (-40mV), and when this value is reached, additional drop across the MOSFET will not cause any increase in droop—until current limit is reached. REV. 1.3.2 8/27/01 Additional droop can be added to the active droop using a discrete resistor (typically a PCB trace) outside the control loop, as shown in Figure 2. This is typically only required for the most demanding applications, such as for the next generation Intel processor (tolerance = +40/-70mV). PCB Layout Guidelines • Placement of the MOSFETs relative to the RC5052 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the RC5052 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difficult to suppress. • In general, all of the noisy switching lines should be kept away from the quiet analog section of the RC5052. That is, traces that connect to pins 9, 10, 11, 12 and 13 (LODRV, VCCP, VCCQP, HIDRV and SW) should be kept far away from the traces that connect to pins 4 through 6, and pin 14. • Place the 0.1µF decoupling capacitors as close to the RC5052 pins as possible. Extra lead length on these reduces their ability to suppress noise. • Each VCC and GND pin should have its own via to the appropriate plane. This helps provide isolation between pins. • Place the MOSFETs, inductor, and Schottky as close together as possible for the same reasons as in the first bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1µF decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter. • Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converter’s performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5. • A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11. Additional Information For additional information contact Fairchild Semiconductor at http://www.fairchildsemi.com/cf/tsgn.htm or contact an authorized representative in your area. 15 RC5052 PRODUCT SPECIFICATION Appendix The value of R5 must be ≤ 8.3KΩ. If a greater value is calculated, RD must be reduced. Worst-Case Formulae for the Calculation of Cout, R5, and Cin (Circuit of Figure 1 Only) Number of capacitors needed for Cout = the greater of: The following formulae design the RC5052 for worst-case operation, including initial tolerance and temperature dependence of all of the IC parameters (initial setpoint, reference tolerance and tempco, active droop tolerance, current sensor gain), the initial tolerance and temperature dependence of the MOSFET, and the ESR of the capacitors. The following information must be provided: ESR * IO X = VT- or ESR * IO Y = VT+, the value of the positive transient voltage limit; 14400 * IO * RD VT+ –0.004 * Vnom + 18 * R5 * 1.1 |VT-|, the absolute value of the negative transient voltage limit; IO, the maximum output current; Example: Suppose that the transient limits are ±134mV, current I is 14.2A, and the nominal voltage is 2.000V, using MOSFET current sensing and the usual caps. We have VT+ = |VT-| = 0.134, IO = 14.2, Vnom = 2.000, and ∆RD = 0.67. We calculate: Vnom, the nominal output voltage; Vin, the input voltage (typically 5V); ESR, the ESR of the output caps, per cap (44mΩ for the Sanyo parts shown in this datasheet); 2.000 14.2 * RD, the on-resistance of the MOSFET (10mΩ for the FDB7030); – 2.000 5 5 2 = 3.47 ⇒ 4 caps Cin = 2 ∆RD, the tolerance of the current sensor (usually about 67% for MOSFET sensing, including temperature). R5 = 14.2 * 0.010 * (1 + 0.67) * 1.10 = 5.2KΩ 50 * 10-6 Irms, the rms current rating of the input caps (2A for the Sanyo parts shown in this datasheet). X= 0.044 * 14.2 = 4.66 0.134 2 IO * Vnom – Vin Vnom Vin Cin = 0.134 – 0.004 * 2.000 + Irms R5 = 0.044 * 14.2 IO* RD * (1 + ∆RD) * 1.10 = 4.28 Y = 14400 * 14.2 * 0.020 18 * 10400 * 1.1 Since X > Y, we choose X, and round up to find we need 5 capacitors for COUT. 50 * 10-6 A detailed explanation of this calculation may be found Applications Bulletin AB-XX. 16 REV. 1.3.2 8/27/01 PRODUCT SPECIFICATION RC5052 Mechanical Dimensions 20 Lead SOIC Inches Symbol Min. A A1 B C D E e H h L N α ccc Notes: Millimeters Max. Min. Notes .093 .104 .004 .012 .013 .020 .009 .013 .496 .512 .291 .299 .050 BSC 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 12.60 13.00 7.40 7.60 1.27 BSC .394 .010 .016 10.00 0.25 0.40 .419 .029 .050 20 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. Max. 10.65 0.75 1.27 20 0° 8° 0° 8° — .004 — 0.10 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals. 3 6 11 20 E H 10 1 h x 45° D C A1 A e B SEATING PLANE –C– LEAD COPLANARITY α L ccc C REV. 1.3.2 8/27/01 17 RC5052 PRODUCT SPECIFICATION Ordering Information Product Number RC5052M Package 20 pin SOIC DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 8/27/01 0.0m 011 Stock#DS30005052 2001 Fairchild Semiconductor Corporation