RX3408 Low Power IF Receiver and PLL Frequency Synthesizer IC DESCRIPTION FEATURES The RX3408 is a low power IF receiver suitable for use as the second IF down-converter in double conversion receiver systems and a serial data input, phase-locked loop IC with programmable input and reference frequency dividers. The RX3408 is well-suited for wireless FM applications and incorporates a quadrature FM demodulator, on-chip audio filter, and a squelch/mute circuit. When combined with a VCO, this IC becomes the core of a very low power frequency synthesizer well-suited for mobile communication applications, such as paging systems and family radio service (FRS). There are some features implemented in this IC, including an 18-bit programmable input frequency divider, a terminal for reference oscillator buffer output, as well as stand-by control through programming, and etc. Details are listed in the following. APPLICATIONS • Built-Pin crystal oscillator for mixer local oscillator • Mixer input frequency: 10 to 50 MHz • Up to 40 MHz PLL external crystal oscillator reference frequency under normal condition • 18-bit programmable input frequency divider (including a ¸ 64/65 prescaler) with divide ratio range from 4032 to 262143 • 13-bit programmable reference frequency divider (including a ¸ 8 prescaler) with divide ratio range from 40 to 65528 • Optional lock detector output (LD, fR/2, fV/2) • Charge pump output for passive low-pass filter • Wide tuning range of charge pump output for external VCO (VSS+0.5 to VDD2-0.5) • Switchover terminal for constant of loop filter or general open drain output • Reference oscillator buffer output • SSOP 28L package • Pager • Family radio service (FRS) • Wireless communication system BLOCK DIAGRAM Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan For:Natertech RX3408 APPLICATION CIRCUIT R12 DIODE D1 R14 C17 R10 R13 C20 MCU R8 R C16 To Audio Amp. R R C21 1 R6 R7 R R11 DEC C18 C19 R5 C15 C14 C13 C12 15 16 MIX OUT VCC LMTIN 455KHZ FLT 14 13 XSC1 DCP0 XSC0 12 18 10 11 VSS MIX IN QUAD DCP1 19 20 9 8 LD VDD1 FLTIN AUDOUT 21 22 FLTOUT FIN 7 SQUIN VSS 6 DO 5 4 XOUT 3 XIN 2 BO VDD2 RX3408 1 23 24 CLK SCANCTL 25 26 DATA 27 SW LE 28 R9 17 2 C28 C10 XTL Buffer Out To MCU C9 XTL1 C1 C2 XTL2 R1 R2 C7 Supply voltage C8 C11 BATTERY 1st IF-AMP C3 (21.4MHZ) C4 C6 C5 R3 R4 VCO (460MHZ) 1st MIXER (460MHZ) PA (460MHZ) LNA (460MHZ) RFSWITCH (460MHZ) V2.1 2 For:Natertech RX3408 ORDER INFORMATION Valid Part Number RX3408-LF Package Type Top Code 28 Pins, SSOP, 150mil RX3408-LF PIN CONFIGURATION V2.1 3 For:Natertech RX3408 PIN DESCRIPTION Pin Number 1 Name BO I/O O 2 XIN I 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 XOUT VDD2 DO VSS FIN VDD1 LD GND MIXIN XSC0 XSC1 MIXOUT VCC LMTIN DCP0 DCP1 QUAD AUDOUT FLTIN FLTOUT SQUIN O POWER O GND I POWER O GND I I O O POWER I 24 SCANCTL O 25 26 27 CLK DATA LE O I I 28 SW I I O I O I Description Terminal of reference crystal oscillator buffer output Reference crystal oscillator or external clock input with internally biased amplifier. (any external input to XIN must be ac-coupled) Reference crystal oscillator or external clock output Nominal 3.0 V supply voltage Single-ended charge pump output for passive low-pass filter PLL Ground VCO frequency input with internally biased input amplifier (any external input to FIN must be ac-coupled) Nominal 1.0 V supply voltage Lock detector output (high when PLL is locked) Ground Mixer input (3.3 KΩ input impedance) Oscillator input (base) Mixer output (1.8 KΩ output impedance) Nominal 3.0 V supply IF amplifier input (1.8 KΩ input impedance) IF amplifier de-coupling capacitor connection IF amplifier de-coupling capacitor connection Quadrature FM demodulator input Quadrature FM demodulator output Audio bandpass filter input Audio bandpass filter output Squelch circuit input Scan control output for LO. Output is high when squelch circuit input level is low. Shift register clock input Serial data input Latch enable input Switchover terminal for constant of loop filter or a general open drain output V2.1 4 For:Natertech RX3408 FUNCTION DESCRIPTION The RX3408 is a MCP (Multi Chip Package), it combines PTC RX3361 and FS8308. The IF receiver part (RX3361) incorporates a mixer, crystal-based local oscillator, IF amplifier, quadrature FM demodulator, audio filter, and a squelch circuit and is capable of demodulating FM input signals. The PLL part (FS8308) supports 20MHz to 500MHz frequency range. IF RECEIVER PART MIXER The mixer down converts frequency from the 1st IF input on pin MIXIN to the 455 KHz 2nd IF output on MIXOUT. The external 2nd IF filter should be chosen so that the specified output impedance on the mixer output port is an acceptable termination for the filter. CRYSTAL OSCILLATOR A single dc/dc coupled transistor is available as a two port gain element (pins XOSC0 & XOSC1) to implement a crystal oscillator. The device is biased on-chip to a constant dc current. IF AMPLIFIER The IF limiter amplify and limits the signal on pin LMTIN input from the external 2nd IF filter. The out put signal is a square wave that drives the following demodulator stage. Two off-chip decoupling capacitors to VCC are required on pins DCP0 & DCP1 to remove dc content from the limiter input. FM DEMODULATOR The demodulator provides an audio output generated by multiplying the input IF from the limiter with a quadrature of the input. The quadrature is generated by the combination of an on-chip 10pF series capacitor with an off-chip shunt LCR resonator connected between pin QUAD and VCC. Biasing for the input transistor connects to pin QUAD comes from the off-chip resonator. The shape of the demodulator S-curve is determined by the shunt resistance on this LCR resonator. An off-chip RC low pass filter should be used on pin AUDOUT for removal of the 2nd IF components. FILTER AMPLIFIER The filter amplifier provides an inverting gain element between pins FLTIN & FLTOUT for the implementation of an audio filter. Typically, a band-pass active filter is built by adding externally at least two resistors and two capacitors to this amplifier. An external dc path must be provided through the feedback network across these pins to set the dc operating point. The design equations are as follows: Where: fo is the desired center frequency, Q is the quality factor, Ao is the voltage gain at band center, R2 is the feedback resistance, C is the value for both capacitors, R1 the series input resistance and R2 the shunt resistance. V2.1 5 For:Natertech RX3408 PLL PART PROGRAMMABLE INPUT FREQUENCY DIVIDER The VCO input to the FIN pin is divided by the programmable divider and then internally output to the phase/frequency detector (PFD) as fv. The programmable input frequency divider consists of a÷64/65 (P/P+1) dual-modulus prescaler in prior to a 18-bit (N) counter, which is further comprised of a 6-bit swallow (A) counter, and a 12-bit main (B) counter. The total divide ratio, N, is related to values for P, A, and B through the relation N = (P + 1)×A +P ×(B –A) = P ×B +A , With B ≧ A. The minimum available programmable divisor for continuous counting is given by P ×(P – 1)=64 × 63=4032, and the valid total divide ratio range for the input divider is M = 4032 to 262143. Take N=10000 for example, since P=64 and hence that B=156 and A=16. Therefore, the binary codes of B and A should be 0000 1001 1100 and 010000, respectively. An alternative approach is to translate the decimal N into binary code directly. And then just take the last 6-bit as A and the remaining 12-bit as B. By far the binary code of N=10000 is 00 0010 0111 0001 0000. One can get the same result as the former method. PROGRAMMABLE REFERENCE FREQUENCY DIVIDER The crystal oscillator output is divided by the programmable divider and then internally output to the PFD as fR. The programmable reference frequency divider consists of a fixed ÷ 8 (S) prescaler and a 13-bit reference (R) counter. The total divide ratio, T, is related to values for S and R through the relation T = S×R = 8 ×R. The usable divisor range of the reference counter is R = 5 to 8191 and therefore, the valid total divide ratio range for the reference divider is T = 40 to 65528 (in steps of 8.) SERIAL INPUT DATA FORMAT The divisors of the input and reference dividers are input using a 20-bit serial interface consisting of separate clock (CLK), data (DATA), and latch enable (LE) lines. The format of the serial data is shown in the figure below LSB MSB Serial input data format DATA[17:0] CB[1:0] 19 2 1 0 The data on the DATA line is written to the shift register on the rising edge of the CLK signal and is input with MSB first. The last two bits are recognized as the latch select control bits. CB[1] X 0 1 CB[0] 0 1 1 Control Bit Setting Fetching Target of Serial Data Input N-counter PS and SW R-counter V2.1 6 For:Natertech RX3408 Data on the DATA line should be changed on the falling edge of CLK, and LE should be held low while data is being written to the shift register. Data is transferred from the shift register to either one of the frequency divider latches or the optional control latch when LE is set high. When the latch select control bits are set high-low or low-low, data is loaded to the 18-bit N-counter latch, and when the latch select control bits are set high-high, the 2 MSBs are ignored, the next 13 data bits are loaded to the 13-bit R-counter latch and the remaining 3 LSBs are used to control testing modes and should be set as follows for normal operation: LD[2] = high, LD[1] = low, LD[0] = low. To disable LD output (i.e. set LD low), LD[2] should be set low. The LD output control bits is shown in Table 6. When the latch select control bits are set low-high, the 2 MSBs are recognized as PS and SW, which are used as stand-by control and open drain output control, respectively. The detail of two control bits setting is summarized in Table 1. In normal work condition, PS is set to low. When PS is programmed to high, it will enter stand-by mode. The definition of the contents of the shift register relating to each particular latch location is listed in the table below. Serial data input format First bit Shift Register Bit Location Last bit 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 N-counter N [ 17:0 ] X 0 Optional PS SW Ignored 0 1 Control R-counter Ignored R [ 12:0 ] LD[2:0] 1 1 The 18-bit input (N) divider ratios are specified by the N [17:0] bits, respectively, and are defined in the table below. Input divider ratios N [17:0] Divide B[11:0] A [5:0] Ratio 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4032 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 4033 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ 262143 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Similarly, the Optional Control are specified by PS and SW bits, respectively, and are defined in the table below Data format for 2 optional bits Bit States PS Description H Stand-by mode L Normal work mode SW Open drain output control Similarly, the 13-bit reference (R) divider ratios are specified by the R[12:0] bits, respectively, and are defined in the table below Similarly, the 13-bit reference (R) divider ratios are specified by the R[12:0] bits, respectively, and are defined in the table below Reference divider ratios Divide Ratio R [12:0] 12 11 10 9 8 7 6 5 4 3 2 1 0 5 0 0 0 0 0 0 0 0 0 0 1 0 1 6 0 0 0 0 0 0 0 0 0 0 1 1 0 ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ ‧ 8191 1 1 1 1 1 1 1 1 1 1 1 1 1 V2.1 7 For:Natertech RX3408 The outputs selected by the LD[3:0] control bits for the multiplexed LD output pin are defined in the table below. LD output control bits LD[2] LD[1] LD[0] Output State DO Pin BO Pin R, bit 2 R, bit 1 R, bit 0 LD Pin 0 0 0 0 0 1 R-Divider/2 Output Tri-state 0 1 0 XOUT / R Output Tri-state 0 1 1 XOUT / 8 Output 1 0 0 Normal Mode (Lock Detector Output) 1 0 1 N-Divider/2 Output Tri-state 1 1 0 Test Mode Tri-state 1 1 1 XOUT / 8 Output Serial input data timing waveforms are shown in the figure below. Serial input data timing waveforms V2.1 8 For:Natertech RX3408 PHASE/FREQUENCY DETECTOR (PFD) The PFD compares an internal input frequency divider output signal, fV, with an internal reference frequency divider output signal, fR, and generates an error signal, DO, which is proportional to the phase error between fV and fR. The DO output is intended for use with a passive filter as shown in the figure below. Passive low-pass filter circuit LOCK DETECTOR (LD) When phase comparator detects phase difference, LD terminal outputs “L”. When phase comparator locks, LD terminal outputs “H”. On standby, outputs “H”. The criteria for lock condition are that the phase difference between fV and fR is less than 2/xin and continues for more than three consecutive times. The input/output waveforms for the PFD and LD are shown in the figure below. PFD input/output waveforms STAND-BY MODE The stand-by mode for the PLL is entered by programming the PS bit to high. In the standby mode, the XIN and FIN amplifiers, N-counter, and R-counter are stopped, as well as the internal current bias for charge pump block, the N- and R-counters are also reset, and the DO and DB outputs are set to the high impedance state. As long as voltage is supplied to VDD2, data loaded to the latches is kept. To exit from stand-by mode to normal operation, the PS bit must be programmed to low. REFERENCE CRYSTAL OSCILLATOR BUFFER OUTPUT (BO) This IC provides a reference crystal oscillator buffer output intended to be used as a crystal local oscillator to a 2nd mixer. The terminal is represented as BO. For cases to enhance the buffer output swing, increasing VDD1 will be an efficient way. Filter Switch Control (SW) Control of SW terminal by “SW” bit. This terminal is for switching time-constant of loop filter. Output type of this terminal is open drain output. When constant of loop filter doesn’t change by this switch, general open drain output is available. Note that there is an internal 200Ω resistor connected between and drain terminal and output pin. V2.1 9 For:Natertech RX3408 ABSOLUTE MAXIMUM RATINGS VSS = 0V Parameter Symbol VDD1 Rating VSS – 0.3 to VSS + 2 Unit V Supply Voltage VDD2 VSS – 0.3 to VSS + 6 V VSS – 0.3 to VSS + 6 V Input Voltage Range VCC VFIN VSS – 0.3 to VDD + 0 V Operating Temperature Range TOPR –30 to 70 ℃ Storage Temperature Range TSGT –65 to 150 ℃ Soldering Temperature Range TSLD 255 ℃ Soldering Time Range tSLD 10 Sec. RECOMMEND OPERATING CONDITIONS VSS = 0V Symbol Parameter Supply Voltage Range Value Unit Min. Typ. Max. VCC 2 3 6 V VDD1 0.95 1.0 2.0 V VDD2 2.4 3.6 3.0 V MIXIN Input Frequency fMIXIN Operating Temperature TA 10.7 -40 25 V2.1 MHz 85 ℃ 10 For:Natertech RX3408 ELECTRICAL CHARACTERISTICS VCC=VDD2=3.0V, VDD1=1.0V, VSS = 0V, CE = 3.0V. Temp =27 ℃, fo = 10.7MHz, fdev = +/- 3KHz, fm = 1KHz. Value Symbol Condition Parameter Min. Typ. Max. Unit DC Current Consumption, Un-muted Current Consumption, Muted IF Receiver Part ICC,UNM ICC,MUT SQUIN=1V SQUIN=0V - 4.0 5.4 - mA mA Input Limiting Sensitivity VLIM3dB - - 2.6 - uV Mixer Conversion Gain GMIX - - 28 - dB RMIX,IN CMIN,INn VAUD THD ZAUD GFLT VFLT VSC,UNM VSC,MUT VHYS - 130 40 0.5 2 - 3.3 9.0 170 0.86 450 50 0.7 0 2.9 45 210 0.9 0.4 100 KΩ pF mVrms % Ω dB V V V mV 20 - 500 MHz 7 -15 0.3 - 40 0.3 MHz dBm VPK-PK V Mixer Input Resistance Mixer Input Capacitance Audio Output Voltage Total Harmonic Distortion Audio Output Impedance Filter Amplifier Gain Filter Amplifier DC Output voltage Scan Control Output Level, Un-Muted Scan Control Output Level, Muted Squelch Circuit Hysteresis PLL Part MIXIN = 10mV rms Measured at AUDOUT AUDIO = 0.3V, 10KHz Measured at FLTOUT SQUIN=1V SQUIN=0V Referred to SQUIN FIN Operating Frequency Range fFIN XIN Operating Frequency Range FIN Input Voltage Swing XIN Input Voltage Swing CLK, DATA, LE Logic LOW Input Voltage CLK, DATA, LE Logic HIGH Input Voltage XIN Logic LOW Input Current fXIN PFIN VXIN VIL PFIN=-15dBm VDD1=1V, PS bit = “L” VDD1=1V - VIH - IIL,XIN VIL =0V IIH,XIN IIL,FIN IIH,FIN IDO IDO IOL IOH VIH = VDD1 VIL =0V VIH = VDD1 VDD2=3.0V, VDO=1.5V XIN Logic HIGH Input Current FIN Logic LOW Input Current FIN Logic HIGH Input Current Charge Pump Drive Current Charge Pump Sink Current LD, FV, FR Logic LOW Output Current LD, FV, FR Logic HIGH Output Current SW Logic LOW Output Current SW Logic HIGH Output Current DATA to CLK Setup Time CLK to LE Setup Time Hold Time ISW,OFF ISW,ON tSU1 tSU2 tHOLD - V2.1 VDD2 -0.3 - - - V - 10 uA 0.1 0.1 2 2 2 1.0 1.0 2.8 2.8 - 10 60 60 10 - uA uA uA mA mA mA mA uA mA us us us 11 For:Natertech RX3408 PACKAGE INFORMATIONS 28 PINS, SSOP, 150 MIL Symbol A A1 A2 b c D E E1 e L Min. 1.34 0.10 1.24 0.20 0.10 9.80 5.79 3.81 0.38 θ y 0° - Nom. 1.6 0.25 5.99 3.91 0.63 - Max. 1.75 0.25 1.52 0.30 0.25 10.00 6.19 3.98 1.27 8° 0.1 Notes : 1. Refer to JEDEC MO-137 2. Unit : mm V2.1 12 For:Natertech RX3408 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V2.1 13 For:Natertech