ETC FS8170

FS8170 2.5 GHz Low Power Phase-locked Loop IC
HiMARK Technology, Inc. reserves the right to change the product described in this datasheet. All information contained in this datasheet is subject to change without prior notice. HiMARK Technology, Inc. assumes no responsibility
for the use of any circuits shown in this datasheet.
Description
The FS8170 IC is a serial data input, fully programmable phase-locked loop with a 2.5
GHz prescaler for use in the local oscillator subsystem of radio transceivers. Multi-modulus division ratios of 32/33 and 64/65 are selectable thru serial programming to enable
pulse swallowing operation. When combined with an external VCO, the FS8170 becomes
the core of a very low power frequency synthesizer well-suited for mobile communication
applications, such as 2.4 GHz ISM-band wireless data links and cellular GSM and PCS.
The FS8170 is also pin compatible with Fujitsu’s MB15E07SL IC.
Features
!
!
!
!
!
!
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Maximum input frequency: 2.5 GHz
Supply voltage range from 2.4 V to 3.6 V
Low current consumption in locked state: 3.5 mA typ. (VCC = VP = 2.7 V, TA = +25 °C)
4.0 mA typ. (VCC = VP = 3.0 V, TA= +25 °C)
10 µA max. in asynchronous power-down mode
Digitally-filtered lock detect output
18-bit programmable input frequency divider using ÷ 32/33/64/65 multi-modulus prescaler with divide ratio range
from 992 to 65631 for ÷ 32/33 mode and from 4032 to 131135 for ÷ 64/65 mode
14-bit programmable reference frequency divider with divide ratio range from 3 to 16383
Programmable charge pump current: 1.5 mA or 6 mA
Pin compatible with Fujitsu MB15E07, MB15E07L, MB15E07SL
16 pin, plastic TSSOP (0.65 mm pitch)
Package and Pin Assignment
16 pin, plastic TSSOP (dimensions in mm)
16
2
15
3
4
5
6
7
8
HiMARK
Page 1
1
FS8170
XIN
XOUT
VP
VCC
DO
VSS
XFIN
FIN
14
13
12
11
10
9
φR
φP
FOLD
ZC
EN
LE
DATA
CLK
May 2003
FS8170
Pin Descriptions
Number
Name
I/O
Description
1
XIN
I
Reference crystal oscillator or external clock input with internally biased amplifier
2
XOUT
O
Reference crystal oscillator output
3
VP
—
Power supply voltage for the charge pump
4
VCC
—
Power supply voltage
5
DO
O
Single-ended charge pump output
6
VSS
—
Ground
7
XFIN
I
Complementary input for prescaler (normally ac-bypassed via a capacitor)
8
FIN
I
VCO frequency input with internally biased input amplifier
9
CLK
I
Shift register clock input
10
DATA
I
Serial data input
11
LE
I
Load enable signal input
12
EN
I
Power-down control
13
ZC
I
Forced high-impedance control for the charge pump
14
FOLD
O
Multiplexed CMOS level output (see Functional Description section for programming information)
15
φP
O
Phase comparator N-channel open drain output for an external charge pump
16
φR
O
Phase comparator CMOS inverter output for an external charge pump
Functional Block Diagram
FIN
XFIN
N-PRESCALER
N-COUNTER
φR
φP
N-LATCH
DATA
CLK
LE
CONTROL
LOGIC
SHIFT REGISTER
PFD
CHARGE
PUMP
DO
ZC
R-LATCH
EN
LOCK
DETECTOR
XIN
XOUT
OSC
LD MUX
FOLD
R-COUNTER
Page 2
May 2003
FS8170
Absolute Maximum Ratings
VSS = 0 V
Parameter
Symbol
Rating
Unit
VCC
VSS – 0.3 to VSS + 4.0
V
VP
VCC to 6.0
V
VFIN
VSS – 0.5 to VDD + 0.5
V
VO
VSS to VCC
V
VDO
VSS to VP
V
Storage temperature range
TSTG
–55 to 125
°C
Soldering temperature range
TSLD
260
°C
Soldering time range
tSLD
4
s
3500
eV
Supply voltage range
Input voltage range
Output voltage range
ESD rating (human body mode)
Recommended Operating Conditions
VSS = 0 V
Value
Parameter
Symbol
Unit
min.
typ.
max.
VCC
2.4
3.0
3.6
V
VP
Vcc
–
5.5
V
TA
–40
25
80
°C
Supply voltage range
Operating temperature
Page 3
May 2003
FS8170
Electrical Characteristics
(VCC = VP = 3.0 V, VSS = 0 V, TA = –40 to 85 °C unless otherwise noted)
Value
Parameter
Symbol
Condition
Unit
min.
typ.
max.
GENERAL
ICC,total
fin = 2.5 GHz
ICC,standby
ZC = “H” or open
FIN operating frequency
fFIN
VFIN = 0.3 Vpk-pk sinusoid
XIN operating frequency
fXIN
Input sensitivity
PFIN
XIN input voltage swing
VXIN
Power supply current consumption
Standby current consumption
50 Ω measurement system
4
mA
10
µA
50
2500
MHz
3
40
MHz
-15
+2
dBm
0.5
VCC
Vpk-pk
CHARGE PUMP
IDOsource
VDO = VP/2, CS bit = “H”
-6
mA
IDOsink
VDO = VP/2, CS bit = “H”
6
mA
IDOsource
VDO = VP/2, CS bit = “L”
-1.5
mA
IDOsink
VDO = VP/2, CS bit = “L”
1.5
mA
RF charge pump output current
DIGITAL INTERFACE (DATA, CLK, LE, PS, ZC)
High-level input voltage
VIH
Low-level input voltage
VIL
High-level input current
IIH
VIH = VCC = 3.6V
Low-level input current
IIL
VIL = 0 V, VCC = 3.6V
XIN logic HIGH input current
IIH,XIN
VIH = VDD
XIN logic LOW input current
IIL,XIN
VIL = 0 V
φP logic LOW output voltage
VOL
Open drain output
φP logic LOW output current
IOL
Open drain output
1
mA
φR logic HIGH output voltage
VOH
VCC = VP = 3.0 V, IOH = –1 mA
VCC –
0.4
V
φR logic LOW output voltage
VOL
VCC = VP = 3.0 V, IOL = 1 mA
0.4
V
φR logic HIGH output current
IOH
VCC = VP = 3.0 V
–1
mA
φR logic LOW output current
IOL
VCC = VP = 3.0 V
V
0.8×VCC
Page 4
0.2×VCC
V
–1
1
µA
–1
1
µA
100
µA
µA
–100
0.4
1
V
mA
May 2003
FS8170
Electrical Characteristics
(VCC = VP = 3.0 V, VSS = 0 V, TA = –40 to 85 °C unless otherwise noted)
Value
Parameter
Symbol
Condition
Unit
min.
typ.
max.
VCC –
0.4
FOLD logic HIGH output voltage
VOH
VCC = VP = 3.0 V, IOH = –1 mA
FOLD logic LOW output voltage
VOL
VCC = VP = 3.0 V, IOL = 1 mA
0.4
V
FOLD logic HIGH output current
VOH
VCC = VP = 3.0 V
–1
mA
FOLD logic LOW output current
VOL
VCC = VP = 3.0 V
V
1
mA
MICROWIRE TIMING
DATA to CLK setup time
tSU1
10
ns
DATA to CLK hold time
tHOLD1
10
ns
CLK to LE setup time
tSU2
20
ns
CLK to LE hold time
tHOLD2
30
ns
tEW
50
ns
LE Pulse width
Page 5
May 2003
FS8170
Functional Description
Programmable Input Frequency Divider
The VCO output to the FIN pin is divided by the programmable divider and then internally output to the phase/frequency detector (PFD) as fV. The programmable input frequency divider consists of a multi-modulus (selectable ÷ 32/33 or ÷ 64/65 (M/M+1))
prescaler and a 18-bit N-counter, which is further comprised of a 7-bit swallow A-counter,
and a 11-bit main B-counter. The total divide ratio, N, is related to values for M, A, and B
through the relation
N = ( M + 1 ) × A + M × ( B – A ) = M × B + A,
with B ≥ A. The minimum programmable divisor for continuous counting is given by
M × ( M – 1 ) , and is 32 × ( 32 – 1 ) = 992 for the ÷ 32/33 prescaler mode, and is
64 × ( 64 – 1 ) = 4032 for the ÷ 64/65 mode. Hence, the valid total divide ratio range for
the input divider is N = 992 to 65631 for the ÷ 32/33 mode and N = 4032 to 131135 for
the ÷ 64/65 mode.
Programmable Reference Frequency Divider
The crystal oscillator output is divided by the programmable reference divider and then
internally output to the PFD as fR. The programmable reference frequency divider consists of a 14-bit reference R-counter. Becasue of its specific design, the minimum acceptable divisor for R is 3, and hence the total divide ratio, R, ranges from 3 to 16383.
Shift Register Configuration
The divide ratios for the input and reference dividers are input using a 19-bit serial interface consisting of separate clock (CLK), data (DATA), and load enable (LE) lines. The
format of the serial data is shown in Table 1. The data on the DATA line is written to the
shift register on the rising edge of the CLK signal and is input with MSB first, and the last
bit is used as the latch select control bit. The data on the DATA line should be changed on
the falling edge of CLK, and LE should be held LOW while data is being written to the
shift register. Data is transferred from the shift register to one of the frequency divider
latches when LE is set HIGH. When the latch select control bit is set LOW, data is loaded
to the 18-bit N-counter latch, and when the latch select control bit is set HIGH, the 4
MSBs are recognized as CS, LDS, FC, SW, respectively, and the next 14 data bits are
loaded to the 14-bit R-counter latch. The definition of the 4 MSBs will be described in
Table 5 and 6. Note that LDS should be set LOW for normal operation.
Also, serial input data timing waveforms are shown in Fig. 1.
Page 6
May 2003
FS8170
Fig. 1 – Serial data input waveforms
DATA
tHOLD1
tSU1
CLK
tSU2
MSB
CONTROL
BIT
LE
DATA
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
CLK
LE
Parameter
Min.
Typ.
Max.
Unit
tSU1
10
–
–
ns
tSU2
20
–
–
ns
tHOLD1
10
–
–
ns
LSB
MSB
Data Flow
Table 1: Serial data input format
1
C
B
CB
A1 to A7
B1 to B11
R1 to R14
SW
FC
LDS
CS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
10
R
11
R
12
R
13
R
14
S
W
F
C
L
D
S
C
S
Control bit for selecting the N or R latch
Control bits for setting the divide ratio of the programmable swallow counter (0 to 127)
Control bits for setting the divide ratio of the programmable main counter (3 to 2047)
Control bits for setting the divide ratio of the programmable reference counter (3 to 16383)
Control bit for setting the divide ratio of the prescaler (32/33 or 64/65)
Control bit for setting the polarity of the phase/frequency detector
Control bit for selecting the output for the FOLD pin
Control bit for setting the charge pump current level
Page 7
May 2003
FS8170
Table 2: Binary 7-bit data format for swallow counter
Divide
ratio
(A)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
.
.
.
.
.
.
.
.
127
1
1
1
1
1
1
1
Table 3: Binary 11-bit data format for main counter
Divide
ratio
(B)
N
11
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
.
.
.
.
.
.
.
.
.
.
.
.
2047
1
1
1
1
1
1
1
1
1
1
1
Table 4: Binary 14-bit data format for reference counter
Divide
ratio
(R)
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
1
0
0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 5: Data format for 3 optional bits
Bit
H
L
Description
SW
32/33
64/65
Prescaler dual-modulus ratio setting
CS
+ 6 mA
+ 1.5 mA
Charge pump current setting
LDS
FO signal
LD signal
FOLD output select setting
Page 8
May 2003
FS8170
Table 6: Data format for FC bit (LDS = HIGH)
FC = HIGH
DO
φR
φP
fR > fV
H
L
L
fR < fV
L
H
Z
fR = fV
Z
L
Z
FC = LOW
FOLD
FOLD =
fR
DO
φR
φP
L
H
Za
H
L
L
Z
L
Z
FOLD
FOLD =
fV
a. Z denotes high impedance state
Phase/Frequency Detector (PFD)
The PFD compares an internal input frequency divider output signal, fV, with an internal
reference frequency divider output signal, fR, and generates an error signal, DO, which is
proportional to the phase error between fV and fR. The DO output is intended for use with
a passive filter as shown in Fig. 2 (a). The polarity of DO is selectable by setting the bit FC
to high or low. The setting should depend on the frequency-voltage characteristic of external VCO as depicted in Fig. 2 (b).
The input/output waveforms for the PFD are shown in Fig. 3.
Fig. 2 – Low-pass filter and external VCO frequency-voltage characteristic
VCO
DO
(1)
fVCO
(2)
VDO
(b) VCO frequency-voltage characteristic
(a) Passive low-pass filter
Note: If VCO has a positive tuning curve similiar to trace
(1), set FC = “H,” otherwise if the VCO has a negative
tuning curve similar to trace (2), set FC = “L.”
Page 9
May 2003
FS8170
Fig. 3 – Phase comparator output waveforms
fR
fV
LD
[FC=”H”]
DO
[FC=”L”]
DO
1.
2.
3.
4.
Pulses of finite width on DO output are generated during locked state to prevent dead zone.
A “locked” condition (LD is HIGH) is indicated when the phase error is less than t1 or t2 at least for
3 consecutive comparison cycles, otherwise an “unlocked” condition (LD is LOW) is indicated.
The values of t1 and t2 depend on the XIN input frequency:
t1 > 2/fosc (e.g. t1 > 250 ns, if fXIN = 8 MHz)
t2 > 2/fosc (e.g. t2 > 250 ns, if fXIN = 8 MHz)
LD becomes HIGH during power-down mode (when EN is set LOW).
Charge Pump (CP)
The phase error signal, DO, generated from the PFD will pump charge into an external
loop filter, which then converts the charge to produce the VCO’s tuning voltage. With a
constant pumping rate, the shift of the VCO’s tuning voltage will be directly proportional
to the phase error signal DO. Two pumping rates, 1.5 mA and 6 mA, are provided by the
chip and are selectable through the bit CS as defined previously in Table 5. Also, the
charge pump characteristics corresponding to both modes are shown in the Typical Characteristics section. The internal charge pump may be turned off by the pin ZC. When ZC
is set low, the internal charge pump will stay in its high-impedance state and will not pump
any charge into the external LPF. In this case, the user is allowed to utilize one’s own
charge pump by two control pins φP and φR which are defined in Table 6. φP and φR are
the error signals directly proportional to the positive/negative phase error when FC = “H.”
When FC = “L,” the relation becomes negative/positive.
Table 7: Setting for the pin ZC
ZC
Do Output
H
Normal output
L
High impedance
Page 10
May 2003
FS8170
Multi-function Lock Detect Output (FOLD)
A digital lock detect function is included with the phase detector through an internal digital filter to produce a logic level output which is available on the FOLD output pin. The
criterion of lock indication depends on the period of the crystal oscillator reference. The
lock dectect output is HIGH whenever the phase error between phase detector inputs is
less than 2 times of the crystal period for more than three consecutive comparison cycles,
otherwise is low. Note that LD becomes HIGH during the power saving mode. The LD
output is depicted in Fig. 3 as well.
Power-down Control (EN)
By setting the pin EN to LOW, the chip enters into power-down mode, reducing the current consumption. During the power-down mode, the phase detector output, DO, is set to
its high impedance. Normal operation mode resumes when EN is switched to HIGH. To
prove a smooth start-up condition, an intermittent control circuit is activated when the
device returns to normal operation. Due to the unknown relationship between fV and fR
after returning from power-down, the PFD output is unpredictable and may give rise to a
significant jump in the VCO’s frequency which will result in an increased lock-up time.
To prevent this, the FS8170 employs an intermittent control circuit to limit the magnitude
of the error signal generated by the phase detector when it returns to normal operation,
thus ensuring a much quicker return to the fully phase-locked condition.
Table 8: Setting for the pin EN
EN
Status
H
Normal operation mode
L
Power-down mode
Page 11
May 2003
FS8170
Measurement Circuit Setup
The circuit shown in Fig. 4 is used for measuring the input sensitivity of the FIN input of
the PLL.
Fig. 4 – FIN input sensitivity test circuit
1000pF
0.1µF
1000pF
1000pF
S.G.
S.G.
50Ω
FIN XFIN VSS
DO
VCC VP XOUT XIN
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
EN
ZC FOLD
φP
φR
CLK
DATA LE
From Controller
Vcc
Page 12
50Ω
To Counter
May 2003
FS8170
Typical Characteristics
FIN Input Sensitivity
Fig. 5 – Input sensitivity vs. frequency
FIN Input Sensitivity (Prescaler: 64/65)
5
0
Sensitivity (dBm)
-5
SPEC
-10
-15
-20
-25
-30
Vcc=2.4V
Vcc=3.0V
Vcc=3.6V
-35
-40
-45
-50
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
FIN (GHz)
FIN Input Sensitivity (Prescaler: 32/33)
5
0
Sensitivity (dBm)
-5
SPEC
-10
-15
-20
-25
-30
-35
Vcc=2.4V
Vcc=3.0V
Vcc=3.6V
-40
-45
-50
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
FIN (GHz)
Page 13
May 2003
FS8170
XIN Input Sensitivity
Fig. 6 – XIN input sensitivity vs. frequency
XIN Input Sensitivity
10
Sensitivity (dBm)
5
SPEC
0
-5
-10
-15
Vcc=2.4V
Vcc=3.0V
Vcc=3.6V
-20
-25
-30
-35
0
50
100
150
200
250
XIN (MHz)
Page 14
May 2003
FS8170
Charge Pump Characteristic
Fig. 7 – Charge pump current vs. VDO
Low Current Mode (Ido=1.5mA)
2.0
1.5
Ido (mA)
1.0
Source State : FR>FV, FC Positive
0.5
0.0
-0.5
Sink State : FR>FV , FC Negative
-1.0
-1.5
-2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Vdo (V)
High Current Mode (Ido=6mA)
8
6
Ido (mA)
4
Source State : FR>FV, FC Positive
2
0
-2
Sink State : FR>FV , FC Negative
-4
-6
-8
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Vdo (V)
Page 15
May 2003
FS8170
Supply Voltage Dependence of Charge Pump Current
Fig. 8 – Charge pump current vs. supply voltage at VDO = VP/2
Low Current Mode (1.5mA mode)
2.0
1.9
VDO = 1/2 VP
1.8
IDO (mA)
1.7
1.6
1.5
Sink Current
Source Current
1.4
1.3
1.2
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
VP (V)
High Current Mode (6.0mA mode)
7.2
7.0
6.8
VDO = 1/2 VP
6.6
IDO (mA)
6.4
6.2
6.0
Sink Current
Source Current
5.8
5.6
5.4
5.2
5.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
VP (V)
Page 16
May 2003
FS8170
Appication Circuit
VP
10K
12K
33pF
Xtal
VP
XOUT
φP
VP
VCC
FOLD
VCC
0.1µF
HiMARK
FS8170
33pF
XIN
φR
1µF
DO
VSS
1000pF
XFIN
FIN
12K
10K
Lock
Detect
ZC
EN
LE
DATA
M
C
U
CLK
1000pF
VCO
Page 17
May 2003