TOSHIBA TC74HCT652AP_07

TC74HCT652AP
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74HCT652AP
Octal Bus Transceiver/Register (3-state)
The TC74HCT652A is high speed CMOS OCTAL BUS
TRANSCEIVER/REGISTER fabricated with silicon gate C2MOS
technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
Its inputs are compatible with TTL, NMOS, and CMOS output
voltage levels.
This device is bus transceiver with 3-state outputs, D-type
flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the internal registers.
ALL inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Weight: 1.50 g (typ.)
Features (Note 1) (Note 2)
•
High speed: fmax = 60 MHz (typ.) at VCC = 5 V
•
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
•
Compatible with TTL output: VIH = 2.0 V (min)
•
Output drive capability: 15 LSTTL loads
•
•
Symmetrical output impedance: |IOH| = IOL = 6 mA (min)
Balanced propagation delays: tpLH ∼
− tpHL
•
Pin and function compatible with 74LS652
VIL = 0.8 V (max)
Note 1: Do not apply a signal to any bus terminal when it is in the out put mode. Damage may result.
Note 2: All floating (high impedance) bus terminals must have their input levels fixed by means of pull up or pull
down resistors.
Pin Assignment
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IEC Logic Symbol
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Truth Table
GAB
L
GBA
H
CAB
CBA
X
X
(Note)
(Note)
X
X
(Note)
(Note)
X
H
(Note)
H
X
X
(Note)
(Note)
X
(Note)
X
X
(Note)
(Note)
X
L
L
(Note)
X
X
(Note)
(Note)
X
(Note)
H
L
X
X
(Note)
(Note)
SAB
SBA
X
X
X
X
L
X
L
X
H
X
H
X
X
L
X
L
X
H
X
H
H
H
A
B
Inputs
Inputs
Z
Z
X
X
Inputs
Outputs
L
L
H
H
L
L
H
H
X
Qn
L
L
H
H
Outputs
Inputs
L
L
H
H
L
L
H
H
Qn
X
L
L
H
H
Outputs
Outputs
Qn
Qn
Function
The output functions of A and B busses are
disabled.
Both A and B busses are used as inputs to the
internal flip-flops. Data on the bus will be stored
on the rising edge of the clock.
The data on the A bus are displayed on the B bus.
The data on the A bus are displayed on the B bus,
and are stored into the A storage flip-flops on the
rising edge of CAB.
The data in the A storage flip-flops are displayed
on the B bus.
The data on the A bus are stored into the A
storage flip-flops on the rising edge of CAB, and
the stored data propagate directly onto the B bus.
The data on the B bus are displayed on the A bus.
The data on the B bus are displayed on the A bus,
and are stored into the B storage flip-flops on the
rising edge of CBA.
The data in the B storage flip-flops are displayed
on the A bus.
The data on the B bus are stored into the B
storage flip-flops on the rising edge of CBA, and
the stored data propagate directly onto the A bus.
The data stored to the internal flip-flops are
displayed at the A and B bus respectively.
X: Don’t care
Qn: The data stored into the internal flip-flops by most recent low to high transition of the clock inputs.
Z: High impedance
Note:
The clock are not internally gated with either GAB or GBA . Therefore, data on the A and/or B busses may
be clocked into the storage flip-flops at any time.
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Timing Chart
System Diagram
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Absolute Maximum Ratings (Note 1)
Characteristics
Symbol
Rating
Unit
Supply voltage range
VCC
−0.5~7.0
V
DC input voltage
VIN
−0.5~VCC + 0.5
V
VOUT
−0.5~VCC + 0.5
V
Input diode current
IIK
±20
mA
Output diode current
IOK
±20
mA
DC output current
IOUT
±35
mA
DC VCC/ground current
ICC
±75
mA
Power dissipation
PD
500 (DIP)
Storage temperature
Tstg
−65∼150
DC output voltage
(Note 2)
mW
°C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C should be
applied up to 300 mW.
Operating Ranges (Note)
Characteristics
Symbol
Rating
Unit
Supply voltage
VCC
4.5~5.5
V
Input voltage
VIN
0~VCC
V
VOUT
0~VCC
V
Operating temperature
Topr
−40~85
°C
Input rise and fall time
tr, tf
0~500
ns
Output voltage
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
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Electrical Characteristics
DC Characteristics
Characteristics
Ta = 25°C
Test Condition
Symbol
Ta = −40~85°C
VCC (V)
Min
Typ.
Max
Min
Max
Unit
High-level input
voltage
VIH
⎯
4.5~5.5
2.0
⎯
⎯
2.0
⎯
V
Low-level input
voltage
VIL
⎯
4.5~5.5
⎯
⎯
0.8
⎯
0.8
V
High-level output
voltage
VOH
IOH = −20 μA
VIN
= VIH or VIL I
OH = −6 mA
4.5
4.4
4.5
⎯
4.4
⎯
4.5
4.18
4.31
⎯
4.13
⎯
Low-level output
voltage
VOL
IOL = 20 μA
VIN
= VIH or VIL I = 6 mA
OL
4.5
⎯
0.0
0.1
⎯
0.1
4.5
⎯
0.17
0.26
⎯
0.33
3-state output off
state current
IOZ
5.5
⎯
⎯
±0.5
⎯
±5.0
μA
Input leakage
current
IIN
VIN = VCC or GND
5.5
⎯
⎯
±0.1
⎯
±1.0
μA
ICC
VIN = VCC or GND
5.5
⎯
⎯
4.0
⎯
40.0
μA
Per input: VIN = 0.5 V or 2.4 V
Other input: VCC or GND
5.5
⎯
⎯
2.0
⎯
2.9
mA
Ta =
−40
~85°C
Unit
Quiescent supply
current
IC
VIN = VIH or VIL
VOUT = VCC or GND
V
V
Timing Requirements (input: tr = tf = 6 ns)
Characteristics
Symbol
Minimum pulse width
tW (L)
(CK)
tW (H)
Ta = 25°C
Test Condition
⎯
Minimum set-up time
ts
⎯
Minimum hold time
th
⎯
Clock frequency
f
⎯
6
VCC (V)
Typ.
Limit
Limit
4.5
⎯
15
19
5.5
⎯
14
17
4.5
⎯
10
13
5.5
⎯
9
12
4.5
⎯
5
5
5.5
⎯
5
5
4.5
⎯
31
25
5.5
⎯
37
30
ns
ns
ns
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AC Characteristics (input: tr = tf = 6 ns)
Characteristics
Output transition time
tpLH
(BUS-bus)
Propagation delay
time
tpLH
(CAB, CBA-bus)
tpHL
Propagation delay
time
tpLH
(SAB, SBA-bus)
tpHL
Output enable time
tpZL
(GAB, GBA -bus)
tpZH
Output enable time
tpLZ
(GAB, GBA -bus)
tpHZ
Maximum clock
frequency
fmax
Input capacitance
CIN
Power dissipation
capacitance
Note:
COUT
CPD
(Note)
Ta = −40~85°C
Unit
Min
Typ.
Max
Min
Max
4.5
⎯
7
12
⎯
15
5.5
⎯
6
11
⎯
14
4.5
⎯
20
30
⎯
38
5.5
⎯
17
27
⎯
34
4.5
⎯
25
38
⎯
48
5.5
⎯
22
34
⎯
43
4.5
⎯
29
44
⎯
55
5.5
⎯
26
40
⎯
50
4.5
⎯
34
52
⎯
65
5.5
⎯
31
47
⎯
59
4.5
⎯
24
34
⎯
43
5.5
⎯
21
31
⎯
39
4.5
⎯
29
42
⎯
53
5.5
⎯
26
38
⎯
48
4.5
⎯
22
33
⎯
41
5.5
⎯
20
30
⎯
37
4.5
⎯
27
41
⎯
51
5.5
⎯
24
37
⎯
46
4.5
⎯
24
35
⎯
44
5.5
⎯
22
32
⎯
40
4.5
31
55
⎯
25
⎯
5.5
37
61
⎯
30
⎯
GAB, GBA , SAB, SBA, CAB, CBA
⎯
5
10
⎯
10
pF
An, Bn
⎯
13
⎯
⎯
⎯
pF
⎯
39
⎯
⎯
⎯
pF
⎯
tTHL
tpHL
Output capacitance
CL (pF) VCC (V)
tTLH
Propagation delay
time
Ta = 25°C
Test Condition
Symbol
50
50
⎯
150
50
⎯
150
50
⎯
150
50
RL = 1 kΩ
150
RL = 1 kΩ
50
⎯
50
⎯
ns
ns
ns
ns
ns
ns
MHz
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD・VCC・fIN + ICC/8 (per bit)
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Package Dimensions
Weight: 1.50 g (typ.)
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RESTRICTIONS ON PRODUCT USE
20070701-EN GENERAL
• The information contained herein is subject to change without notice.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc.
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
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document shall be made at the customer’s own risk.
• The products described in this document shall not be used or embedded to any downstream products of which
manufacture, use and/or sale are prohibited under any applicable laws and regulations.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patents or other rights of
TOSHIBA or the third parties.
• Please contact your sales representative for product-by-product details in this document regarding RoHS
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that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses
occurring as a result of noncompliance with applicable laws and regulations.
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