TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 D D D D D D D Three Separate Loops: 1 UHF and 2 VHF Operation to 1.2-GHz for Main Synthesizer Operation to 250 MHz for Auxiliary Synthesizers Fast Lock-up Time High-Speed Serial Data Bus Low Power Consumption Ideal for Global Systems for Mobile Communications (GSM) Applications description PW PACKAGE (TOP VIEW) VDD CLOCK DATA STROBE LD VSS REF_IN VSSP PDA2 SW2 VDDP2 AUX2_IN 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 AUX1_IN VDDP1 PDA1 SW1 RPA VDDA SWM PDM VSSA RPM VDDPM RF_IN The Texas Instruments (TI) TRF2020 is an integrated high performance frequency synthesizer device. The TRF2020 consists of one main 1.2-GHz synthesizer and two auxiliary 250-MHz synthesizers. Each synthesizer has an independent dual-modulus prescaler and separate powerdown modes. These features provide maximum flexibility for the design of 900-MHz wireless systems. The main synthesizer consists of a 32/33-modulus prescaler with an 11-bit counter, a phase-frequency detector, and a charge pump. The phase-frequency detector is referenced to an internal reference frequency that is derived from an external TCXO signal. The phase-frequency detector is also provided with a dead-zone compensation circuit that reduces synthesizer phase noise during locked conditions. Each auxiliary synthesizer consists of an independent 8/9-modulus prescaler with an 11-bit counter, a phase-frequency detector, and a charge pump. Similar to the main synthesizer, each auxiliary synthesizer’s phase-frequency detector is referenced to an internal reference frequency that is derived from an external TCXO signal. The external TCXO signal is prescaled by an 11-bit counter and then distributed to three independent postscalers. Each postscaler provides a selectable, divide-by-1, -2, -4, or -8 function before the reference signal is distributed to the associated synthesizer phase detector. The reference frequency prescaler and independent postscalers are software programmable. To achieve minimum lock-up time, each synthesizer contains a speed-up mode charge pump capable of providing 2 mA output current and an analog switch that can change the loop-filter time constant. The duration of the speed-up mode operations can be independently controlled with software. The states of the three internal lock detectors are provided on a programmable, combinational logic output; each synthesizer can be selected independently or ANDed together. The device is programmed over a three- wire, synchronous, serial data bus (clock, data, strobe) with achievable bit rates as high as 20 Mbits/sec. The data is partitioned into words in such a manner that static parameters may be sent once during initialization, and dynamic parameters, such as frequency, may be sent as often as needed. The TRF2020 is offered in a 24-pin plastic thin-shrink small-outline package (TSSOP) and is characterized for free-air operation from – 40°C to 85°C. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 functional block diagram R R RF_IN 1/32, 33 Prescaler 13 5-Bit Counter 11-Bit Counter 15 F 2 Phase Detector Charge Pump 5 AUX1_IN 24 R 1/8, 9 Prescaler 5 Lock Detect 11-Bit Counter 21 Control Logic Phase Detector 3 T AUX2_IN 12 S 1/8, 9 Prescaler 3-Bit Counter K Speed-Up Counter 19 2 20 Current Reference 10 G Control Logic 3 T L M N 2 H VSSA VDDA RPA Phase Detector 9 Charge Pump 1 T AUX-1 Reference Select 2 AUX-2 Reference Select ÷2 SW2 11 J Main Reference Select 2 ÷1 7 PDA1 16 S 11-Bit Counter SW1 6 14 VDDPM 23 VDDP1 11 VDDP2 8 VSSP REF_IN E LD 22 Charge Pump 11 D PDM 2 C B 3-Bit Counter SWM U 6 11 A 17 RPM Speed-Up Counter Control Logic S 18 ÷4 ÷8 11-Bit Reference Counter 11 P 2 Speed-Up Counter Reference Counter Power Enable Lock Detect Select Test Mode K 6 G 6 4 PDA2 VDD VSS STROBE Address Decoder Word-3 AUX-2 Synthesizer Reference Postscaler Select Auxiliary Current Ratio Word-2 AUX-1 Synthesizer Auxiliary Speed-Up Main Current Ratio Word-1 Main Synthesizer Word-0 3 22-Bit Shift Register DATA 2 Bit 2 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CLOCK TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AUX1_IN 24 I RF input auxiliary-1 synthesizer AUX2_IN 12 I RF input auxiliary-2 synthesizer CLOCK 2 I Clock input DATA 3 I Data input LD 5 O Lock detect output PDA1 22 O Auxiliary-1 synthesizer phase detector output PDA2 9 O Auxiliary-2 synthesizer phase detector output PDM 17 O Main synthesizer phase detector output REF_IN 7 I Reference input RF_IN 13 I Main synthesizer RF input RPA 20 I Reference current input for AUX-1 and AUX-2 charge pumps RPM 15 I Reference current input for main charge pump STROBE 4 I Strobe input SWM 18 O Main analog switch output SW1 21 O Auxiliary-1 analog switch output SW2 10 O Auxiliary-2 analog switch output VDD VDDA 1 Digital supply voltage 19 Analog supply voltage VDDPM VDDP1 14 Main prescaler supply voltage 23 Auxiliary-1 prescaler supply voltage VDDP2 VSS 11 Auxiliary-2 prescaler supply voltage 6 Digital ground VSSA VSSP 16 Analog ground 8 Prescaler ground absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage VDDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.6 V Supply voltage VDD, VDDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 6 V Voltage applied to any other pin, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Power dissipation at or below TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mW Junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Ambient operating temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature, TSTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions MIN NOM MAX UNIT VDDA VDD, VDDP Analog supply voltage 2.75 3 4.5 Digital supply voltage 2.75 3 3.6 V TA TJ Operating free-air temperature – 40 25 85 °C Junction temperature – 30 105 °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 3 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 electrical characteristics with VDDA = 4.5 V, VDDP = VDD = 3 V, TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS TYP MAX (see Note 1) 11 13 10 µA (see Note 1) 6 8 mA R = 0, S = 1, T = 0 (see Note 1) 3.3 4.5 mA IOPER ISTDBY Operational supply current R=S=T=1 Maximum standby current R=S=T=0 IDDPM IDDP1 Main synthesizer operational supply current R = 1, S = T = 0 Auxiliary-1 synthesizer operational supply current MIN UNIT mA IDDP2 Auxiliary-2 synthesizer operational supply current R = 0, S = 0, T = 1 (see Note 1) 3.3 4.5 mA NOTES: 1. Operational supply currents measured with RF_IN = 1200 MHz, AUX1_IN = 250 MHz, AUX2_IN = 250 MHz, fREF_IN = 39.6 MHz. All loops are in lock condition and normal mode. Operational supply current = IOPER = IDDA + IDDP1 + IDDP2 + IDDPM + IDD digital interface characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.7 VDD VDD V 0 0.3 VDD V 0 1 µA 0 1 µA Clock VIH High-level input voltage Data Strobe Clock VIL Low-level input voltage Data Strobe Clock ť IIH ť High-level input current Data Strobe Clock IIL Low-level input current VOH VOL High-level output voltage LD Low-level output voltage LD ť ť Data Strobe IOH = 1 mA IOH = –2 mA VDD – 0.4 V 0.4 V ac electrical characteristics with VDDA = 4.5 V, VDDP = VDD = 3 V, TA = 25°C (unless otherwise noted) main loop, RF_IN PARAMETER TEST CONDITIONS fRF_IN Input signal frequency 2.75 ≤ VDDP ≤ 3.5 V PRF_IN Input sensitivity 2.75 ≤ VDDP ≤ 3.5 V, Rsource = 50 Ω fCOMP Phase detector comparison 2.75 ≤ VDD ≤ 3.5 V MIN TYP MAX UNIT 1200 MHz – 20 0 dBm 0 2 MHz MAX UNIT 250 MHz – 20 0 dBm 0 2 MHz auxiliary loops, AUX1_IN and AUX2_IN PARAMETER fAUX_IN TEST CONDITIONS 2.75 ≤ VDDP ≤ 3.5 V Input signal frequency PAUX_IN Input sensitivity 2.75 ≤ VDDP ≤ 3.5 V, Rsource = 50 Ω fAUX_ COMP 2.75 ≤ VDD ≤ 3.5 V 4 MIN Phase detector comparison POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 reference divider, REF_IN PARAMETER fREF_IN VREF_IN Input signal frequency ZREF IN REF_IN Input impedance TEST CONDITIONS MIN TYP MAX 2.75 ≤ VDDP ≤ 3.5 V UNIT 40 Input sensitivity 0.3 MHz VDDP – 0.8 Resistive Capacitive Vp–p 100 kΩ 3 pF charge pump characteristics ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ D ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ D ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ D ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ main charge pump output TEST CONDITIONS† PARAMETER normal mode |IPDM| Output current PDM I PDM |I PDM| Relative output current variation PDM (see Figure 1) RPM 5% tolerance, VSSA + 0.5 ≤ VPDM ≤ VDDA – 0.5 ∆IPDM Output current matching (see Figure 1) VPDM = 0.5 VDDA speed-up mode |ISWM| Analog switch output current SWM, speed-up mode † RPM = RPA = 27 kΩ to VSSA, F = K = 10. VPDM = 0 0.5 5 VDDA ÁÁÁ Á ÁÁ Á ÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁ Á ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ VSWM = 0.5 VDDA auxiliary-1 charge pump output TEST CONDITIONS† PARAMETER normal mode |IPDA1| Output current PDA1 I PDA1 |I PDA1| Relative output current variation PDA1 (see Figure 1) RPA 5% tolerance VSSA + 0.5 ≤ VPDA1 ≤ VDDA – 0.5 ∆IPDA1 Output current matching (see Figure 1) VPDA1 = 0.5 VDDA speed-up mode |ISW1| Analog switch output current SW1, speed-up mode † RPM = RPA = 27 kΩ to VSSA, F = K = 10. VPDA1 = 0 0.5 5 VDDA VSW1 = 0.5 VDDA auxiliary-2 charge pump output TEST CONDITIONS† PARAMETER normal mode |IPDA2| Output current PDA2 I PDA2 |I PDA2| Relative output current variation PDA2 (see Figure 1) RPA 5% tolerance VSSA + 0.5 ≤ VPDA2 ≤ VDDA – 0.5 ∆IPDA2 Output current matching (see Figure 1) VPDA2 = 0.5 VDDA speed-up mode |ISW2| Analog switch output current SW2, speed-up mode † RPM = RPA = 27 kΩ to VSSA, F = K = 10. VPDA2 = 0 0.5 5 VDDA VSW2 = 0.5 VDDA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN TYP MAX 400 500 600 µA 1.5 2 2.5 mA 15 % 8 UNIT % 1.5 2 2.5 mA MIN TYP MAX UNIT 400 500 600 µA 1.5 2 2.5 mA 15 % 8 % 1.5 2 2.5 MIN TYP MAX 400 500 600 µA 1.5 2 2.5 mA 15 % 8 1.5 2 2.5 mA UNIT % mA 5 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 Current I2 ∆ IOUT REL I1 ∆ IOUT MATCH ISINK V1 V2 Voltage ISOURCE I2 ∆ IOUT REL I1 Figure 1. Charge-Pump Output Current Definitions The relative output current variation is defined as the percent difference between charge-pump current output at two charge-pump output voltages and the mean charge-pump current output: DIOUT REL (I 2 – I 1) 2 x 100%; with V1 = 0.5 V, V2 = VDDA – 0.5 V. I OUT MEAN |(I 2 I 1)| Ť Ť+ ) Output current matching is defined as the difference in charge-pump sinking current output and charge-pump sourcing current output at a given charge-pump output (see Figure 1). ∆ IOUT MATCH = ISINK – ISOURCE; with V1 ≤ Voltage ≤ V2. charge-pump leakage currents, charge pumps not active PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PDM PDA1 IOZ Disabled output current PDA2 SWM VO = 0.5VDDA, RPM = RPA = VDDA DDA, Normal and speed-up s eed u modes SW1 SW2 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 nA TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 serial interface timing requirements with VDDA = 4.5 V, VDDP = VDD = 3.0 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CI Input capacitance RI Input resistance fclock tr, tf CLOCK frequency tw(High) tw(Low) Pulse duration, CLOCK high 20 ns Pulse duration, CLOCK low 20 ns Data before CLOCK high 15 ns 15 ns CLOCK input rise and fall time Strobe before CLOCK high th tw(pulse) pF 20 MHz 8 ns Ω 13 Under continuous operation tsu 10 10 k First power on or programmed from standby mode 10 Cext_coupling 60 kΩ µs Data after CLOCK high 15 ns Strobe after CLOCK high 15 ns 2 REF_IN s Strobe pulse width PARAMETER MEASUREMENT INFORMATION The timing relationship between the TRF2020 Data, Clock, and Strobe registers is shown in Figure 2. Data Valid DATA Data Change D0 D1 tsu D22 th – VIH D23 – VIL tw(HIGH) – VIH CLOCK – VIL tsu tw(LOW) th tw(PULSE) STROBE – VIH – VIL Clock Enabled Shift in Data Clock Disabled Store Data Figure 2. Serial Data Interface Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 TYPICAL CHARACTERISTICS MAIN DIVIDER MINIMUM INPUT POWER vs. FREQUENCY AND TEMPERATURE MAIN DIVIDER INPUT POWER vs. FREQUENCY AND SUPPLY VOLTAGE 0 0 VDDA = VDDP = VDD = 2.75 V MIP – Minimum Input Power – dBm TA = 25°C –40 TA = 25°C 1400 1300 1100 1200 900 1000 Figure 4 REFERENCE DIVIDER MINIMUM INPUT VOLTAGE vs. FREQUENCY AND TEMPERATURE 0.12 0.1 0.08 2.75 V 0.06 3.5 V 0.04 MIV – Minimum Input Voltage – V PP VDDA = VDDP = VDD = 2.75 V TA = 25°C 0.02 0.1 TA = –40°C 0.08 0.06 0.04 TA = 25°C TA = 85°C 0.02 0 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 f – Frequency – MHz 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 f – Frequency – MHz Figure 5 8 800 f – Frequency – MHz Figure 3 0.12 MIV – Minimum Input Voltage – V PP 700 500 f – Frequency – MHz REFERENCE DIVIDER MINIMUM INPUT VOLTAGE vs. FREQUENCY AND SUPPLY VOLTAGE 0 600 –50 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 900 1000 800 700 600 500 –50 TA = 85°C 2000 –40 1900 3.5 V TA = –40°C –30 1800 –30 –20 1700 2.75 V 1600 –20 –10 1500 IP – Input Power – dBm –10 Figure 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 TYPICAL CHARACTERISTICS AUXILIARY-1 DIVIDER MINIMUM INPUT POWER vs. FREQUENCY AND SUPPLY VOLTAGE AUXILIARY-1 DIVIDER MINIMUM INPUT POWER vs. FREQUENCY AND TEMPERATURE 0 0 VDDA = VDDP = VDD = 2.75 V –5 –10 –15 3.5 V –20 –25 2.75 V –30 –35 50 100 150 200 MIP – Minimum Input Power – dBm MIP – Minimum Input Power – dBm TA = 25°C –5 –10 –15 TA = –40°C –20 TA = 85°C –30 –35 50 250 300 350 400 450 500 TA = 25°C –25 100 150 f – Frequency – MHz 250 300 350 400 450 500 f – Frequency – MHz Figure 7 Figure 8 AUXILIARY-2 DIVIDER MINIMUM INPUT POWER vs. FREQUENCY AND SUPPLY VOLTAGE AUXILIARY-2 DIVIDER MINIMUM INPUT POWER vs. FREQUENCY AND SUPPLY VOLTAGE 0 0 TA = 25°C VDDA = VDDP = VDD = 2.75 V –10 –15 –20 3.5 V –25 2.75 V –30 –35 –40 MIP – Minimum Input Power – dBm –5 MIP – Minimum Input Power – dBm 200 –5 –10 –15 TA = –40°C –20 –25 TA = 85°C –30 TA = 25°C –35 50 100 150 200 250 300 350 400 450 500 f – Frequency – MHz –40 50 100 150 Figure 9 200 250 300 350 400 450 500 f – Frequency – MHz Figure 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 TYPICAL CHARACTERISTICS CH1 1: 34.688 Ω –133.84 Ω 1.1 GHz 2: 29.848 Ω –116.08 Ω 1.2 GHz 3: 45.211 Ω –182.11 Ω 900 MHz S11 1 U FS 1 3 2 START .030 000 MHz STOP 2 000.000 000 MHz Figure 11. Typical RF_IN Input Impedance (S11) CH1 1: 58.672 Ω – 403.83 Ω 250 MHz 2: 33.328 Ω –189.11 Ω 500 MHz 3: 109.47 Ω –1,0037 kΩ 100 MHz S11 1 U FS 1 3 2 START STOP 2 000.000 000 MHz .030 000 MHz Figure 12. Typical AUX1_IN Input Impedance (S11) 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 CH1 1: 57.031 Ω – 398.92 Ω 250 MHz 2: 32.273 Ω – 188.6 Ω 500 MHz 3: 107.63 Ω – 982.31 Ω 100 MHz S11 1 U FS 1 3 2 START STOP 2 000.000 000 MHz .030 000 MHz Figure 13. Typical AUX2_IN Input Impedance (S11) CH1 1: 803.75 Ω – 4.9245 κΩ 16.8 MHz 2: 218.88 Ω – 2.148 kΩ 40 MHz 3: 601 Ω – 4.1308 Ω 20.0 MHz S11 1 U FS 3 1 2 START STOP 2 000.000 000 MHz .030 000 MHz Figure 14. Typical REF_IN Input Impedance (S11) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 12 POST OFFICE BOX 655303 C51 0.1 µ F VOSC1 0.1 µ F C22 C64 22 pF 2 1 10 14 OUT VCC VT J4 3 4 • DALLAS, TEXAS 75265 Figure 15. Evaluation Board Schematic (Part 1 of 2) J3 C45 220pF 18 18 R47 18 R49 R50 6 2 VCO190–S VARIL RF_OUT MOD VCC AUX2_VCO NDK–OSC GND VCONT TCXO R46 50 C52 0.1 µ F 220 pF C48 C55 33 pF 51 k R56 REFIN 22 nF C23 C57 330 pF 22 pF C60 VOSC2 12 k R54 C58 12 nF R59 15 k C40 0.1 µ F C15 DNP C39 0.1 µ F VDD 1000 pF C62 12 11 10 9 8 7 6 5 4 3 2 1 TRF2020 AUX2_IN VDDP2 SW2 PDA2 VSSP REF_IN VSS LD STROBE DATA CLOCK VDD U1 RF_IN VDDPM RPM VSSA PDM SWM VDDA RPA SW1 PDA1 VDDP1 AUX_IN 13 14 15 16 17 18 19 20 21 22 23 24 100 pF C8 C44 0.1 µ F VDD C41 0.1 µ F VDD 18 R15 18 R10 50 R12 18 R17 33 k 12 k R20 5 7 100 pF C46 OUT 6 18 VCC 14 10 VDDA MVCO VT J1 VCO191–U VARIL 3 1 36 k R19 C18 680pF RF_OUT VCC MOD R22 18 k C6 4700 pF C42 0.1 µ F R43 24 k VCO190–S VARIL VT MOD RF_OUT AUX1_VCO C14 47 pF C20 0.1 µ F 2 18 R23 R25 50 C13 820 pF C7 0.1 µ F C19 4700 pF R11 R9 24 k 12 k R18 R21 20 k 220 pF C24 R26 220pF 18 R24 C43 C61 0.1 µ F C16 68 pF C59 22 pF C63 22 pF VOSC2 C12 0.1 µ F VOSC1 J2 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 APPLICATION INFORMATION TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 APPLICATION INFORMATION FOR PC INTERFACE ONLY VDD VOPTO R27 1.8 k 1 14 2 15 3 16 4 17 5 18 R31 3.6 k R28 1.8 k R32 3.6 k R29 1.8 k R33 3.6 k R30 2.7 k DATA CLOCK R34 1.8 k STROBE CLOCK1 U2 DATA1 STROBE1 4N28S 6 19 7 20 8 21 9 22 10 23 U3 4N28S U4 U5 6 4N28S CLOCK 1 5 LOCK 9 11 24 To U1/5 4 12 25 13 MOC8030 STROBE DATA To U1/4 To U1/3 CLOCK To U1/2 POWER POWER VR1 GND DGND HUB + C1 4.7 µ F 1 AGND 4 2 3 VT VR2 NC VO VO VO VO A NC 8 VDDA 2 7 3 6 5 VDDA LM317LBD R5 W CCW CW 1k 1 4 VT VR3 NC VO VO VO VO A NC 8 VDD 1 2 7 3 6 5 VDD LM317LBD 4 VT VR4 NC VO VO VO VO A NC 8 VOSC1 1 7 2 6 3 5 4 LM317LBD VT VR5 NC VO VO VO VO A NC 8 6 3 5 4 LM317LBD R3 R13 220 220 270 270 1k + C3 1 µF R7 820 + C4 1 µF R8 390 VT NC VO VO VO VO A NC 8 VOPTO 7 6 5 LM317LBD R2 R6 W CCW CW 1 2 7 R1 + C2 1 µF VOSC2 R37 270 + C5 1 µF R38 820 + C25 1 µF NOTE: Evaluation board dc supply circuitry Figure 15. Evaluation Board Schematic (Part 2 of 2) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 APPLICATION INFORMATION Table 1. TRF2020 Evaluation Board Parts List 14 DESIGNATORS DESCRIPTION VALUE QTY SIZE (mm) MANUFACTURER MANUFACTURER P/N C1 Capacitor 4.7 uF 1 “A” 3.2x1.6 Venkel TA025TCM series C2, 3, 4, 5, 25 Capacitor 1 uF 5 “A” 3.2x1.6 Venkel TA025TCM series C6, 19 Capacitor 4700 pF 2 0603 1.6x.08 Murata GRM39X7R series C7, 12, 20, 22, 39, 40, 41, 42, 44, 51, 52, 61 Capacitor 0.1 uF 12 0603 1.6x.08 Murata GRM39X7R series C8, 46 Capacitor 100 pF 2 0603 1.6x.08 Murata GRM39X7R series C13 Capacitor 820 pF 1 0603 1.6x.08 Murata GRM39X7R series C14 Capacitor 47 pF 1 0603 1.6x.08 Murata GRM39X7R series C15 Capacitor DNP 1 0603 1.6x.08 C16 Capacitor 68 pF 1 0603 1.6x.08 Murata GRM39X7R series C18 Capacitor 680 pF 1 0603 1.6x.08 Murata GRM39X7R series C23 Capacitor 22 nF 1 0603 1.6x.08 Murata GRM39X7R series C24, 43, 45, 48 Capacitor 220 pF 4 0603 1.6x.08 Murata GRM39X7R series C55 Capacitor 33 pF 1 0603 1.6x.08 Murata GRM39X7R series C57 Capacitor 330 pF 1 0603 1.6x.08 Murata GRM39X7R series C58 Capacitor 12 nF 1 0603 1.6x.08 Murata GRM39X7R series C59, 60, 63, 64 Capacitor 22 pF 4 0603 1.6x.08 Murata GRM39X7R series C62 Capacitor 1000 pF 1 0603 1.6x.08 Murata GRM39X7R series R1, 2 Resistor 220 2 0603 1.6x.08 Panasonic ERJ–3GSYJ series R3, 13, 37 Resistor 270 3 0603 1.6x.08 Panasonic ERJ–3GSYJ series R5, 6 Resistor 1K 2 .25” square R7, 38 Resistor 820 2 0603 1.6x.08 Panasonic ERJ–3GSYJ series Bourns 3269W001 series R8 Resistor 390 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series R9, 43 Resistor 24K 2 0603 1.6x.08 Panasonic ERJ–3GSYJ series R10, 25, 46 Resistor 50 3 0603 1.6x.08 Panasonic ERJ–3GSYJ series R11, 12, 15, 23, 24, 26, 47, 49, 50 Resistor 18 9 0603 1.6x.08 Panasonic ERJ–3GSYJ series R17 Resistor 33K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series R18, 20, 54 Resistor 12K 3 0603 1.6x.08 Panasonic ERJ–3GSYJ series R19 Resistor 36K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series R21 Resistor 20K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series R22 Resistor 18K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series R27, 28, 29, 34 Resistor 1.8K 4 0603 1.6x.08 Panasonic ERJ–3GSYJ series R30 Resistor 2.7K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series R31, 32, 33 Resistor 3.6K 3 0603 1.6x.08 Panasonic ERJ–3GSYJ series R56 Resistor 51K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series R59 Resistor 15K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series U1 Integrated Circuit 1 U2, 3, 4 Optoelectronics 3 POST OFFICE BOX 655303 TI 730C–04 • DALLAS, TEXAS 75265 Motorola TRF2020 4N28S TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 APPLICATION INFORMATION Table 1. TRF2020 Evaluation Board Parts List (Continued) DESIGNATORS DESCRIPTION U5 Optoelectronics VALUE QTY SIZE (mm) MANUFACTURER 1 730C – 04 Motorola MOC8030S National Semiconductor LM317LBD 747238 – 4 VR1, 2, 3, 4, 5 Voltage regulator 5 SO – 8 MANUFACTURER P/N P1 Para. connector 1 AMP J1, 2, 3, 4 SMA connector 4 EF Johnson 142 – 0701– 831 MVCO Voltage-controlled oscillator 1 Vari-L Comp. VCO190–U TCXO Temp.-compensated crystal oscillator 1 Toyocom AUX 1_VCO Voltage-controlled oscillator 1 Vari-L Comp. VCO190–S AUX 2_VCO Voltage-controlled oscillator 1 Vari-L Comp. VCO190–S DATA, VDDA, VDD, LOCK, POWER, CLOCK, GND, STROBE Test point 8 Components Corp. ATTEN 10 dB RL 0 dBm D VAVG 50 10 dB/ TCO – 980 series TP –105 – 01 series MKR – 85.33 dB 200 kHz MKR 200 kHz – 85.33 dB CENTER 1.1089992 GHz RBW 3 kHz VBW 3 kHz SPAN 500 kHz SWP 140 ms Figure 16. Typical Main Synthesizer Reference Spurs POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 APPLICATION INFORMATION ATTEN 10 dB RL 0 dBm VAVG 50 10 dB/ MKR – 45.83 dB 4 kHz MKR 4 kHz – 45.83 dB D CENTER 1.10899908 GHz RBW 300 Hz VBW 300 Hz SPAN 30 kHz SWP 840 ms Figure 17. Typical Main Synthesizer Close-in Noise at 4 kHz Offset ATTEN 10 dB RL 0 dBm D VAVG 50 10 dB/ MKR – 51.50 dB 1 kHz MKR 1 kHz – 51.50 dB CENTER 1.10899918 GHz RBW 100 Hz VBW 100 Hz SPAN 10 kHz SWP 802 ms Figure 18. Typical Main Synthesizer Close-in Noise at 1 kHz Offset 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 APPLICATION INFORMATION TRACE A: Ch1 FM Main Time A Marker 25 kHzpk 652.3438 us 643.05 Hzpk LinMag 5 kHz /div – 25 kHzpk Start: 0 s Stop: 1.99609375 ms Figure 19. Typical Main Synthesizer Transient Response For 35-MHz Jump From 1074 MHz to 1109 MHz TRACE A: Ch1 FM Main Time A Marker 25 kHzpk 652.4375 us 893.77 Hzpk LinMag 5 kHz /div – 25 kHzpk Start: 0 s Stop: 1.99609375 ms Figure 20. Typical Main Synthesizer Transient Response For 35-MHz Jump From 1109 MHz to 1074 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 APPLICATION INFORMATION ATTEN 10 dB RL 0 dBm D VAVG 50 10 dB/ MKR – 88.17 dB 200 kHz MKR 200 kHz – 88.17 dB CENTER 248 MHz RBW 3 kHz VBW 3 kHz SPAN 500 kHz SWP 140 ms Figure 21. Typical Auxiliary-1 Synthesizer Reference Spurs ATTEN 10 dB RL 0 dBm D VAVG 50 10 dB/ MKR – 87.33 dB 200 kHz MKR 200 kHz – 87.33 dB CENTER 45.2000 MHz RBW 3 kHz VBW 3 Hz SPAN 500 kHz SWP 140 ms Figure 22. Typical Auxiliary-2 Synthesizer Reference Spurs 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 PRINCIPLES OF OPERATION serial port operation The TRF2020 device registers are manipulated via a synchronous serial data port. The timing relationships are defined in Figure 2, in the parameter measurement information section. Four 24-bit words are clocked into temporary holding registers with the least significant bit clocked first. The operation registers are loaded with the new data residing in the temporary registers with the rising edge of the strobe input. Each word can be written to the device independently. In this manner, only the words containing the information required to change the current state of the device need to be written. To fully program the device, the words are written in the following order: Word-1 Auxiliary-1 synthesizer Word-2 Auxiliary-2 synthesizer Word-3 Device Word-0 Main synthesizer Word-3 follows Word-1 and Word-2 because the frequency information for the auxiliary synthesizers is stored in the operational registers with Word-1 and Word-2. It is necessary to load this frequency information before the speed-up mode is activated by the auxiliary synthesizers’ power enable bits in Word-3. Word-0 is written last because the speed-up mode for the main synthesizers is activated by the writing of Word-0. If the main synthesizer is to be enabled, the power enable bit is written to the device in the preceding Word-3. The two most significant bits of each word contain the unique address of the word; the balance of the 22 bits contains the data fields. serial word format 23 22 21 20 19 18 17 16 15 14 13 12 11 ADDR 10 9 8 7 6 5 4 3 2 1 0 DATA 0 0 C 0 1 G 1 0 1 1 N M V B L A F E D K J H U T S R P serial word format function A: 5-bit NM2 data for main divider coefficient B: 11-bit NM1 data for main divider coefficient C: 6-bit data to control speed-up mode time of main synthesizer analog switch D: 3-bit NM2 data for auxiliary-1 divider coefficient E: 11-bit NM1 data for auxiliary-1 divider coefficient F: 2-bit data to select main synthesizer speed-up/normal mode current ratio G: 6-bit data to control speed-up mode time of auxiliary synthesizers H: 3-bit NM2 data for auxiliary-2 divider coefficient POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 PRINCIPLES OF OPERATION serial word format function (continued) J: 11-bit NM1 data for auxiliary-2 divider coefficient K: 2-bit data to select auxiliary synthesizers speed-up/normal mode current ratio L: 2-bit data to select reference postscaler for main synthesizer M: 2-bit data to select reference postscaler for auxiliary-1 N: 2-bit data to select reference postscaler for auxiliary-2 P: 11-bit data for reference divider coefficient R: 1-bit data to enable main synthesizer power. When 1, power is enabled S: 1-bit data to enable auxiliary-1 synthesizer power. When 1, power is enabled T: 1-bit data to enable auxiliary-2 synthesizer power. When 1, power is enabled U: 2-bit data to select lock detect for main, auxiliary-1, and auxiliary-2 synthesizers V: 6-bit data reserved for test purposes main prescaler Main prescaler and speed-up mode coefficients are defined by Word-0 at address 00. The total division of the main synthesizer prescaler is defined as follows: TOTALMAIN = 32 × B + A, where 31 ≤ B < 211†, and 0 ≤ A < 25. † The above equation defines a synthesizer operation where contiguous channels exist for all combinations of A and B. If B < 31, the synthesizer no longer provides contiguous channels. In either case, it is important that the value assigned to A is never greater than the value assigned to B. The speed-up mode total-time duration of the main synthesizer analog switch is defined by field C in Word-0 as follows: TIME MAIN–SP +2 C 1 , f ref where 1 ≤ C < 26, and fref is the corresponding phase detector reference frequency. auxiliary-1 prescaler Auxiliary-1 prescaler coefficients are defined by Word-1 at address 01. The total division of the auxiliary-1 synthesizer prescaler is defined as follows: TOTALAUX–1 = 8 × E + D, where 7 ≤ E < 211‡, and 0 ≤ D < 23. ‡ The above equation defines a synthesizer operation where contiguous channels exist for all combinations of D and E. If E < 7, the synthesizer no longer provides contiguous channels. In either case, it is important that the value assigned to D is never greater than the value assigned to E. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 PRINCIPLES OF OPERATION auxiliary-1 prescaler (continued) The speed-up total-time duration of the auxiliary synthesizer boost charge pumps is defined as follows: TIME AUX–SP +2 G 1 , f ref where 1 ≤ G < 26, and fref is the corresponding phase detector reference frequency. The speed-up mode of both auxiliary synthesizers is controlled by field G in Word-1, although each auxiliary synthesizer has its own independent speed-up mode counter. auxiliary-2 prescaler Auxiliary-2 prescaler coefficients are defined by Word-2 at address 10. The total division of the auxiliary-2 synthesizer prescaler is defined as follows: TOTALAUX–2 = 8 × J + H, where 7 ≤ J < 211†, and 0 ≤ H < 23. † The above equation defines a synthesizer operation where contiguous channels exist for all combinations of H and J. If J < 7, the synthesizer no longer provides contiguous channels. In either case, it is important that the value assigned to H is never greater than the value assigned to J. reference divider postscalers Each synthesizer section is referenced to the main reference divider through a selectable divide-by-1, -2, -4, or -8 postscaler (see the reference divider section below). Selection of the additional 1, 2, 4, or 8 division is determined by the state of bits L, M, and N, as depicted in Word-2 as follows: Additional Postscaler Division N1, M1, OR L1 N0, M0, OR L0 ADDITIONAL DIVISION 0 0 1 0 1 2 1 0 4 1 1 8 reference divider The reference divider coefficients are defined by Word-3 at address 11. The total division of the 11-bit reference counter is defined as follows: TOTAL REF + P1 , where 1 ≤ P < 211. power enable Each synthesizer section can be enabled/disabled by manipulation of fields R, S, and T of Word-3. The appropriate synthesizer section is enabled if a logic one (1) is written to the appropriate field. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 PRINCIPLES OF OPERATION lock detect (LD) selection The phase-locked state of each synthesizer section is indicated by the logic state of the LD terminal. Each synthesizer section can be selected individually or as an ANDed function by the manipulation of field U in Word-3 as follows: Additional Postscaler Division U1 U0 LOCK DETECT 0 0 MAIN 0 1 AUX-1 1 0 AUX-2 1 1 ANDed The terms in the ANDed function are dependent on the power enable bit state of each synthesizer section. Only if the synthesizer section is enabled is its term significant in the ANDed term of the lock detect output. This is depicted in the following logic equation: LDU1 = U0 = 1 = (MAIN ) R) (AUX1 ) S) (AUX2 ) T) S (R + S+ T) where R, S, and T are the power enable bits of Word-3. test mode selection Internal signals can be routed to the LD terminal by manipulating the test mode field V in Word-3 as shown in Table 2. Table 2. Test Mode Selection 22 V4 V3 V2 V1 V0 0 0 1 0 1 Main prescaler output 0 0 1 1 0 Main 11-bit counter output 0 0 1 1 1 Main 5-bit counter output 1 1 0 0 1 Main phase comparator down pulse output 1 1 0 1 0 Main phase comparator up pulse output 1 1 0 1 1 Main timer output 1 0 1 0 1 Auxiliary-1 prescaler output 1 0 1 1 0 Auxiliary-1 11-bit counter output 1 0 1 1 1 Auxiliary-1 3-bit counter output 0 1 1 0 1 Auxiliary-1 phase comparator down pulse output 0 1 1 1 0 Auxiliary-1 phase comparator up pulse output 0 1 1 1 1 Auxiliary-1 timer output 1 1 1 0 1 Auxiliary-2 prescaler output 1 1 1 1 0 Auxiliary-2 11-bit counter output 1 1 1 1 1 Auxiliary-2 3-bit counter output 1 0 0 0 1 Auxiliary-2 phase comparator down pulse output 1 0 0 1 0 Auxiliary-2 phase comparator up pulse output 1 0 0 1 1 Auxiliary-2 timer output 0 1 0 0 1 Main reference clock POST OFFICE BOX 655303 ROUTING TO LD TERMINAL • DALLAS, TEXAS 75265 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 PRINCIPLES OF OPERATION test mode selection (continued) Table 2. Test Mode Selection (continued) V4 V3 V2 V1 V0 0 1 0 1 0 Auxiliary-1 reference clock ROUTING TO LD TERMINAL 0 1 0 1 1 Auxiliary-2 clock reference clock NOTE: All other binary combinations of the test mode field V not shown above are reserved for future use. Bit 5 in the V-word is used to select an external pulse mode. In the external pulse mode, the CMOS main and subcounters are fed externally sourced clock pulses through pin 18 instead of from the prescaler inputs as normally operated. This mode makes testing of the internal CMOS counters easy. speed-up switching time main synthesizer When the main frequency synthesizer is changed in frequency, it may be desirable to increase the loop bandwidth for a short time in order to achieve a faster lock time. An analog switch is provided that can vary the topography of the loop filter in order to achieve a faster loop gain. When the frequency is changed (and speed-up operation is desired), the following actions occur: 1. The new frequency coefficients for the main synthesizer are sent to the device over the serial bus. 2. After the data is clocked in, the strobe is toggled to high. 3. The positive edge of the strobe loads the new frequency into the main synthesizer prescaler (using the next reference frequency pulse to synchronize). 4. With loading of the main synthesizer prescaler, the speed-up mode analog switch is activated to a low-impedance state and the speed-up mode charge-pump boost circuit is activated. 5. The speed-up mode is maintained until the main synthesizer speed-up counter, previously loaded with field C of Word-0, counts down to zero (0). The speed-up counter is clocked with the main synthesizer phase detector reference frequency. 6. With the speed-up counter reaching a terminal count of zero (0), the speed-up analog switch reverts to the normal mode high-impedance state, and the speed-up mode charge pump boost circuit is deactivated. auxiliary synthesizer Because the frequency of the auxiliary synthesizers is rarely changed during normal operation, speed-up mode occurs during the independent power enable of the auxiliary synthesizer sections as controlled by fields S and T in Word-3. Upon the transition of these 1-bit fields from a logic zero (0) to a logic one (1), the following actions occur: 1. It is assumed that the proper frequency coefficients were written to the corresponding auxiliary synthesizer prescaler field. 2. The power enable bit for the corresponding auxiliary synthesizer is changed from a zero (0) to a one (1). 3. The positive edge of the strobe loads Word-3, which contains the power enable bit fields (using the next reference frequency pulse to synchronize). 4. With the loading of Word-3, the speed-up mode charge-pump boost circuit is activated and the analog switch is activated to a low-impedance state. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 PRINCIPLES OF OPERATION auxiliary synthesizer (continued)1234 5. The speed-up mode is maintained until the corresponding speed-up mode counter counts down to a terminal count of zero. The speed-up counter is clocked with the corresponding auxiliary synthesizer phase detector reference frequency. 6. With the corresponding speed-up counter reaching terminal count, the speed-up mode charge-pump boost circuit and the analog switch for the corresponding auxiliary synthesizer revert to the normal mode, high-impedance, off state. using the speed-up mode By changing the loop filter frequency response or the charge-pump output current, the overall closed-loop response of the synthesizer system is altered. Without careful consideration, synthesizer lock-up times may degrade rather than improve using the speed-up mode. selecting current ratios The normal mode and speed-up mode charge-pump current ratios for the main synthesizer and the auxiliary synthesizers are selected using field F of Word-1 and field K of Word-2, respectively, as shown in Table 3. Table 3. Charge-Pump Current Ratio Selection F AND K FIELDS SPEED-UP/NORMAL MODE RATIO 11 8 (2 mA/0.25 mA) 10 4 (2 mA/0.5 mA) 01 2 (2 mA/ 1 mA) 00 1 (2 mA/2 mA) external charge-pump scaling resistors Two external scaling resistors are connected between RPM, RPA, and VSSA (analog ground) in order to scale the speed-up mode charge-pump output current for the main synthesizer and the two auxiliary synthesizers as defined in the following equations. The external scaling resistors in conjunction with the programmable charge-pump current ratios determine speed-up and normal mode currents. Main charge-pump speed-up mode current = 1 RPM Auxiliary charge-pump speed-up mode current = 24 2 mA 1 RPA POST OFFICE BOX 655303 2 mA v RPM v R), 27 kW (5 kW v RPM v R), 27 kW (5 kW • DALLAS, TEXAS 75265 TRF2020 SYNTHESIZER FOR GLOBAL SYSTEM FOR MOBILE (GSM) CELLULAR TELEPHONES SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° 0,75 0,50 A Seating Plane 1,20 MAX 0,10 0,05 MIN PINS ** 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064 / E 08/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (“Critical Applications”). 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