P R E L I M I N A R Y Z89303/05/07 CPS DC-4222-03 PRELIMINARY CUSTOMERPROCUREMENTSPECIFICATION Z89303/05/07 DIGITALTELEVISIONCONTROLLER GENERAL DESCRIPTION The Z89303/05/07 Digital Television Controllers are application-specific controllers designed to provide complete audio and video control of television receivers, video recorders, with advanced on-screen display facilities. The Z89303/05/07 are 24K, 16K and 12K ROM versions in 52-pin SDIP packages. The powerful 12 MHz Z89C00 RISC processor core allows the user to control the onboard peripheral functions and registers using the standard processor instruction set. The extensive character attributes can be controlled in two modes: by the on-screen display controller character control mode for maximum display control flexibility, and closed caption mode for optimum display of closed caption text. Closed caption text can be decoded directly from the composite video signal with the assistance of the processor's digital signal processing capabilities and displayed on the screen. The character representation in this mode allows for a simple attribute control through the insertion of control characters, and each word of RAM specifies two displayed characters. The character control mode provides access to the full set of attribute controls. Each word of RAM specifies a single displayed character and basic character attributes, allowing the modification of attributes on a character-by-character basis. The insertion of control characters permits direction of other character attributes. The fully customized 512 character set, formatted in two 256 character banks, can be displayed with a host of display attributes that incude underlining, italics, blinking, eight foreground/background colors, character position offset delay, and background transparency. The 16-bit display character representation allows the modification of some key attributes on a character-by-character basis. A character's pixel array is stored as a 16- or 18-word representation in Character Graphics ROM (CGROM). The ROM contents are referenced by a 16-bit word stored in video RAM (VRAM) defining the character type and its key attributes. DC-4222-03 (10-10-94) Serial interfacing with the television tuner is provided through the tuner serial port. Other serial devices, such as digital channel tunning adjustments, may be accessed through the industry standard I2C port. Additional hardware provides the capability to display two times normal size characters. The smoothing logic contained in the on-screen display circuit improves the appearance of larger fonts. Fringing circuitry can be activated to improve the visibiity of text by surrounding the character lines with a one-pixel border. RGB outputs provide the direct video signals, and a blanking output is provided to control the video multiplexor. Dot clock and verticle line synchronization are normally obtained from H_FLYBACK and V_FLYBACK, but can be generated by the Z89303/05/047, and driven to the external deflection unit through the bidirectional SYNC ports when external video synchronization signals are not present. User control can be monitored through the keypad port, or the 16-bit remote control capture register. functions such as color and volume can be controlled by eight 8-bit pulse width modulated scanning Receiver directly ports. All nine PWM ports are available in the 52-pin package. The Z89303/05/07 has two internal 12 MHz VCOs that are referenced to a 32 KHz internal oscillator to provide the system clock. In Sleep mode, the controller uses the 32 KHz clock for the system clock to reduce power consumption. The processor can be suspended by placing it into STOP mode when main power is not available for minimal power consumption. 1 Z89303/05/07 CPS DC-4222-03 P R E L I M I N A R Y GENERAL DESCRIPTION (Continued) PWM Capture IRIN Port 17 Port 00 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 PWM9 ADC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 Port1 Port 0 Port 00 Port 01 Port 02 Port 03 Port 04 Port 05 Port 06 Port 07 Port 08 Port 09 Port 0A Port 0B Port 0C Port 0D Port 0E Port 0F Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 Port 19 Note: Shaded pin functions not available on 40-pin device. Control XTAL1 XTAL2 LPF HSYNC VSYNC /Reset V1 V2 V3 BLANK HALFBLNK CPU RAM 640 x 16 OSD Register Addr/Data ROM Addr Data ROM Data Functional Block Diagram 2 Port0F Address ROM 12K x 16 16K x 16 24K x 16 Note: Z89307 has 12K words of ROM. Z89305 has 16K words. Z89302/03 has 24K words. P R E L I M I N A R Y PWM9 1 52 PWM8 IRIN 2 51 PWM7 Port18/G<0> 3 50 PWM6 Port19 4 49 PWM5 Port0E 5 48 PWM4 Port00/ADC2 6 47 PWM3 Port01/I2SSC 7 46 PWM2 Port02/I2SSD 8 45 PWM1 Port03 9 44 ADC5 10 43 CVI/ADC0 Port04/ADC4 11 42 LPF Port05/ADC3 12 Z89303 Z89305 Z89307 41 XTAL2 40 AN GND 52-Pin Shrink DIP 39 XTAL1 38 AN VCC /Reset GND Port06/Counter 13 Port07/CSync 14 Port08/R<1> 15 Port09 16 37 VCC 17 36 Port0F/HalfBlnk Port17/ADC1 Port10/R<0> 18 35 Port11/I2MSC 19 34 Blank Port12/I2MSD 20 33 V1 Port13/G<1> 21 32 V2 Port14/B<0> 22 31 V3 Port15/B<1> 23 30 VSync Port16/SCLK 24 29 HSync Port0A 25 28 Port0D Port0B 26 27 Port0C Z89303/05/07 CPS DC-4222-03 52-Pin Shrink DIP Configuration 3 Z89303/05/07 CPS DC-4222-03 P R E L I M I N A R Y PIN DESCRIPTIONS Z89303/05/07 Pin Name Function VCC – GND – +5 V IRIN ADC[5:0] a Infrared Remote Capture Input 4-Bit Analog to Digital Converter Input b 14-Bit Pulse Width Modulator Output PWM10, PWM9 PWM[8:1]c Port0[F:0]d 0V 8-Bit Pulse Width Modulator Output Bit Programmable Input/Output Ports Z89303/05/07 52-Pin Configuration Direction Reset 17,38 PWR 10,40 PWR 2 44,11,12,6,35,43 I nAI I I –,1 OD O 52,51,50,49, 48,47,46,45 36,5,28,27,26,25, 16,15,14,13,12, 11,9,8,7,6 4,3,35,24,23,22, 21,20,19,18 OD O B I B I 7 or 19 8 or 20 BOD BOD Port1[9:0] c Bit Programmable Input/Output Ports SCLf SCD g 12C Clock I/O 12C Data I/O XTAL1 XTAL2 Crystal Oscillator Input Crystal Oscillator Output 39 41 AI AO I O LPF HSYNC Loop Filter H_Sync 42 29 AB B O I VSYNC V_Sync 30 B I /RESET Device Reset 37 I I V[3:1] OSD Video Output (Typically Drive B, G, and R Outputs) Blank OSD Blank Output 31,32,33 O O 34 O O Half Blankh RGB Digital Outputs i OSD Half Blank Output R[1:0],G[1:0], and B[1:0] Outputs of the RGB Matrix 36 23,22,21, 18,15,3 O O SCLKk Internal Processor SCLK 24 O 4 Z89303/05/07 CPS DC-4222-03 P R E L I M I N A R Y V1, V2, V3 ANALOG OUTPUT Specifications VCC = 5.25 V VCC = 5.25 V Condition Limit Output Voltage Bit = 11 Bit = 10 4.55 V +/– 0.25 V 3.205V +/– 0.2 V Bit = 01 Bit = 00 1.95 V +/– 0.15 V 0.65 V +/– 0.1 V Settling Time 70% of DC Level, 10pf Load < 50 nsec V1, V2, V3 ANALOG OUTPUT Specifications VCC = 4.75V VCC = 4.75V Condition Limit Output Voltage Bit = 11 Bit = 10 3.90 V +/– 0.25 V 2.90 V +/– 0.2 V Bit = 01 Bit = 00 1.90 V +/– 0.15 V 0.1 V +/– 0.1 V Settling Time 70% of DC Level, 10pf Load < 50 nsec Z893XX 32K Oscillator Recommended Circuit Notes: c) PWM[8,7] is not available on the 40-pin DIP version. d) Port0[F:A] is not available on the 40-pin DIP version. e) Port19 is not available on the 40-pin DIP version. f) SCL I/O pin is shared with Port0 or Port11. g) SCD I/O pin is shared with Port02 or Port12. h) Half Blank output is a function shared with Port0F. Half Blank output is not available on the 40-pin DIP version. i) Digital RGB outputs and the internal SCLK are shared with Port1[5:0]. k) Internal processor SCLK is shared with Port16. 5 Z89303/05/07 CPS DC-4222-03 P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Max Units Conditions VCC VID Power Supply Voltage Input Voltage 0 –0.3 7 VCC +0.3 V V Digital Inputs VIA VO VO Input Voltage Output Voltage Output Voltage –0.3 –0.3 –0.3 VCC +0.3 VCC +0.3 VCC +8.0 V V V IOH IOH IOL IOL Output Output Output Output –10 –100 20 200 mA mA mA mA TA TA Operating Temperature Storage Temperature 70 150 °C °C Current Current Current Current High High Low Low 0 –65 Analog Inputs (A/D0...A/D4) All Push-Pull Digital Output Open-Drain PWM Outputs (PWM1...PWM8) One Pin All Pins One Pin All Pins DC CHARACTERISTICS TA = 0°C to + 70°C; V CC = 4.5 V to + 5.5 V; FOSC = 32.768 KHz Symbol Parameter Min Max Typical Units VIL VIH Input Voltage Low Input Voltage High 0 0.6 VCC 0.2 VCC VCC 0.4 3.6 V V VPU VOL VOL Max. Pull-Up Voltage Output Voltage Low Output Voltage High 0.16 4.75 V V V PWM0...PWM8 Only @ IOL = 1 mA @ IOL = 0.75 mA VXL VXH VHY IIR Input Voltage XTAL1 Low Input Voltage XTAL1 High Schmitt Hysteresis Reset Input Current 0.75 150 1.0 3.5 0.5 90 V V V µA External Clock Generator Driven On XTAL1 Input Pin VRL = 0 V IIL ICC ICC1E Input Leakage Supply Current Supply Current of the OTP 3.0 100 700 0.01 60 300 µA mA µA @ 0 V and VCC ICC1 ICC2 Supply Current Supply Current 300 10 100 5 µA µA Sleep Mode @ 32 KHz Sleep Mode 6 12 0.4 V CC –0.9 0.3 VCC VCC –2.0 3.0 –3.0 Conditions Sleep Mode @ 32 KHz Z89303/05/07 CPS DC-4222-03 P R E L I M I N A R Y AC CHARACTERISTICS TA = 0°C to + 70°C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz Symbol Parameter Min Max T PC T RC,TFC Input Clock Period Clock Input Rise and Fall 16 100 T DPOR Power On Reset Delay 0.8 Typical Units 32 12 µS µS 1.2 s AC CHARACTERISTICS TA = 0°C to + 70°C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 KHz Symbol Parameter Min Max Typical Units TWRES TD HS Power-On Reset Min. Width H_Sync Incoming Signal Width 5.5 5TPC 12.5 11 µS µS TDVS TD ES V_Sync Incoming Signal Width Time Delay Between Leading Edge of V_Sync and H_Sync in Even Field 0.15 –12 1.5 +12 1.0 0 mS µS T DOS Time Delay Between Leading Edge of H_Sync in Odd Field H_Sync/V_Sync Edge Width 20 44 32 µS 2.0 0.5 µS TWHVS Notes: All timing of the I 2C bus interface are defined by related specifications of the I 2C bus interface. 7 P R E L I M I N A R Y Development Projects: Customer is cautioned that while reasonable efforts will be employed to meet performance objectives and milestone dates, development is subject to unanticipated problems Pre-Characterization Product: The product represented by this CPS is newly introduced and Zilog has not completed the full characterization of the product. The CPS states what Zilog knows about this product at this time, but additional features or non-con- © 1994 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. 8 Z89303/05/07 CPS DC-4222-03 and delays. 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