SCAS184A − JUNE 1990 − REVISED APRIL 1996
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D
D
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54ACT16620 . . . WD PACKAGE
74ACT16620 . . . DL PACKAGE
(TOP VIEW)
Widebus Family
Inputs Are TTL-Voltage Compatible
Inverting Logic
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
1OEAB
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2OEAB
description
The ’ACT16620 are inverting 16-bit transceivers
designed for asynchronous communication
between data buses. The control-function
implementation allows for maximum flexibility in
timing.
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. They allow
data transmission from the A bus to the B bus or
from the B bus to the A bus, depending on the logic
level at the output-enable (OEAB or OEBA)
inputs. The output-enable inputs can be used to
disable the device so that the buses are effectively
isolated.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OEBA
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OEBA
The dual-enable configuration gives the transceiver the capability to store data by simultaneously enabling
OEAB and OEBA. Each output reinforces its input in this transceiver configuration. Thus, when both control
inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, the bus lines
remain at their last states.
The 74ACT16620 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16620 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74ACT16620 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
!"#$%&' #"'(' ')"*%("' #$**&' ( ") +$,-#("' !(&. *"!$# #"')"*% "
+&#)#("' +&* & &*% ") &/( '*$%&' ('!(*! 0(**('1.
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1
SCAS184A − JUNE 1990 − REVISED APRIL 1996
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OEBA
OEAB
L
L
B data to A bus
L
H
B data to A bus,
A data to B bus
H
L
Isolation
H
H
A data to B bus
logic symbol†
48
1OEBA
1OEAB
1
25
2OEBA
2OEAB
1A1
24
EN1
EN2
EN3
EN4
47
2
1
1
1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
3
44
5
43
6
41
8
40
9
38
11
37
12
36
13
1
1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2
46
3
35
14
33
16
32
17
30
19
29
20
27
22
26
23
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1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
4
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
1B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
SCAS184A − JUNE 1990 − REVISED APRIL 1996
logic diagram (positive logic)
1OEBA
1OEAB
1A1
48
2OEBA
1
2OEAB
47
2A1
2
25
24
36
13
2B1
1B1
To Seven Other Channels
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.2 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16620
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
∆t/∆v
Low-level output current
High-level input voltage
74ACT16620
2
2
0.8
Input transition rise or fall rate
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
UNIT
V
V
0.8
V
VCC
VCC
V
−24
−24
mA
24
24
mA
VCC
VCC
0
0
V
0
10
0
10
ns/V
−55
125
−40
85
°C
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SCAS184A − JUNE 1990 − REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
74ACT16620
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.8
3.8
IOH = −24 mA
5.5 V
4.94
4.8
4.8
IOH = −75 mA†
5.5 V
IOL = 24 mA
MIN
MAX
3.85
4.5 V
IOL = 50 µA
A
VOL
54ACT16620
MIN
IOH = −50 µA
A
VOH
TA = 25°C
TYP
MAX
VCC
0.1
MIN
MAX
UNIT
V
3.85
0.1
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
V
II
Control inputs
IOL = 75 mA†
VI = VCC or GND
IOZ‡
A or B ports
VO = VCC or GND
5.5 V
±0.5
±5
±5
µA
VI = VCC or GND,
IO = 0
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
8
80
80
µA
5.5 V
0.9
1
1
mA
ICC
∆ICC§
Ci
Control inputs
Cio
A or B ports
5.5 V
5.5 V
±0.1
±1
±1
µA
VI = VCC or GND
VO = VCC or GND
5V
4
pF
5V
15
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPZH
tPZL
OEBA
A
tPHZ
tPLZ
OEBA
A
tPZH
tPZL
OEAB
B
tPHZ
tPLZ
OEAB
B
MIN
TA = 25°C
TYP
MAX
54ACT16620
74ACT16620
MIN
MAX
MIN
MAX
2
5
7.7
2
8.5
2
8.5
4
7
9.3
4
10.5
4
10.5
2.2
5.5
8.3
2.2
9.1
2.2
9.1
2.8
6.4
10
2.8
10.9
2.8
10.9
6
8.8
11
6
11.9
6
11.9
5.1
7.9
10
5.1
10.6
5.1
10.6
3.6
6.2
7.9
3.6
8.9
3.6
8.9
4.4
7.1
9.4
4.4
10.5
4.4
10.5
5
7.8
10.1
5
10.8
5
10.8
4.1
6.7
9.1
4.1
9.6
4.1
9.6
UNIT
ns
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
Power dissipation capacitance per transceiver
Outputs disabled
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TYP
UNIT
57
CL = 50 pF,
f = 1 MHz
10
pF
SCAS184A − JUNE 1990 − REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
Output
Control
(low-level
enabling)
LOAD CIRCUIT
3V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
50% VCC
S1
Open
2 × VCC
GND
3V
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
VOL
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
Output
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
50% VCC
20% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
[ VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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