SDZS009 − D3418, JANUARY 1990
•
•
•
•
•
DW OR NT PACKAGE
(TOP VIEW)
100K Compatible
ECL Clock and TTL Control Inputs
Flow-Through Architecture Optimizes PCB
Layout
Center Pin VCC, VEE, and GND
Configurations Minimize High-Speed
Switching Noise
Package Options Include “Small Outline”
Packages and Standard Plastic DIPs
1Q
2Q
3Q
4Q
VCC
GND
GND
GND
5Q
6Q
7Q
8Q
description
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
1D
2D
3D
4D
OE(TTL)
VEE
GND
CLK(ECL)
5D
6D
7D
8D
This octal ECL-to-TTL translator is designed to
14
11
provide efficient translation between a 100K ECL
13
12
signal environment and a TTL signal environment.
This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented
functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The eight flip-flops of the SN100KT5574 are edge-triggered D-type flip-flops. On the positive transition of the
clock, the Q outputs are set to the logic levels that were set up at the D inputs.
A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive
bus lines without need for interface or pullup components.
The output-enable input OE does not affect the internal operations of the flip-flops. Old data can be retained
or new data can be entered while the outputs are off.
The SN100KT5574 is characterized for operation from 0°C to 85°C.
FUNCTION TABLE
OUTPUT
(TTL)
INPUTS
OE
CLK
D
Q
L
↑
L
L
L
↑
H
H
L
L
X
Qo
H
X
X
Z
Copyright 1990, Texas Instruments Incorporated
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(""!'#'$,
POST OFFICE BOX 655303
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1
logic symbol†
CLK
17
20
OE
1D
2D
3D
4D
5D
6D
7D
8D
logic diagram (positive logic)
24
ECL/TTL
C1
OE
EN
1D
CLK
ECL/TTL
1
23
2
22
3
21
4
16
9
15
10
14
11
13
12
1Q
1D
20
17
ECL/TTL
24
ECL/TTL
C1
1D
1
C1
2
2Q
3Q
4Q
2D
23
ECL/TTL
5Q
6Q
3D
ECL/TTL
8Q
4D
5D
6D
7D
16
15
14
ECL/TTL
C1
8D
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• DALLAS, TEXAS 75265
4
9
ECL/TTL
1D
10
ECL/TTL
C1
1D
C1
11
ECL/TTL
ECL/TTL
3Q
4Q
1D
5Q
6Q
7Q
1D
C1
13
3
1D
C1
21
2Q
1D
C1
22
7Q
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2
1Q
1D
12
8Q
absolute maximum ratings over operating temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Supply voltage range, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V to 0 V
Input voltage range: TTL (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V
ECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE to 0 V
Voltage applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Voltage applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC
Input current range, TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The TTL input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
MIN
NOM
MAX
UNIT
VCC
VEE
TTL supply voltage
4.5
5
5.5
V
ECL supply voltage
−4.2
−4.5
−4.8
V
VIH
VIL
TTL high-level input voltage
TTL low-level input voltage
0.8
V
IIK
VIH
TTL input clamp current
−18
mA
−1150
−840
mV
−1810
−1490
mV
−15
mA
VIL
IOH
2
ECL high-level input voltage‡
ECL low-level input voltage‡
High-level output current
V
IOL
Low-level output current
48
mA
TA
Operating temperature range
0
85
°C
‡ The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic levels only.
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3
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
OE only
TEST CONDITIONS
MIN
VCC = 4.5 V,
VCC = 4.5 V,
VEE = − 4.2 V,
VEE = − 4.5 V ± 0.3 V,
II = − 18 mA
IOH = − 3 mA
VCC = 4.5 V,
VCC = 4.5 V,
VEE = − 4.5 V ± 0.3 V,
VEE = − 4.5 V ± 0.3 V,
IOH = − 15 mA
IOL = 48 mA
VCC = 5.5 V,
VCC = 5.5 V,
VEE = − 4.8 V,
VEE = − 4.8 V,
VI = 7 V
VI = 2.7 V
VCC = 5.5 V,
VCC = 5.5 V,
VEE = − 4.8 V,
VEE = − 4.8 V,
VI = 0.5 V
VIH = − 840 mV
VCC = 5.5 V,
VCC = 5.5 V,
VEE = − 4.8 V,
VEE = − 4.8 V,
VIL = − 1810 mV
VO = 2.7 V
VCC = 5.5 V,
VCC = 5.5 V,
VEE = − 4.8 V,
VEE = − 4.8 V,
VO = 0.5 V
VO = 0 V
ICCH
ICCL
VCC = 5.5 V,
VCC = 5.5 V,
VEE = − 4.8 V
VEE = − 4.8 V
ICCZ
IEE
VCC = 5.5 V,
VCC = 5.5 V,
VEE = − 4.8 V
VEE = − 4.8 V
Ci
VCC = 5.5 V,
VCC = 5.5 V,
VEE = − 4.5 V
VEE = − 4.5 V
VOH
VOL
II
OE only
IIH
IIL
OE only
IIH
IIL
Data inputs and CLK
OE only
Data inputs and CLK
IOZH
IOZL
IOS‡
TYP†
2.4
3.3
2
3.1
0.38
MAX
UNIT
−1.2
V
V
0.55
V
0.1
mA
20
µA
−0.5
mA
350
µA
µA
0.50
50
µA
−225
mA
66
95
mA
76
110
mA
74
106
mA
−43
−61
mA
−100
Co
† All typical values are at VCC = 5 V, VEE = − 4.5 V, TA = 25°C.
‡ Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
µA
−50
5
pF
7
pF
timing requirements
VCC = 4.5 V to 5.5 V,
VEE = − 4.2 V to − 4.8 V,
TA = MIN to MAX§
MIN
tw
Pulse duration
th
Hold time after CLK↑
tsu
Setup time before CLK↑
CLK high
4
CLK low
4
Data high
1
Data low
1
Data high
1
Data low
1
§ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
4
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UNIT
MAX
ns
ns
ns
switching characteristics over recommended ranges of operating free-air temperature and supply
voltage (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
FROM
TO
(INPUT)
(OUTPUT)
CLK
Q
OE
Q
OE
tPLZ
† All typical values are at VCC = 5 V, VEE = − 4.5 V, TA = 25°C.
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Q
• DALLAS, TEXAS 75265
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω
MIN TYP†
MAX
UNIT
200
300
MHz
2.3
4.1
7
2.9
4.6
7.4
1.9
3.6
6.3
2.7
4.8
7.7
2.1
3.9
6.1
0.5
3.4
6.3
ns
ns
ns
5
PARAMETER MEASUREMENT INFORMATION
7V
Open
SWITCH POSITION TABLE
S1
From Output
Under Test
Test Point
CL
(See Note A)
S1
Open
Open
Open
Closed
Open
Closed
TEST
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
R1
R2
LOAD CIRCUIT
tf
tr
ECL Input
(See Note C)
80% 80%
50%
20%
−950 mV
50%
20%
1.5 V
Low-Level
Input
VOLTAGE WAVEFORMS
PULSE DURATION
tPHL
1.5 V
1.5 V
VOL
tr
tf
80% 80%
50%
50%
20%
1.5 V
0
tPLZ
Output
Waveform 1
(See Note D)
80% 80%
50%
−950 mV
50%
20%
tr
Output
Waveform 2
(See Note D)
tPHZ
VOL
0.3 V
VOH
1.5 V
0.3 V
0
−1690 mV
tf
3.5 V
1.5 V
−1690 mV
th
1.5 V
tPZL
tPZH
tsu
Data
Input
20%
−950 mV
3V
Output
Control
(Low-Level
Enabling)
VOLTAGE WAVEFORMS
ECL-INPUT PROPAGATION DELAY TIMES
20%
50%
−1690 mV
VOL
VOH
Timing
Input
50%
1.5 V
tPLH
In-Phase
TTL Output
−1690 mV
tw
−950 mV
VOH
Out-of-Phase
TTL Output
50%
50%
−1690 mV
tPLH
tPHL
−950 mV
High-Level
Input
VOLTAGE WAVEFORMS
TTL ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A.CL includes probe and jig capacitance.
B. For TTL inputs, input pulses are supplied by generators having the following characteristics PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns,
tf ≤ 2.5 ns.
C. For ECL inputs, input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 0.7 ns,
tf ≤ 0.7 ns.
D. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
E. The outputs are measured one at a time with one transition per measurement.
figure 1. load circuit and voltage waveforms
6
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