PHILIPS 74AVCH8T245BQ

74AVCH8T245
8-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 02 — 28 April 2009
Product data sheet
1. General description
The 74AVCH8T245 is an 8-bit, dual supply transceiver that enables bidirectional level
translation. It features two data input-output ports (An and Bn), a direction control input
(DIR), a output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A)
and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device
suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V and 3.3 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are
referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on
DIR allows transmission from B to A. The output enable input (OE) can be used to disable
the outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A and B outputs are in the high-impedance OFF-state. The bus-hold
circuitry on the powered-up side always stays active.
The 74AVCH8T245 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features
n Wide supply voltage range:
u VCC(A): 0.8 V to 3.6 V
u VCC(B): 0.8 V to 3.6 V
n Complies with JEDEC standards:
u JESD8-12 (0.8 V to 1.3 V)
u JESD8-11 (0.9 V to 1.65 V)
u JESD8-7 (1.2 V to 1.95 V)
u JESD8-5 (1.8 V to 2.7 V)
u JESD8-B (2.7 V to 3.6 V)
n ESD protection:
u HBM JESD22-A114E Class 3B exceeds 8000 V
u MM JESD22-A115-A exceeds 200 V
u CDM JESD22-C101C exceeds 1000 V
n Maximum data rates:
u 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
u 260 Mbit/s (≥ 1.1 V to 3.3 V translation)
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
n
n
n
n
n
n
n
u 260 Mbit/s (≥ 1.1 V to 2.5 V translation)
u 210 Mbit/s (≥ 1.1 V to 1.8 V translation)
u 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
u 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
74AVCH8T245PW −40 °C to +125 °C
TSSOP24
74AVCH8T245BQ −40 °C to +125 °C
DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1
thin quad flat package; no leads; 24 terminals;
body 3.5 × 5.5 × 0.85 mm
4. Functional diagram
B1
B2
21
VCC(A)
OE
DIR
Fig 1.
B3
20
B4
19
B5
18
B6
17
B7
16
B8
15
14
VCC(B)
22
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
10
A8
001aai472
Logic symbol
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
2 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
DIR
OE
A1
B1
VCC(A)
VCC(B)
to other seven channels
Fig 2.
001aai473
Logic diagram (one channel)
5. Pinning information
5.1 Pinning
terminal 1
index area
1
74AVCH8T245
24 VCC(B)
VCC(A)
74AVCH8T245
DIR
2
23 VCC(B)
VCC(A)
1
24 VCC(B)
A1
3
22 OE
DIR
2
23 VCC(B)
A2
4
21 B1
A1
3
22 OE
A3
5
20 B2
A2
4
21 B1
A4
6
19 B3
A3
5
20 B2
A5
7
18 B4
A4
6
19 B3
A6
8
17 B5
A5
7
18 B4
A7
9
A6
8
17 B5
A7
9
16 B6
A8 10
15 B7
GND 11
14 B8
GND 12
13 GND
16 B6
GND(1)
A8 10
15 B7
GND 13
14 B8
GND 12
GND 11
001aai488
Transparent top view
001aai487
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 3. Pin configuration TSSOP24
Fig 4. Pin configuration DHVQFN24
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
3 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
VCC(A)
1
supply voltage A (An, OE and DIR inputs are referenced to VCC(A))
DIR
2
direction control
A1 to A8
3, 4, 5, 6, 7, 8, 9, 10
data input or output
GND[1]
11
ground (0 V)
GND[1]
12
ground (0 V)
GND[1]
13
ground (0 V)
B1 to B8
21, 20, 19, 18, 17, 16, 15, 14 data input or output
OE
22
output enable input (active LOW)
VCC(B)
23
supply voltage B (Bn inputs are referenced to VCC(B))
VCC(B)
24
supply voltage B (Bn inputs are referenced to VCC(B))
[1]
All GND pins must be connected to ground (0 V).
6. Functional description
Table 3.
Function table[1]
Input/output[3]
Supply voltage
Input
VCC(A), VCC(B)
OE[2]
DIR[2]
An[2]
Bn
0.8 V to 3.6 V
L
L
An = Bn
input
0.8 V to 3.6 V
L
H
input
Bn = An
0.8 V to 3.6 V
H
X
Z
Z
GND[3]
X
X
Z
Z
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2]
The An, DIR and OE input circuit is referenced to VCC(A); The Bn input circuit is referenced to VCC(B).
[3]
If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC(A)
Min
Max
Unit
supply voltage A
−0.5
+4.6
V
VCC(B)
supply voltage B
−0.5
+4.6
V
IIK
input clamping current
VI
input voltage
IOK
output clamping current
VO
output voltage
Conditions
VI < 0 V
[1]
-
mA
+4.6
V
−50
-
mA
[1][2][3]
−0.5
VCCO + 0.5
V
[1]
VO < 0 V
Active mode
−50
−0.5
−0.5
+4.6
V
IO
output current
VO = 0 V to VCC
-
±50
mA
ICC
supply current
ICC(A) or ICC(B)
-
100
mA
Suspend or 3-state mode
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
4 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Table 4.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
IGND
ground current
Tstg
storage temperature
Conditions
Tamb = −40 °C to +125 °C
total power dissipation
Ptot
[4]
Min
Max
Unit
−100
-
mA
−65
+150
°C
-
500
mW
[1]
The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
VCCO is the supply voltage associated with the output port.
[3]
VCCO + 0.5 V should not exceed 4.6 V.
[4]
For TSSOP24 package: Ptot derates linearly at 5.5 mW/K above 60 °C.
For DHVQFN24 package: Ptot derates linearly at 4.5 mW/K above 60 °C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol
Parameter
VCC(A)
Conditions
Min
Max
Unit
supply voltage A
0.8
3.6
V
VCC(B)
supply voltage B
0.8
3.6
V
VI
input voltage
0
3.6
V
0
VCCO
V
0
3.6
V
−40
+125
°C
-
5
ns/V
output voltage
VO
Active mode
[1]
Suspend or 3-state mode
Tamb
ambient temperature
∆t/∆V
input transition rise and fall rate
VCCI = 0.8 V to 3.6 V
[1]
VCCO is the supply voltage associated with the output port.
[2]
VCCI is the supply voltage associated with the input port.
[2]
9. Static characteristics
Table 6.
Typical static characteristics at Tamb = 25 °C[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOH
HIGH-level output voltage
Conditions
Min
Typ
Max
Unit
-
0.69
-
V
-
V
VI = VIH or VIL
IO = −1.5 mA; VCC(A) = VCC(B) = 0.8 V
VOL
LOW-level output voltage
VI = VIH or VIL
II
input leakage current
DIR, OE input; VI = 0 V or 3.6 V;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IBHL
bus hold LOW current
A or B port; VI = 0.42 V; VCC(A) = VCC(B) = 1.2 V
IO = 1.5 mA; VCC(A) = VCC(B) = 0.8 V
-
0.07
-
±0.025 ±0.25 µA
[3]
-
26
-
µA
IBHH
bus hold HIGH current
A or B port; VI = 0.78 V; VCC(A) = VCC(B) = 1.2 V
[4]
-
−24
-
µA
IBHLO
bus hold LOW overdrive
current
A or B port; VCC(A) = VCC(B) = 1.2 V
[5]
-
27
-
µA
IBHHO
bus hold HIGH overdrive
current
A or B port; VCC(A) = VCC(B) = 1.2 V
[6]
-
−26
-
µA
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
5 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Table 6.
Typical static characteristics at Tamb = 25 °C[1][2] …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
IOZ
Conditions
OFF-state output current
power-off leakage current
IOFF
Min
Typ
Max
Unit
A or B port; VO = 0 V or VCCO;
VCC(A) = VCC(B) = 3.6 V
[7]
-
±0.5
±2.5
µA
suspend mode A port; VO = 0 V or VCCO;
VCC(A) = 3.6 V; VCC(B) = 0 V
[7]
-
±0.5
±2.5
µA
suspend mode B port; VO = 0 V or VCCO;
VCC(A) = 0 V; VCC(B) = 3.6 V
[7]
-
±0.5
±2.5
µA
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
-
±0.1
±1
µA
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
-
±0.1
±1
µA
CI
input capacitance
DIR, OE input; VI = 0 V or 3.3 V;
VCC(A) = VCC(B) = 3.3 V
-
1.5
-
pF
CI/O
input/output capacitance
A and B port; VO = 3.3 V or 0 V;
VCC(A) = VCC(B) = 3.3 V
-
4.3
-
pF
[1]
VCCO is the supply voltage associated with the output port.
[2]
VCCI is the supply voltage associated with the data input port.
[3]
The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VI to GND
and then raising it to VIL max.
[4]
The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VI to VCC
and then lowering it to VIH min.
[5]
An external driver must source at least IBHLO to switch this node from LOW to HIGH.
[6]
An external driver must sink at least IBHHO to switch this node from HIGH to LOW.
[7]
For I/O ports, the parameter IOZ includes the input leakage current.
Table 7.
Static characteristics [1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
−40 °C to +85 °C
Conditions
−40 °C to +125 °C
Unit
Min
Max
Min
Max
0.70VCCI
-
0.70VCCI
-
V
VCCI = 1.1 V to 1.95 V
0.65VCCI
-
0.65VCCI
-
V
VCCI = 2.3 V to 2.7 V
1.6
-
1.6
-
V
VCCI = 3.0 V to 3.6 V
2
-
2
-
V
HIGH-level
data input
input voltage
VCCI = 0.8 V
DIR, OE input
VCC(A) = 0.8 V
0.70VCC(A)
-
0.70VCC(A)
-
V
VCC(A) = 1.1 V to 1.95 V
0.65VCC(A)
-
0.65VCC(A)
-
V
VCC(A) = 2.3 V to 2.7 V
1.6
-
1.6
-
V
VCC(A) = 3.0 V to 3.6 V
2
-
2
-
V
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
6 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIL
−40 °C to +85 °C
Conditions
−40 °C to +125 °C
Min
Max
Min
Max
LOW-level
data input
input voltage
VCCI = 0.8 V
Unit
-
0.30VCCI
-
0.30VCCI
V
VCCI = 1.1 V to 1.95 V
-
0.35VCCI
-
0.35VCCI
V
VCCI = 2.3 V to 2.7 V
-
0.7
-
0.7
V
VCCI = 3.0 V to 3.6 V
-
0.8
-
0.8
V
VCC(A) = 0.8 V
-
0.30VCC(A)
-
0.30VCC(A) V
VCC(A) = 1.1 V to 1.95 V
-
0.35VCC(A)
-
0.35VCC(A) V
VCC(A) = 2.3 V to 2.7 V
-
0.7
-
0.7
V
VCC(A) = 3.0 V to 3.6 V
-
0.8
-
0.8
V
VCCO − 0.1
-
VCCO − 0.1
-
V
IO = −3 mA;
VCC(A) = VCC(B) = 1.1 V
0.85
-
0.85
-
V
IO = −6 mA;
VCC(A) = VCC(B) = 1.4 V
1.05
-
1.05
-
V
IO = −8 mA;
VCC(A) = VCC(B) = 1.65 V
1.2
-
1.2
-
V
IO = −9 mA;
VCC(A) = VCC(B) = 2.3 V
1.75
-
1.75
-
V
IO = −12 mA;
VCC(A) = VCC(B) = 3.0 V
2.3
-
2.3
-
V
IO = 100 µA;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
-
0.1
-
0.1
V
IO = 3 mA; VCC(A) = VCC(B) = 1.1 V
-
0.25
-
0.25
V
IO = 6 mA; VCC(A) = VCC(B) = 1.4 V
-
0.35
-
0.35
V
IO = 8 mA;
VCC(A) = VCC(B) = 1.65 V
-
0.45
-
0.45
V
IO = 9 mA; VCC(A) = VCC(B) = 2.3 V
-
0.55
-
0.55
V
IO = 12 mA;
VCC(A) = VCC(B) = 3.0 V
-
0.7
-
0.7
V
-
±1
-
±5
µA
VI = 0.49 V; VCC(A) = VCC(B) = 1.4 V
15
-
15
-
µA
VI = 0.58 V;
VCC(A) = VCC(B) = 1.65 V
25
-
25
-
µA
VI = 0.70 V; VCC(A) = VCC(B) = 2.3 V
45
-
45
-
µA
VI = 0.80 V; VCC(A) = VCC(B) = 3.0 V
100
-
90
-
µA
DIR, OE input
VOH
VOL
HIGH-level
output
voltage
LOW-level
output
voltage
VI = VIH or VIL
IO = −100 µA;
VCC(A) = VCC(B) = 0.8 V to 3.6 V
VI = VIH or VIL
II
input leakage DIR, OE input; VI = 0 V or 3.6 V;
current
VCC(A) = VCC(B) = 0.8 V to 3.6 V
IBHL
bus hold
LOW current
[3]
A or B port
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
7 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
−40 °C to +85 °C
Conditions
Min
IBHH
bus hold
A or B port
HIGH current
VI = 0.91 V; VCC(A) = VCC(B) = 1.4 V
IBHHO
bus hold
LOW
overdrive
current
bus hold
HIGH
overdrive
current
IOFF
OFF-state
output
current
power-off
leakage
current
−15
-
−15
-
µA
−25
-
−25
-
µA
VI = 1.60 V; VCC(A) = VCC(B) = 2.3 V
−45
-
−45
-
µA
−100
-
−100
-
µA
VCC(A) = VCC(B) = 1.6 V
125
-
125
-
µA
VCC(A) = VCC(B) = 1.95 V
200
-
200
-
µA
VCC(A) = VCC(B) = 2.7 V
300
-
300
-
µA
VCC(A) = VCC(B) = 3.6 V
500
-
500
-
µA
VCC(A) = VCC(B) = 1.6 V
−125
-
−125
-
µA
VCC(A) = VCC(B) = 1.95 V
−200
-
−200
-
µA
VCC(A) = VCC(B) = 2.7 V
−300
-
−300
-
µA
[5]
A or B port
[6]
A or B port
−500
-
−500
-
µA
A or B port; VO = 0 V or VCCO;
VCC(A) = VCC(B) = 3.6 V
[7]
-
±5
-
±30
µA
suspend mode A port;
VO = 0 V or VCCO; VCC(A) = 3.6 V;
VCC(B) = 0 V
[7]
-
±5
-
±30
µA
suspend mode B port;
VO = 0 V or VCCO; VCC(A) = 0 V;
VCC(B) = 3.6 V
[7]
-
±5
-
±30
µA
A port; VI or VO = 0 V to 3.6 V;
VCC(A) = 0 V; VCC(B) = 0.8 V to 3.6 V
-
±5
-
±30
µA
B port; VI or VO = 0 V to 3.6 V;
VCC(B) = 0 V; VCC(A) = 0.8 V to 3.6 V
-
±5
-
±30
µA
74AVCH8T245_2
Product data sheet
Max
VI = 1.07 V;
VCC(A) = VCC(B) = 1.65 V
VCC(A) = VCC(B) = 3.6 V
IOZ
Min
Unit
[4]
VI = 2.00 V; VCC(A) = VCC(B) = 3.0 V
IBHLO
Max
−40 °C to +125 °C
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
8 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued[1][2]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
ICC
supply
current
−40 °C to +85 °C
Conditions
−40 °C to +125 °C
Unit
Min
Max
Min
Max
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
10
-
55
µA
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
-
8
-
50
µA
VCC(A) = 3.6 V; VCC(B) = 0 V
-
8
-
50
µA
VCC(A) = 0 V; VCC(B) = 3.6 V
−2
-
−12
-
µA
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
10
-
55
µA
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
-
8
-
50
µA
−2
-
−12
-
µA
A port; VI = 0 V or VCCI; IO = 0 A
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A) = 3.6 V; VCC(B) = 0 V
VCC(A) = 0 V; VCC(B) = 3.6 V
-
8
-
50
µA
A plus B port (ICC(A) + ICC(B));
IO = 0 A; VI = 0 V or VCCI;
VCC(A) = 0.8 V to 3.6 V;
VCC(B) = 0.8 V to 3.6 V
-
20
-
70
µA
A plus B port (ICC(A) + ICC(B));
IO = 0 A; VI = 0 V or VCCI;
VCC(A) = 1.1 V to 3.6 V;
VCC(B) = 1.1 V to 3.6 V
-
16
-
65
µA
[1]
VCCO is the supply voltage associated with the output port.
[2]
VCCI is the supply voltage associated with the data input port.
[3]
The bus hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VI to GND
and then raising it to VIL max.
[4]
The bus hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VI to VCC
and then lowering it to VIH min.
[5]
An external driver must source at least IBHLO to switch this node from LOW to HIGH.
[6]
An external driver must sink at least IBHHO to switch this node from HIGH to LOW.
[7]
For I/O ports, the parameter IOZ includes the input leakage current.
Table 8.
VCC(A)
Typical total supply current (ICC(A) + ICC(B))
VCC(B)
Unit
0V
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0V
0
0.1
0.1
0.1
0.1
0.1
0.1
µA
0.8 V
0.1
0.1
0.1
0.1
0.1
0.3
1.6
µA
1.2 V
0.1
0.1
0.1
0.1
0.1
0.1
0.8
µA
1.5 V
0.1
0.1
0.1
0.1
0.1
0.1
0.4
µA
1.8 V
0.1
0.1
0.1
0.1
0.1
0.1
0.2
µA
2.5 V
0.1
0.3
0.1
0.1
0.1
0.1
0.1
µA
3.3 V
0.1
1.6
0.8
0.4
0.2
0.1
0.1
µA
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
9 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
10. Dynamic characteristics
Table 9.
Typical dynamic characteristics at VCC(A) = 0.8 V and Tamb = 25 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6
Symbol Parameter
Conditions
VCC(B)
0.8 V
tpd
[1]
1.8 V
2.5 V
3.3 V
14.4
7.0
6.2
6.0
5.9
6.0
ns
Bn to An
14.4
12.4
12.1
11.9
11.8
11.8
ns
OE to An
16.2
16.2
16.2
16.2
16.2
16.2
ns
OE to Bn
17.6
10.0
9.0
9.1
8.7
9.3
ns
OE to An
21.9
21.9
21.9
21.9
21.9
21.9
ns
OE to Bn
22.2
11.1
9.8
9.4
9.4
9.6
ns
enable time
ten
1.5 V
propagation delay An to Bn
disable time
tdis
1.2 V
Unit
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
Table 10. Typical dynamic characteristics at VCC(B) = 0.8 V and Tamb = 25 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6
Symbol Parameter
tpd
[1]
Unit
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
propagation delay An to Bn
14.4
12.4
12.1
11.9
11.8
11.8
ns
Bn to An
14.4
7.0
6.2
6.0
5.9
6.0
ns
OE to An
16.2
5.9
4.4
4.2
3.1
3.5
ns
OE to Bn
17.6
14.2
13.7
13.6
13.3
13.1
ns
OE to An
21.9
6.4
4.4
3.5
2.6
2.3
ns
OE to Bn
22.2
17.7
17.2
17.0
16.8
16.7
ns
enable time
ten
VCC(A)
0.8 V
disable time
tdis
Conditions
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
10 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C [1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
power dissipation
capacitance
CPD
Conditions
VCC(A) = VCC(B)
0.8 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
A port: (direction A to B);
output enabled
0.2
0.2
0.2
0.3
0.4
0.5
pF
A port: (direction A to B);
output disabled
0.2
0.2
0.2
0.3
0.4
0.5
pF
A port: (direction B to A);
output enabled
9
9
10
10
11
13
pF
A port: (direction B to A);
output disabled
0.6
0.6
0.6
0.7
0.7
0.8
pF
B port: (direction A to B);
output enabled
9
9
10
10
11
13
pF
B port: (direction A to B);
output disabled
0.6
0.6
0.6
0.7
0.7
0.8
pF
B port: (direction B to A);
output enabled
0.2
0.2
0.2
0.3
0.4
0.5
pF
B port: (direction B to A);
output disabled
0.2
0.2
0.2
0.3
0.4
0.5
pF
[1]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
[2]
fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
74AVCH8T245_2
Product data sheet
Unit
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
11 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Table 12. Dynamic characteristics for temperature range −40 °C to +85 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V ± 0.1 V
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V
3.3 V ± 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
0.5
9.0
0.5
6.7
0.5
5.8
0.5
4.9
0.5
4.8
ns
VCC(A) = 1.1 V to 1.3 V
tpd
propagation
delay
An to Bn
Bn to An
0.5
9.0
0.5
8.5
0.5
8.3
0.5
8.0
0.5
7.8
ns
tdis
disable time
OE to An
0.5
11.8
0.5
11.8
0.5
11.8
0.5
11.8
0.5
11.8
ns
OE to Bn
0.5
12.3
0.5
9.5
0.5
9.4
0.5
8.0
0.5
8.9
ns
OE to An
1.1
14.4
1.1
14.4
1.1
14.4
1.1
14.4
1.1
14.4
ns
OE to Bn
1.1
14.2
1.1
10.4
1.1
9.0
1.0
7.7
1.0
7.3
ns
propagation
delay
An to Bn
0.5
8.5
0.5
5.6
0.5
4.7
0.5
4.4
0.5
4.1
ns
Bn to An
0.5
6.7
0.5
5.6
0.5
5.3
0.5
5.2
0.5
5.0
ns
disable time
OE to An
0.5
8.6
0.5
8.6
0.5
8.6
0.5
8.6
0.5
8.6
ns
OE to Bn
0.5
11.2
0.5
8.4
0.5
7.6
0.5
7.2
0.5
7.8
ns
OE to An
1.1
8.7
1.1
8.7
1.1
8.7
1.1
8.7
1.1
8.7
ns
OE to Bn
1.1
12.8
1.1
8.1
1.1
7.1
1.0
5.6
1.0
5.2
ns
enable time
ten
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
enable time
ten
VCC(A) = 1.65 V to 1.95 V
propagation
delay
An to Bn
0.5
8.3
0.5
5.3
0.5
4.5
0.5
3.8
0.5
3.5
ns
Bn to An
0.5
5.8
0.5
4.7
0.5
4.5
0.5
4.3
0.5
4.1
ns
tdis
disable time
OE to An
0.5
7.1
0.5
7.1
0.5
7.1
0.5
7.1
0.5
7.1
ns
OE to Bn
0.5
10.9
0.5
7.8
0.5
6.9
0.5
6.0
0.5
5.8
ns
ten
enable time
OE to An
1.0
6.8
1.0
6.8
1.0
6.8
1.0
6.8
1.0
6.8
ns
OE to Bn
1.1
12.4
1.1
8.2
1.0
6.7
0.5
5.1
0.5
4.5
ns
propagation
delay
An to Bn
0.5
8.0
0.5
5.2
0.5
4.3
0.5
3.3
0.5
2.9
ns
Bn to An
0.5
4.9
0.5
4.4
0.5
3.8
0.5
3.3
0.5
3.1
ns
disable time
OE to An
0.5
5.1
0.5
5.1
0.5
5.1
0.5
5.1
0.5
5.1
ns
OE to Bn
0.5
10.4
0.5
7.1
0.5
6.3
0.5
5.1
0.5
5.2
ns
OE to An
0.5
4.8
0.5
4.8
0.5
4.8
0.5
4.8
0.5
4.8
ns
OE to Bn
1.1
11.9
1.1
7.9
0.5
6.4
0.5
4.6
0.5
4.0
ns
0.5
7.8
0.5
5.0
0.5
4.1
0.5
3.1
0.5
2.7
ns
tpd
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
enable time
ten
VCC(A) = 3.0 V to 3.6 V
tpd
propagation
delay
An to Bn
Bn to An
0.5
4.8
0.5
4.1
0.5
3.5
0.5
2.9
0.5
2.7
ns
tdis
disable time
OE to An
0.5
4.9
0.5
4.9
0.5
4.9
0.5
4.9
0.5
4.9
ns
OE to Bn
0.5
10.1
0.5
6.9
0.5
6.0
0.5
4.8
0.5
5.0
ns
OE to An
0.5
4.0
0.5
4.0
0.5
4.0
0.5
4.0
0.5
4.0
ns
OE to Bn
1.1
11.7
1.1
7.8
0.5
6.2
0.5
4.5
0.5
3.9
ns
enable time
ten
[1]
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
12 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
Table 13. Dynamic characteristics for temperature range −40 °C to +125 °C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V ± 0.1 V
1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V
3.3 V ± 0.3 V
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
0.5
9.9
0.5
7.4
0.5
6.4
0.5
5.4
0.5
5.3
ns
VCC(A) = 1.1 V to 1.3 V
tpd
propagation
delay
An to Bn
Bn to An
0.5
9.9
0.5
9.4
0.5
9.2
0.5
8.8
0.5
8.6
ns
tdis
disable time
OE to An
0.5
13.0
0.5
13.0
0.5
13.0
0.5
13.0
0.5
13.0
ns
OE to Bn
0.5
13.6
0.5
10.5
0.5
10.4
0.5
8.8
0.5
9.8
ns
OE to An
1.1
15.9
1.1
15.9
1.1
15.9
1.1
15.9
1.1
15.9
ns
OE to Bn
1.1
15.7
1.1
11.5
1.1
9.9
1.0
8.5
1.0
8.1
ns
propagation
delay
An to Bn
0.5
9.4
0.5
6.2
0.5
5.2
0.5
4.9
0.5
4.6
ns
Bn to An
0.5
7.4
0.5
6.2
0.5
5.9
0.5
5.8
0.5
5.5
ns
disable time
OE to An
0.5
9.5
0.5
9.5
0.5
9.5
0.5
9.5
0.5
9.5
ns
OE to Bn
0.5
12.4
0.5
9.3
0.5
8.4
0.5
8.0
0.5
8.6
ns
OE to An
1.1
9.6
1.1
9.6
1.1
9.6
1.1
9.6
1.1
9.6
ns
OE to Bn
1.1
14.1
1.1
9.0
1.1
7.9
1.0
6.2
1.0
5.8
ns
enable time
ten
VCC(A) = 1.4 V to 1.6 V
tpd
tdis
enable time
ten
VCC(A) = 1.65 V to 1.95 V
propagation
delay
An to Bn
0.5
9.2
0.5
5.9
0.5
5.0
0.5
4.2
0.5
3.9
ns
Bn to An
0.5
6.4
0.5
5.2
0.5
5.0
0.5
4.8
0.5
4.6
ns
tdis
disable time
OE to An
0.5
7.9
0.5
7.9
0.5
7.9
0.5
7.9
0.5
7.9
ns
OE to Bn
0.5
12.0
0.5
8.6
0.5
7.6
0.5
6.6
0.5
6.4
ns
ten
enable time
OE to An
1.0
7.5
1.0
7.5
1.0
7.5
1.0
7.5
1.0
7.5
ns
OE to Bn
1.1
13.7
1.1
9.1
1.0
7.4
0.5
5.7
0.5
5.0
ns
propagation
delay
An to Bn
0.5
8.8
0.5
5.8
0.5
4.8
0.5
3.7
0.5
3.2
ns
Bn to An
0.5
5.4
0.5
4.9
0.5
4.2
0.5
3.7
0.5
3.5
ns
disable time
OE to An
0.5
5.7
0.5
5.7
0.5
5.7
0.5
5.7
0.5
5.7
ns
OE to Bn
0.5
11.5
0.5
7.9
0.5
7.0
0.5
5.7
0.5
5.8
ns
OE to An
0.5
5.3
0.5
5.3
0.5
5.3
0.5
5.3
0.5
5.3
ns
OE to Bn
1.1
13.1
1.1
8.7
0.5
7.1
0.5
5.1
0.5
4.4
ns
0.5
8.6
0.5
5.5
0.5
4.6
0.5
3.5
0.5
3.0
ns
tpd
VCC(A) = 2.3 V to 2.7 V
tpd
tdis
enable time
ten
VCC(A) = 3.0 V to 3.6 V
tpd
propagation
delay
An to Bn
Bn to An
0.5
5.3
0.5
4.6
0.5
3.9
0.5
3.2
0.5
3.0
ns
tdis
disable time
OE to An
0.5
5.4
0.5
5.4
0.5
5.4
0.5
5.4
0.5
5.4
ns
OE to Bn
0.5
11.2
0.5
7.6
0.5
6.6
0.5
5.3
0.5
5.5
ns
OE to An
0.5
4.4
0.5
4.4
0.5
4.4
0.5
4.4
0.5
4.4
ns
OE to Bn
1.1
12.9
1.1
8.6
0.5
6.9
0.5
5.0
0.5
4.3
ns
enable time
ten
[1]
tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
13 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
11. Waveforms
VI
VM
An, Bn input
GND
tPHL
tPLH
VOH
VM
Bn, An output
VOL
001aai475
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
The data input (An, Bn) to output (Bn, An) propagation delay times
VI
OE input
VM
GND
tPLZ
tPZL
VCCO
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPZH
tPHZ
VOH
VY
output
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
enabled
outputs
disabled
001aai474
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
Table 14.
Enable and disable times
Measurement points
Supply voltage
Input[1]
Output[2]
VCC(A), VCC(B)
VM
VM
VX
VY
0.8 V to 1.6 V
0.5VCCI
0.5VCCO
VOL + 0.1 V
VOH − 0.1 V
1.65 V to 2.7 V
0.5VCCI
0.5VCCO
VOL + 0.15 V
VOH − 0.15 V
3.0 V to 3.6 V
0.5VCCI
0.5VCCO
VOL + 0.3 V
VOH − 0.3 V
[1]
VCCI is the supply voltage associated with the data input port.
[2]
VCCO is the supply voltage associated with the output port.
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
14 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
tW
VI
90 %
negative
pulse
VM
VM
10 %
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
VM
VM
10 %
0V
tW
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
001aae331
Test data is given in Table 15.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
VEXT = External voltage for measuring switching times.
Fig 7.
Table 15.
Load circuit for switching times
Test data
Supply voltage
Input
VCC(A), VCC(B)
VI[1]
∆t/∆V[2]
Load
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ[3]
0.8 V to 1.6 V
VCCI
≤ 1.0 ns/V
15 pF
2 kΩ
open
GND
2VCCO
1.65 V to 2.7 V
VCCI
≤ 1.0 ns/V
15 pF
2 kΩ
open
GND
2VCCO
3.0 V to 3.6 V
VCCI
≤ 1.0 ns/V
15 pF
2 kΩ
open
GND
2VCCO
[1]
VCCI is the supply voltage associated with the data input port.
[2]
dV/dt ≥ 1.0 V/ns
[3]
VCCO is the supply voltage associated with the output port.
VEXT
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
15 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
12. Typical propagation delay characteristics
001aai476
24
tpd
(ns)
(1)
(2)
(3)
(4)
(5)
(6)
tpd
(ns)
(1)
20
001aai477
21
17
16
12
13
(2)
(3)
(4)
(5)
(6)
8
4
9
0
20
40
60
0
CL (pF)
40
60
CL (pF)
a. Propagation delay (A to B); VCC(A) = 0.8 V
b. Propagation delay (A to B); VCC(B) = 0.8 V
(1) VCC(B) = 0.8 V.
(1) VCC(A) = 0.8 V.
(2) VCC(B) = 1.2 V.
(2) VCC(A) = 1.2 V.
(3) VCC(B) = 1.5 V.
(3) VCC(A) = 1.5 V.
(4) VCC(B) = 1.8 V.
(4) VCC(A) = 1.8 V.
(5) VCC(B) = 2.5 V.
(5) VCC(A) = 2.5 V.
(6) VCC(B) = 3.3 V.
(6) VCC(A) = 3.3 V.
Fig 8.
20
Typical propagation delay vs load capacitance; Tamb = 25 °C
74AVCH8T245_2
Product data sheet
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Rev. 02 — 28 April 2009
16 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
001aai478
7
001aai491
7
(1)
tPLH
(ns)
tPHL
(ns)
(1)
(2)
5
5
(3)
(2)
(3)
(4)
(4)
(5)
(5)
3
3
1
1
0
20
40
60
0
20
40
CL (pF)
a. LOW to HIGH propagation delay (A to B);
VCC(A) = 1.2 V
b. HIGH to LOW propagation delay (A to B);
VCC(A) = 1.2 V
001aai479
7
60
CL (pF)
001aai480
7
(1)
tPLH
(ns)
tPHL
(ns)
(1)
5
5
(2)
(3)
(2)
(3)
(4)
(5)
3
(4)
(5)
3
1
1
0
20
40
60
0
CL (pF)
20
40
60
CL (pF)
c. LOW to HIGH propagation delay (A to B);
VCC(A) = 1.5 V
d. HIGH to LOW propagation delay (A to B);
VCC(A) = 1.5 V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 9.
Typical propagation delay vs load capacitance; Tamb = 25 °C
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
17 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
001aai481
7
(1)
tPLH
(ns)
001aai482
7
tPHL
(ns)
5
(1)
5
(2)
(3)
(2)
(3)
(4)
3
(4)
(5)
3
(5)
1
1
0
20
40
60
0
20
40
CL (pF)
a. LOW to HIGH propagation delay (A to B);
VCC(A) = 1.8 V
b. HIGH to LOW propagation delay (A to B);
VCC(A) = 1.8 V
001aai483
7
tPLH
(ns)
60
CL (pF)
001aai486
7
tPHL
(ns)
(1)
5
(1)
5
(2)
(2)
(3)
(3)
(4)
3
3
(4)
(5)
(5)
1
1
0
20
40
60
0
CL (pF)
20
40
60
CL (pF)
c. LOW to HIGH propagation delay (A to B);
VCC(A) = 2.5 V
d. HIGH to LOW propagation delay (A to B);
VCC(A) = 2.5 V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 10. Typical propagation delay vs load capacitance; Tamb = 25 °C
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
18 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
001aai485
7
tPLH
(ns)
001aai484
7
tPHL
(ns)
(1)
5
(1)
5
(2)
(2)
(3)
(3)
3
3
(4)
(4)
(5)
(5)
1
1
0
20
40
60
0
CL (pF)
20
40
60
CL (pF)
a. LOW to HIGH propagation delay (A to B);
VCC(A) = 3.3 V
b. HIGH to LOW propagation delay (A to B);
VCC(A) = 3.3 V
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
Fig 11. Typical propagation delay vs load capacitance; Tamb = 25 °C
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
19 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
13. Package outline
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
D
SOT355-1
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT355-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 12. Package outline SOT355-1 (TSSOP24)
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
20 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
B
D
SOT815-1
A
A
E
A1
c
detail X
terminal 1
index area
C
e1
terminal 1
index area
e
y1 C
v M C A B
w M C
b
2
y
11
L
12
1
e2
Eh
24
13
23
14
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
5.6
5.4
4.25
3.95
3.6
3.4
2.25
1.95
0.5
4.5
1.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT815-1
---
---
---
EUROPEAN
PROJECTION
ISSUE DATE
03-04-29
Fig 13. Package outline SOT815-1 (DHVQFN24)
74AVCH8T245_2
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
21 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
14. Abbreviations
Table 16.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
15. Revision history
Table 17.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AVCH8T245_2
20090428
Product data sheet
-
74AVCH8T245_1
Modifications:
•
Section 5 “Pinning information”:
Changed: pin names changed in pin description table.
74AVCH8T245_1
20080709
Product data sheet
74AVCH8T245_2
Product data sheet
-
-
© NXP B.V. 2009. All rights reserved.
Rev. 02 — 28 April 2009
22 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74AVCH8T245_2
Product data sheet
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Rev. 02 — 28 April 2009
23 of 24
74AVCH8T245
NXP Semiconductors
8-bit dual supply translating transceiver; 3-state
18. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Typical propagation delay characteristics. . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 20
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22
Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Contact information. . . . . . . . . . . . . . . . . . . . . 23
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 28 April 2009
Document identifier: 74AVCH8T245_2