Revised June 2005
74VCXH16374
Low Voltage 16-Bit D-Type Flip-Flops with Bushold
General Description
The VCXH16374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock (CP) and output enable (OE) are common to
each byte and can be shorted together for full 16-bit operation.
The VCXH16374 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The 74VCXH16374 is designed for low voltage (1.4V to
3.6V) VCC applications with output compatibility up to 3.6V.
The 74VCXH16374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
■ 1.4V to 3.6V VCC supply operation
■ 3.6V tolerant control inputs and outputs
■ Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
■ tPD
3.0 ns max for 3.0V to 3.6V VCC
■ Static Drive (IOH/IOL)
r24 mA @ 3.0V VCC
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
Human body model ! 2000V
Machine model ! 200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number
74VCXH16374GX
(Note 1)
Package Number
BGA54A
(Preliminary)
74VCXH16374MTD
(Note 2)
MTD48
Package Descriptions
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: BGA package available in Tape and Reel only.
Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS500228
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74VCXH16374 Low Voltage 16-Bit D-Type Flip-Flops with Bushold
January 2000
74VCXH16374
Connection Diagrams
Pin Descriptions
Pin Assignment for TSSOP
Pin Names
Description
OEn
Output Enable Input (Active LOW)
CPn
Clock Pulse Input
I0–I15
Bushold Inputs
O0–O15
Outputs
NC
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
O0
NC
OE1
CP1
NC
I0
B
O2
O1
NC
NC
I1
I2
C
O4
O3
VCC
VCC
I3
I4
D
O6
O5
GND
GND
I5
I6
E
O8
O7
GND
GND
I7
I8
F
O10
O9
GND
GND
I9
I10
G
O12
O11
VCC
VCC
I11
I12
H
O14
O13
NC
NC
I13
I14
J
O15
NC
OE2
CP2
NC
I15
Truth Tables
Inputs
Pin Assignment for FBGA
Outputs
OE1
I0–I7
O0–O7
L
H
H
L
L
L
L
L
X
O0
X
H
X
Z
CP1
Inputs
OE2
I8–I15
O8–O15
L
H
H
L
L
L
L
L
X
O0
X
H
X
Z
CP2
(Top Thru View)
H
L
X
Z
O0
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2
Outputs
HIGH Voltage Level
LOW Voltage Level
Immaterial (HIGH or LOW, control inputs may not float)
High Impedance
Previous O0 before HIGH-to-LOW of CP
flip-flop will store the state of their individual I inputs that
meet the setup and hold time requirements on the
LOW-to-HIGH Clock (CPn) transition. With the Output
Enable (OEn) LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to
the high impedance state. Operations of the OEn input
does not affect the state of the flip-flops.
The 74VCXH16374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each clock has a buffered clock and buffered Output
Enable common to all flip-flops within that byte. The
description which follows applies to each byte. Each
Logic Diagram
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VCXH16374
Functional Description
74VCXH16374
Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions (Note 5)
0.5V to 4.6V
Supply Voltage (VCC)
DC Input Voltage (VI)
Power Supply
0.5V to 4.6V
0.5V to VCC 0.5V
OEn, CPn
I0 – I15
Output Voltage (VO)
Operating
1.4V to 3.6V
Input Voltage
0.3V to VCC
Output Voltage (VO)
0.5V to 4.6V
0.5V to VCC 0.5V
Outputs 3-STATED
Outputs Active (Note 4)
Output in Active States
DC Input Diode Current (IIK)
50 mA
DC Output Diode Current (IOK)
VO 0V
50 mA
50 mA
VO ! VCC
DC Output Source/Sink Current
VCC
3.0V to 3.6V
VCC
2.3V to 2.7V
VCC
1.65V to 2.3V
VCC
1.4V to 1.6V
Free Air Operating Temperature (TA)
r50 mA
(IOH/IOL)
r24 mA
r18 mA
r6 mA
r2 mA
40qC to 85qC
Minimum Input Edge Rate ('t/'V)
DC VCC or GND Current per
Storage Temperature Range (TSTG)
0.0V to 3.6V
Output Current in IOH/IOL
VI 0V
Supply Pin (ICC or GND)
0V to VCC
Output in “OFF” State
VIN
r100 mA
65qC to 150qC
0.8V to 2.0V, VCC
3.0V
10 ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
Note 5: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
VIH
VIL
Parameter
Conditions
HIGH Level Input Voltage
LOW Level Input Voltage
VCC
(V)
Min
2.7 - 3.6
2.0
2.3 - 2.7
1.6
1.65 - 2.3
0.65 x VCC
1.4 - 1.6
0.65 x VCC
2.7 - 3.6
HIGH Level Output Voltage
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0.8
0.7
1.65 - 2.3
1.35 x VCC
V
1.35 x VCC
IOH
100 PA
2.7 - 3.6
VCC - 0.2
IOH
12 mA
2.7
2.2
IOH
18 mA
3.0
2.4
IOH
24 mA
3.0
2.2
IOH
100 PA
2.3 - 2.7
VCC - 0.2
IOH
6 mA
2.3
2.0
IOH
12 mA
2.3
1.8
IOH
18 mA
2.3
1.7
IOH
100 PA
1.65 - 2.3
VCC - 0.2
IOH
6 mA
IOH
100 PA
IOH
2 mA
4
Units
V
2.3 - 2.7
1.4 - 1.6
VOH
Max
1.65
1.25
1.4 - 1.6
VCC - 0.2
1.4
1.05
V
Symbol
(Continued)
Parameter
Conditions
VCC
Min
Max
Units
(V)
VOL
II
II(HOLD)
II(OD)
IOZ
LOW Level Output Voltage
Input Leakage Current
IOL
100 PA
2.7 - 3.6
0.2
IOL
12 mA
2.7
0.4
IOL
18 mA
3.0
0.4
IOL
24 mA
3.0
0.55
IOL
100 PA
2.3 - 2.7
0.2
IOL
12 mA
2.3
0.4
IOL
18 mA
2.3
0.6
IOL
100 PA
1.65 - 2.3
0.2
IOL
6 mA
1.65
0.3
IOL
100 PA
IOL
2 mA
Control Pins
0 d VI d 3.6V
Data Pins
VI
VCC or GND
0.2
1.4
0.35
2.7 - 3.6
r5.0
2.7 - 3.6
r5.0
Bushold Input Minimum
VIN
0.8V
3.0
75.0
Drive Hold Current
VIN
2.0V
3.0
75.0
VIN
0.7V
2.3
45.0
VIN
1.6V
2.3
45.0
VIN
0.57V
1.65
25.0
VIN
1.07V
1.65
25.0
Bushold Input Over-Drive
(Note 6)
3.6
450
Current to Change State
(Note 7)
3.6
450
(Note 6)
2.7
300
(Note 7)
2.7
300
(Note 6)
1.95
200
(Note 7)
1.95
200
3-STATE Output Leakage
0 d VO d 3.6V
VI
VIH or VIL
IOFF
Power-OFF Leakage Current
0 d (VO) d 3.6V
ICC
Quiescent Supply Current
VI
VCC or GND
VCC d (VO) d 3.6V (Note 8)
'ICC
1.4 - 1.6
Increase in ICC per Input
VIH
VCC 0.6V
V
PA
PA
PA
1.4 - 3.6
r10.0
PA
PA
0
10.0
1.4 - 3.6
20.0
PA
1.4 - 3.6
r20.0
PA
2.7 - 3.6
750
PA
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: Outputs disabled or 3-STATE only.
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74VCXH16374
DC Electrical Characteristics
74VCXH16374
AC Electrical Characteristics
Symbol
fMAX
tPHL
(Note 9)
Parameter
Maximum Clock Frequency
Propagation Delay
Conditions
CL
30 pF
CL
15 pF
CL
pF, RL
500:
tPLH
tPZL
Output Enable Time
tS
tH
tW
Output Disable Time
Setup Time
Hold Time
Pulse Width
tOSHL
Output to Output Skew
tOSLH
(Note 10)
40qC to 85qC
Min
3.3 r 0.3
250
2.5 r 0.2
200
1.8 r 0.15
100
1.5 r 0.1
80.0
3.3 r 0.3
0.8
2.5 r 0.2
1.0
3.9
1.8 r 0.15
1.5
7.8
1.0
15.6
3.0
1.5 r 0.1
CL
30 pF, RL
500:
3.3 r 0.3
0.8
3.5
2.5 r 0.2
1.0
4.6
1.8 r 0.15
1.5
9.2
CL
15 pF, RL
2 k:
1.5 r 0.1
1.0
18.4
CL
30 pF, RL
500:
3.3 r 0.3
0.8
3.5
2.5 r 0.2
1.0
3.8
1.8 r 0.15
1.5
6.8
CL
15 pF, RL
2 k:
1.5 r 0.1
1.0
13.6
CL
30 pF, RL
500:
3.3 r 0.3
1.5
2.5 r 0.2
1.5
1.8 r 0.15
2.5
15 pF, RL
500:
1.5 r 0.1
3.0
CL
30 pF, RL
500:
3.3 r 0.3
1.0
2.5 r 0.2
1.0
1.8 r 0.15
1.0
CL
15 pF, RL
500:
1.5 r 0.1
2.0
CL
30 pF, RL
500:
3.3 r 0.3
1.5
2.5 r 0.2
1.5
1.8 r 0.15
4.0
4.0
CL
15 pF, RL
500:
1.5 r 0.1
CL
30 pF, RL
500:
3.3 r 0.3
0.5
2.5 r 0.2
0.5
1.8 r 0.15
0.75
1.5 r 0.1
1.5
15 pF, RL
2 k:
Figure
Number
MHz
2 k:
CL
Units
Max
15 pF, RL
CL
Note 9: For CL
TA
(V)
CL
tPZH
tPLZ
VCC
ns
Figures
1, 2
Figures
7, 8
ns
Figures
1, 3, 4
Figures
7, 9, 10
ns
Figures
1, 3, 4
Figures
7, 9, 10
ns
Figure 6
ns
Figure 6
ns
Figure 5
ns
50PF, add approximately 300 ps to the AC maximum specification.
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
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6
Symbol
VOLP
VOLV
VOHV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
Quiet Output Dynamic Valley VOH
Conditions
CL
CL
CL
30 pF, VIH
30 pF, VIH
30 pF, VIH
VCC, VIL
VCC, VIL
VCC, VIL
0V
0V
0V
VCC
TA 25qC
(V)
Typical
1.8
0.25
2.5
0.6
3.3
0.8
1.8
0.25
2.5
0.6
3.3
0.8
1.8
1.5
2.5
1.9
3.3
2.2
Units
V
V
V
Capacitance
Symbol
Parameter
Conditions
CIN
Input Capacitance
VCC
COUT
Output Capacitance
VI
0V or VCC, VCC
CPD
Power Dissipation Capacitance
VI
0V or VCC, f
VCC
1.8V, 2.5V or 3.3V, VI
Typical
Units
0V or VCC
6.0
pF
1.8V, 2.5V or 3.3V
7.0
pF
20.0
pF
10 MHz,
1.8V, 2.5V or 3.3V
7
TA 25qC
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74VCXH16374
Dynamic Switching Characteristics
74VCXH16374
AC Loading and Waveforms (VCC 3.3V r 0.3V to 1.8V r 0.15V)
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC 3.3V r 0.3V;
VCC x 2 at VCC 2.5V r 0.2V; 1.8V r 0.15V
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
tREC Waveforms
Symbol
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FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
VCC
3.3V r 0.3V
2.5V r 0.2V
1.8V r 0.15V
Vmi
1.5V
VCC/2
VCC/2
Vmo
1.5V
VCC/2
VCC/2
VX
VOL 0.3V
VOL 0.15V
VOL 0.15V
VY
VOH 0.3V
VOH 0.15V
VOH 0.15V
8
74VCXH16374
AC Loading and Waveforms (VCC 1.5V r 0.1V)
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
VCC x 2 at VCC
tPZH, tPHZ
1.5 r 0.1V
GND
FIGURE 7. AC Test Circuit
FIGURE 8. Waveform for Inverting and Non-Inverting Functions
FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
1.5V r 0.1V
Vmi
VCC/2
Vmo
VCC/2
VX
VOL 0.1V
VY
VOH 0.1V
9
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74VCXH16374
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
(Preliminary)
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74VCXH16374 Low Voltage 16-Bit D-Type Flip-Flops with Bushold
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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