Low Skew, 1-to-4 LVCMOS/LVTTL-to-LVDS Fanout Buffer ICS8545I-02 DATASHEET General Description Features The ICS8545I-02 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8545I-02 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω. The ICS8545I-02 accepts an LVCMOS/LVTTL input level and translates it to 3.3V LVDS output levels. • • Four differential LVDS output pairs • • • • • • • • • Maximum output frequency: 350MHz ICS Guaranteed output and part-to-part skew characteristics make the ICS8545I-02 ideal for those applications demanding well defined performance and repeatability. Q LE 00 CLK2 Pulldown 11 Output skew: 60ps (maximum) Part-to-part skew: 450ps (maximum) Propagation delay: 1.45ns (maximum) Additive phase jitter, RMS: 0.14ps (typical) Full 3.3V supply mode -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package GND CLK_EN CLK_SEL CLK1 nc CLK2 nc nD CLK1 Pulldown Translates LVCMOS/LVTTL input signals to LVDS levels Pin Assignment Block Diagram CLK_EN Pullup Two LVCMOS/LVTTL clock inputs to support redundant or selectable frequency fanout applications CLK_SEL Pulldown Q0 nQ0 Q1 nQ1 OE GND VDD Q2 nQ2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDD Q1 nQ1 Q2 nQ2 GND Q3 nQ3 ICS8545I-02 Q3 nQ3 20-Lead TSSOP OE Pullup 6.5mm x 4.4mm x 0.925mm package body G Package Top View ICS8545AGI-02 REVISION A JULY 29, 2009 1 ©2009 Integrated Device Technology, Inc. ICS8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Table 1. Pin Descriptions Number Name 1, 9, 13 GND Power Type Description 2 CLK_EN Input Pullup 3 CLK_SEL Input Pulldown Clock select input. When HIGH, selects CLK2 input. When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels. 4 CLK1 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. 5, 7 nc Unused 6 CLK2 Input Pulldown 8 OE Input Pullup Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Qx outputs are forced low, nQx outputs are forced high. LVCMOS / LVTTL interface levels. No connect. Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of outputs Q0/nQ0 through Q3/nQ3. LVCMOS/LVTTL interface levels. 10, 18 VDD Power Positive supply pins. 11, 12 nQ3, Q3 Output Differential output pair. LVDS interface levels. 14, 15 nQ2, Q2 Output Differential output pair. LVDS interface levels. 16, 17 nQ1, Q1 Output Differential output pair. LVDS interface levels. 19, 20 nQ0, Q0 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ICS8545AGI-02 REVISION A JULY 29, 2009 Test Conditions 2 Minimum Typical Maximum Units ©2009 Integrated Device Technology, Inc. ICS8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Function Tables Table 3A. Control Input Function Table Inputs Outputs OE CLK_EN CLK_SEL 0 X X 1 0 0 1 0 1 1 Selected Source Q0:Q3 nQ0:nQ3 High-Impedance High-Impedance CLK1 Low High 1 CLK2 Low High 1 0 CLK1 Active Active 1 1 CLK2 Active Active After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK1 and CLK2 inputs as described in Table 3B. Enabled Disabled CLK1, CLK2 CLK_EN nQ[0:3] Q[0:3] Figure 1. CLK_EN Timing Diagram Table 3B. Clock Input Function Table Inputs Outputs CLK1 or CLK2 Q0:Q3 nQ0:nQ3 0 LOW HIGH 1 HIGH LOW ICS8545AGI-02 REVISION A JULY 29, 2009 3 ©2009 Integrated Device Technology, Inc. ICS8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 91.1°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 90 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V CLK1, CLK2, CLK_SEL VDD = VIN = 3.465V 150 µA OE, CLK_EN VDD = VIN = 3.465V 5 µA CLK1, CLK2, CLK_SEL VDD = 3.465V, VIN = 0V -5 µA OE, CLK_EN VDD = 3.465V, VIN = 0V -150 µA Table 4C. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change ICS8545AGI-02 REVISION A JULY 29, 2009 Test Conditions Minimum Typical Maximum Units 525 mV 50 mV 1.25 1.4 V 5 50 mV 275 1.1 4 ©2009 Integrated Device Technology, Inc. ICS8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER AC Electrical Characteristics Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section tsk(o) Output Skew; NOTE 2, 4 tsk(pp) Part-to-Part Skew; NOTE 3, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle; NOTE 5 Test Conditions Minimum Typical 1.0 155.52MHz, Integration Range: 12kHz – 20MHz Maximum Units 350 MHz 1.45 ns 0.14 ps 60 ps 450 ps 20% to 80% 150 700 ps ƒ ≤ 166MHz 45 55 % ƒ > 166MHz 40 60 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Measured using 50% duty cycle. ICS8545AGI-02 REVISION A JULY 29, 2009 5 ©2009 Integrated Device Technology, Inc. ICS8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise dBc/Hz Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.14ps (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This ICS8545AGI-02 REVISION A JULY 29, 2009 is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 6 ©2009 Integrated Device Technology, Inc. ICS8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Parameter Measurement Information VDD SCOPE 3.3V±5% POWER SUPPLY + Float GND – Qx VDD nQ0:nQ3 V LVDS Cross Points PP V CMR Q0:Q3 nQx GND 3.3V LVDS Output Load AC Test Circuit Differential Output Level Par t 1 nQx nQx Qx Qx nQy nQy Par t 2 Qy Qy tsk(o) tsk(pp) Part-to-Part Skew Output Skew nQ0:nQ3 Q0:Q3 CLK1, CLK2 t PW t odc = PERIOD t PW nQ0:nQ3 Q0:Q3 x 100% tPD t PERIOD Output Duty Cycle/Pulse Width/Period ICS8545AGI-02 REVISION A JULY 29, 2009 Propagation Delay 7 ©2009 Integrated Device Technology, Inc. ICS8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Parameter Measurement Information, continued VDD nQ0:nQ3 out VOD 20% 20% Q0:Q3 DC Input LVDS 100 tF tR out Output Rise/Fall Time ➤ VOD/∆ VOD ➤ 80% ➤ 80% Differential Output Voltage Setup VDD out LVDS ➤ DC Input out ➤ VOS/∆ VOS ➤ Offset Voltage Setup ICS8545AGI-02 REVISION A JULY 29, 2009 8 ©2009 Integrated Device Technology, Inc. ICS8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Application Information Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK Inputs LVDS Outputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 3.3V LVDS Driver Termination A general LVDS interface is shown in Figure 2. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50Ω 3.3V LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line Figure 2. Typical LVDS Driver Termination ICS8545AGI-02 REVISION A JULY 29, 2009 9 ©2009 Integrated Device Technology, Inc. ICS8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS8545I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8545I-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 90mA = 311.85mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 91.1°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.312W * 91.1°C/W = 113.4°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS8545AGI-02 REVISION A JULY 29, 2009 0 1 2.5 91.1°C/W 86.7°C/W 84.6°C/W 10 ©2009 Integrated Device Technology, Inc. ICS8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Reliability Information Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 91.1°C/W 86.7°C/W 84.6°C/W Transistor Count The transistor count for ICS8545I-02 is: 360 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS8545AGI-02 REVISION A JULY 29, 2009 11 ©2009 Integrated Device Technology, Inc. ICS8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Ordering Information Table 9. Ordering Information Part/Order Number 8545AGI-02LF 8545AGI-02LFT Marking ICS8545AI02L ICS8545AI02L Package “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS8545AGI-02 REVISION A JULY 29, 2009 12 ©2009 Integrated Device Technology, Inc. ICS8545I-02 Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.