LIN Bus Transceiver with Integrated Voltage Regulator The A8423 provides the physical interface requirements of the LIN (Local Interconnect Network) serial communications bus plus an integrated voltage regulator that is permanently enabled. These allow the development of simple, inexpensive slave nodes in a LIN-Bus system. A8423 SOIC RX 1 8 VREG Regulator EN 2 7 VSUP Control WAKE 3 TX 4 6 LIN 5 GND The LIN transceiver is compatible with LIN-Bus systems that conform to the LIN Protocol Specification, Revision 1.2. It provides all the necessary interface and timing control to convert signals to and from the bidirectional LIN Bus to individual transmit and receive signals at logic-compatible levels. The A8423 provides regulated 5V output with a current limit in excess of 50 mA. This is sufficient to power a microcontroller handling the LIN slave node protocol. The A8423 is supplied in 8-lead plastic SOIC (part number suffix L). FEATURES Compatible with LIN Bus, Revision 1.2 systems Data rate up to 20 kbaud Normal operation from 7 to 30 V ABSOLUTE MAXIMUM RATINGS Supply Voltage, VSUP Continuous.....................30 V Supply Voltage, VSUP Transient (500 ms).........40 V LIN Bus Voltage, LIN........................... –18 to +40 V Wake Pin ............................................... –18 to +40 V Logic Pins: RX, TX, EN ...................... –0.3 V to 7 V Package Power Dissipation, PD ......see chart, page 6 Operating Temperature Range Ambient Temperature, TA ..........–40°C to +125°C Junction Temperature, TJ ...........–55°C to +150°C Storage Temperature, TS ..........–55°C to +150°C Handles 40 V transients during load dump Handles automotive transients per ISO 7637 Unpowered node does not disturb the network 4 kV (hbm) ESD protection on LIN and WAKE pins Low quiescent current regulator for slave microcontroller supply Interface to slave microcontroller 8-pin small outline surface mount package APPLICATIONS Automotive, industrial, and consumer LIN-Bus systems Use the following complete part number when ordering: Part Number Package Description A8423KL 8-lead, SOIC Continuous voltage regulator Datasheet A8423-DS Rev.0 A8423 Preliminary Subject to Change without Notice February 9, 2004 Datasheet A8423-DS Rev.0 Preliminary – Subject to Change Without Notice February 9, 2004 A8423 LIN Bus Transceiver with Integrated Voltage Regulator ELECTRICAL CHARACTERISTICS at TJ = –40°C to 150ºC, VSUP = 7 V to 18 V (unless otherwise noted) Characteristics VSUP Power Supply Operating Voltage Range Symbol VSUP VSUP Supply Current ISUP Supply Standby Current ISTBY Supply Sleep Current Undervoltage Threshold TX and EN Input Low Level Input Voltage High Level Input Voltage Input Hysteresis Pull-Down Resistor Pull-Up Resistor RX Output Low Level Output Current High Level Leakage Current ISLEEP VSUPUV VIL VIH VIHYS RPD RPU IOL IOH Wake Input Low Level Input Voltage VIL High Level Input Voltage VIH Pull-up Current IIL High Level Leakage Current IIH VREG Regulated 5V Supply Output Voltage VREG Output Current Limit IREGLIM External Decoupling Cap Line Regulation Load Regulation LIN Interface Output Short Circuit Current IOSC Output Voltage – Recessive VOR Output Voltage – Dominant VOD High Level Leakage Current IIH Termination Resistance RSLAVE Input Threshold – Dominant VTHDOM Input Threshold – Recessive VTHREC Input Threshold Hysteresis VLINHYS Test Conditions Min. Typ. Max. Units 7 – – – – – – 4.8 – – 0.8 1.5 0.8 1.5 80 5.0 30 40 1 2 1 2 100 5.2 V V mA mA mA mA µA V EN pin TX pin – 2 – 60 60 – – 300 100 100 0.8 – – 200 200 V V mV kΩ kΩ VRX= 0.4 V VRX= 5 V 1.5 – – – – 5 mA µA – VSUP –1 – – – – 40 – VSUP –5 – – 5 V V µA µA 4.5 – 1 – – 5.0 – – – – 5.5 180 – 100 100 V mA µF mV mV Continuous Transient; 500 ms LIN output recessive (High); VWAKE = 0 LIN output dominant (Low); VWAKE= 0 VWAKE= 0, LIN = N.C. LIN = Dominant (Low), Wake = N.C. IREG < 20 µA VWAKE= 0 V VWAKE= VSUP= 30 V IOUT = 0 to 50 mA VREG = 0 V VREG to GND IOUT = 30 mA VSUP = 13.5 V; IOUT = 1 to 30 mA VTX= 5 V; ILIN= 0 mA VTX= 0 V; ILIN= 40 mA VLIN= VSUP VLIN – Recessive to Dominant VLIN – Dominant to Recessive 60 85 110 mA 0.9 VSUP – – V – 1 1.2 V – – 10 µA 20 30 47 kΩ 0.4 VSUP – – V – – 0.6 VSUP V 0.05 VSUP 0.1 VSUP 0.175 VSUP V www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 2 Datasheet A8423-DS Rev.0 Preliminary – Subject to Change Without Notice February 9, 2004 A8423 LIN Bus Transceiver with Integrated Voltage Regulator DYNAMIC CHARACTERISTICS at TJ = –40°C to 150ºC, VSUP = 7 V to 18 V (unless otherwise noted) Characteristics LIN Falling Edge Slew Rate1 LIN Rising Edge Slew Rate1 Symbol Test Conditions SHL 80% to 20% 20% to 80% into >1 kΩ and < 5 nF SLH 20% to 80% into >1 kΩ and < 10 nF tSYM 20% to 80% into > 1 kΩ and < 5 nF TX H → L; LIN crossing 95% tTXL tTXH TX L → H; LIN crossing 5% Min. 1 1 – –2 – – – – – – – – Typ. 2 2 1 – 1.5 1.5 – 3 3 – 1.8 50 Max. 3 3 – 2 4 4 2 6 6 2 – – LIN Rise Fall Symmetry TX Propagation Delay H → L TX Propagation Delay L → H TX Propagation Delay Matching LIN crossing 40%; RX crossing 50% RX Propagation Delay H → L tRXL RX Propagation Delay L → H tRXH LIN crossing 60%; RX crossing 50% RX Propagation Delay Matching Glitch Rejection tGLR +ve and -ve pulse rejection on LIN (to RX) Wake-up Delay (LIN or WAKE) tWL Wake-up to INH Thermal Shutdown Shutdown Temperature TSD – 165 – – 20 – Thermal Shutdown Hysteresis THYS 1Slew rate is controlled during both transitions and will not exceed specified limits at any point between test limits. Units V/µs V/µs V/µs µs µs µs µs µs µs µs µs µs ºC ºC TX 50% LIN 95% tTXL VLIN (%) 40% tTXH 50% 80 20 tRXL Figure 1. Propagation timing definition SLH 5% tRXH RX SHL LIN 60% t Figure 2. Slew rate definition www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3 Datasheet A8423-DS Rev.0 Preliminary – Subject to Change Without Notice February 9, 2004 A8423 LIN Bus Transceiver with Integrated Voltage Regulator Functional Description Power Supply. The device power supply, 13.5 V nominal for automotive applications, is connected to the battery through an external diode, in order to protect against reversal of battery polarity. To comply with the LIN Bus protocol, there must be no more than a 1 V drop between the battery potential and the supply pin. The A8423 operates continuously up to 30 V, and withstands 40 V during a 500 ms load dump. If the supply drops below the undervoltage limit, this condition is detected and the A8423 disables the transmission path and the 5 V regulator, while maintaining a high-impedance state on the LIN terminal. The A8423 does not disturb the LIN Bus in the case of ground disconnection at the module level. In addition, full functionality is maintained with a ground shift of up to 8 V, provided that the difference between GND and VSUP is greater than the undervoltage threshold. LIN Bus Interface. The A8423 integrates all components required to drive and monitor the single-wire LIN Bus as a slave node. An external resistor, diode, and capacitor are normally required for the A8423 to function as a master node. The LIN pin can withstand voltages from +40 V to –18 V with respect to the GND pin without adversly affecting LIN Bus communications between other devices. When the A8423 is in Sleep mode or Standby mode, the LIN pin is in the recessive state. When the A8420/A8421 is the active interface on the LIN Bus, it controls the rise and fall slew rates of the voltage The state of the LIN Bus is determined by the receiver and output as a logic level on the RX pin. This pin is open drain. In Normal mode, RX is active (pull-down) when the LIN Bus is in the dominant (low) state, and RX is inactive (highZ) when the LIN Bus is in the recessive (high) state. In Sleep mode RX is not active (high-Z). When in Standby mode, RX asserts an active low and can be used to indicate to the controlling device that either the wake signal has gone low or that a dominant sate is present on the LIN Bus, indicating that the bus has become active. Operating Mode. The A8423 has three modes of operation: Normal, Standby, and Sleep. The enable input, EN, determines whether Normal mode is maintained (EN high) TX EN WAKE Standby Active→T Active=F EN→0 EN→1 The data to be transmitted is input to the TX pin and converted to LIN Bus signals. A logic high on this pin produces a recessive bus (high) state while a logic low produces a dominant bus (low) state. The TX input has an internal pull-up resistor to ensure a recessive state if the pin is not connected or becomes disconnected. Inputs EN→1 Active=T EN→0 If, while in Sleep mode, the A8423 detects the LIN Bus transitioning into the dominant state, a wake-up signal is generated. This transitions the device from Sleep mode into Standby mode. Logic Functions Active→F Normal level on the LIN pin, such that the rising or falling slew rate does not exceed the specified limits at any point between the 20% and 80% levels. Sleep UVLO POR Figure 3. Operating state. Active is true (T) if WAKE is low (L) or if LIN is low (L). Otherwise, Active is false (F). The UVLO feature overrides. LIN State Norm Outputs RX LIN INH VREG Z Rec(Z) VSUP 5V 1 1 * H 1 1 * L Norm L Rec(Z) VSUP 5V 0 1 * * Norm L Dom(L) VSUP 5V * 0 L1 * Standby L Rec(Z) VSUP 5V * 0 * L1 Standby L Rec(Z) VSUP 5V * 0 H1 H1 Sleep Z Rec(Z) Z Z * 1 * * UVLO Z Rec(Z) Z Off * 1 * H TSD Z Rec(Z) VSUP 5V * 1 * L TSD L Rec(Z) VSUP 5V 1Sleep mode is entered only when LIN is high, WAKE is high, and EN goes to 0. The A8420/A8421 remains in Standby mode when WAKE or LIN is low. 2Z = High Impedance, * = Don’t Care. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 4 Datasheet A8423-DS Rev.0 Preliminary – Subject to Change Without Notice February 9, 2004 A8423 LIN Bus Transceiver with Integrated Voltage Regulator or one of the two inactive modes, Standby or Sleep, are entered (EN low). If no other wake-up signals are active, EN low sets the A8423 into low-current Sleep mode. From Sleep mode the A8423 can be put directly into Normal mode by taking EN high. Alternatively, it can be taken into Standby mode by pulling the WAKE input to ground or by a dominant state on the LIN Bus. the temperature falls below the hysteresis level, the LIN output resumes the state defined by the TX input. During TSD, the output on VREG is maintained. If the supply voltage drops below the UVLO threshold, all outputs are disabled. When the supply voltage rises above the UVLO threshold, the A8423 is reset into the Sleep mode. From that state, it follows the logic shown in figure 1. That is, if Active is true (T), the A8423 immediately goes to Standby mode. If EN is high, it goes directly to the normal mode. In Sleep mode, the supply current is at its minimum level, and the LIN and RX pins are high impedance. In this mode, the linear regulator is still active. When the power is first applied, the A8423 enters Sleep mode directly. Linear Regulator. The A8423 provides a linear regulator From Sleep mode, the A8423 may be taken through the Standby mode, in which the RX output goes low to wake up the protocol control device attached to the TX, RX, and EN pins. Once the controller is active, it may then bring the A8423 into Normal mode by taking EN high. If there is no need to wake the controller prior to enabling the A8423, then simply asserting EN high moves the A8423 directly from Sleep mode to Normal mode. Power Dissipation. Most power will normally be dissi- The EN input has an internal pull-down resistor to ensure a known safe state when the protocol controller is powered off. The WAKE signal is a high-voltage input, which is designed to allow a node on a sleeping bus to be awaken by a local event. Sleep mode may be entered when WAKE is connected directly to the battery or other similar voltage, such as VSUP. To disable Sleep mode and allow the A8423 to enter Standby mode, the WAKE input should be switched to ground. The A8423 incorporates two protection functions. If the die temperature becomes excessive, a thermal shutdown feature (TSD) disables the LIN output dominant-state drive. Once output with specified line and load regulation up to 30 mA at 5 V. The regulator output is current-limited, at typically 100 mA. Care must be taken, however, when operating above 30 mA, due to power dissipation. This is especially important under fault conditions, such as load dump. This output is active all modes, allowing a low-power microcontroller to continuously monitor sensor signals. pated in the linear regulator. Because the output of the regulator is fixed at 5 V, but the input supply can vary between 7 V and 18 V, care must be taken when setting the maximum current. This is particularly important if the ability of the A8423 to withstand a 40 V load dump is to be used. The figures in the charts on the following page show the allowable power dissipation and estimated maximum current for various ambient temperatures and supply voltages. The data were taken using a standard FR4 board with minimal copper (RθJA = 140ºC/W), and using a "High K" dielectric board with copper ground plane and thermal vias (RθJA= 80ºC/W). www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 5 Datasheet A8423-DS Rev.0 Preliminary – Subject to Change Without Notice February 9, 2004 A8423 LIN Bus Transceiver with Integrated Voltage Regulator Allowable Package Power Dissipation, PD 1.2 1.0 "High K" RθJA = 80ºC/W Power (W) 0.8 0.6 0.4 FR4 RθJA = 140ºC/W 0.2 0.0 25 50 75 100 125 150 Ambient Temperature (ºC) Available Current "High K" RθJA = 80ºC/W Available Current FR4 RθJA = 140ºC/W 60.0 60.0 20.0 V Current (mA) Current (mA) 40 7V 30.0 50.0 V 24 12 18 40.0 7V 50.0 V V 10.0 12 40.0 18 30.0 24 20.0 V V V 40 V 10.0 0.0 0.0 25 50 75 100 125 25 Ambient Temperature (ºC) 50 75 100 125 Ambient Temperature (ºC) www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 6 Datasheet A8423-DS Rev.0 Preliminary – Subject to Change Without Notice February 9, 2004 A8423 LIN Bus Transceiver with Integrated Voltage Regulator Terminal List Table Name Description Number RX Receive open drain logic output 1 EN Enable; logic input with internal pull-down 2 High-voltage input controlling modes: active (Standby and Normal) and inactive (Sleep); with pull-up to VSUP 3 Transmit logic input with internal pull-up 4 Ground; connected to battery negative terminal 5 LIN bus connection 6 VSUP Positive supply, 12 V nominal; external diode fitted between the battery and this pin 7 VREG Output providing regulated 5 V at 30 mA 8 WAKE TX GND LIN A8420L and A8421L 8-Pin SOIC .196 4.98 .189 4.80 8” 0” 8 .009 0.23 .007 0.18 .157 3.99 .150 3.81 .034 0.86 .016 0.41 .244 6.20 .229 5.82 1 2 .004 0.10 BSC Seating Plane Gauge Plane .018 0.46 .014 0.36 .022 0.55 REF .050 1.27 BSC .068 1.73 .053 1.35 .010 0.25 .004 0.10 Dimensions in inches Metric dimensions (mm) in brackets, for reference only www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 7 Datasheet A8423-DS Rev.0 Preliminary – Subject to Change Without Notice February 9, 2004 A8423 LIN Bus Transceiver with Integrated Voltage Regulator The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copyright©2004 AllegroMicrosystems, Inc. www.allegromicro.com 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 8