Freescale Semiconductor Advance Information Document Number: MC34670 Rev. 3.0, 12/2006 IEEE 802.3af PD With Current Mode Switching Regulator 34670 The 34670 combines a Power Interface Port for IEEE 802.3af Powered Devices (PD) and a high performance current mode switching regulator. It allows a designer to build PDs with a minimum of external components by means of integrating the required IEEE 802.3af functions and all functions necessary to build a high efficiency DC/DC converter. On the PD side the 34670 fully supports the IEEE802.3af standard and provides complete signature and power classification functions. It controls inrush current limiting and incorporates adjustable undervoltage lockout. The switching regulator provides excellent line and load regulation. It drives an external Power MOSFET with sense resistor. POWER OVER ETHERNET EG SUFFIX (PB-FREE) 98ASB42343B 20-PIN SOICW Features • • • • • • • • • • • • • Integrated IEEE 802.3af Compliant Interface Signature Detection and Classification Functionality Integrated Isolation Switch Programmable Inrush Current Limiting Control Adjustable Undervoltage Lockout Input Voltage Range up to 80 V Current Mode Control Adjustable Oscillator Leading Edge Blanking Internal Slope Compensation Circuitry Input Overvoltage Protection 50% Duty Cycle Limitation Pb-Free Packaging Designated by Suffix Code EG ORDERING INFORMATION Device Temperature Range (TA) Package MCZ34670EG/R2 -40°C to 85°C 20 SOICW RJ-45 PSE HUB OR SWITCH ETHERNET APPLIANCE (PD) TX RX RX TX PHY HOST PROCESSOR PHY SWITCH 48 V POWER SUPPLY HOST CONTROLLER PSE POWER CONTROLLER -48V CAT 5 CABLE GND -48V PD POWER CONTROLLER ISOLATION SWITCH Figure 1. 34670 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2006. All rights reserved. 34670 DC/DC INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM FREQ HIGH VOLTAGE REGULATOR VPWR VDD 2.5V 8V INTERNAL SUPPLY 0.8R 5.7V R POR RCLA S R OSC GATE Q EN R 3.5V UV or UVLO UNDERVOLTAGE UV or UVLO LOCKOUT OVERVOLTAGE DETECTION 5µA + SS 0.3V CONTROL LOGIC S 4.5V Q R 5kΩ PWM COMPARATOR 0.6 - 2.6V 0.4V BLANK CS 1.4V 0.6V CURRENT LIMITATION ILIM UVLO + VIN 250mV RSENSE 3 + SLOPE COMP GATE DRIVE COMP FB TEMP SENSOR 1.2V REG DETECT VOUT RESET Figure 2. 34670 Simplified Internal Block Diagram 34670 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS VPWR 1 20 VDD VPWR 2 19 GATE RCLA 3 18 CS UVLO 4 17 FB TEST1 5 16 COMP TEST2 6 15 SS FREQ 7 14 RESET ILIM 8 13 VOUT VIN 9 12 VOUT VIN 10 11 VOUT Figure 3. 34670 Pin Connections Table 1. 34670 Pin Definitions Pin Number Pin Name Formal Name Definition 1, 2 VPWR Positive Supply Voltage Input This is the most positive power supply input. The load connects between this pin and the VOUT pin. 3 RCLA Classification Resistor Connect a resistor between RCLA and VIN to select the class of the PD. 4 UVLO Undervoltage Lookout Used to adjust the undervoltage lookout threshold voltage, connected to VIN to use the default threshold voltage. 5 TEST1 Test pins 6 TEST2 7 FREQ Frequency Adjustment 8 ILIM Inrush Current Limit 9 VIN Negative Supply Voltage 10 VIN 11, 12 VOUT Output Voltage This pin is the drain of the internal Power MOSFET (high current path). 13 VOUT Output Voltage This pin is the drain of the internal Power MOSFET (low current path). 14 RESET RESET Output (active low) This is an active-low RESET output signal. This pin is referenced to VOUT. 15 SS Soft Start Input Connect an external capacitor to SS. The internal current source charges the capacitor and generates a soft-start ramp. 16 COMP Compensation Pin 17 FB Feedback Input This is the inverting input of the error amplifier. In non-isolated applications it’s connected to the secondary output through a resistor divider. 18 CS Current Sense The current sense pin CS senses a voltage that is proportional to the current through the sense resistor. 19 GATE Gate Driver Output GATE drives the gate of the external power MOSFET. GATE sources and sinks up to 1.0 A. 20 VDD VDD Output VDD mainly supplies the gate of the external power MOSFET. Connect a capacitor from VDD to VOUT. Connect to VIN in application mode. Adjusts the internal oscillator frequency by connecting a resistor between FREQ and VIN. Used to adjust the inrush current limit of the isolation switch, add a resistor between ILIM and VIN. This is the most negative power supply input. COMP is the output of the error amplifier and is available for feedback compensation. COMP is pulled-up by an internal 5.0 kΩ resistor to 5.0 V. 34670 Analog Integrated Circuit Device Data Freescale Semiconductor 3 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to VIN unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit Power Supply Voltage VPWR -0.3 to 80 V Supply Current IPWR 18 mA VOUT Pins Voltage VOUT -0.3 to (VPWR + 0.3) V UVLO Voltage VUVLO -0.3 to 10 V RCLA Voltage VRCLA -0.3 to 5.0 V ILIM Voltage VILIM -0.3 to 5.0 V FREQ Voltage VFREQ -0.3 to 5.0 V ELECTRICAL RATINGS With respect to: VOUT(2) VIN(3) VFB, VCOMP -0.3 to 5.0 -0.3 to 80 V SS Voltage VSS -0.3 to 5.0 -0.3 to 80 V VDD Voltage VDD -0.3 to 16 -0.3 to 80 V VGATE -0.3 to (VDD + 0.3) -0.3 to 80 V VCS -0.3 to 5.0 -0.3 to 80 V VRESET -0.3 to 15 -0.3 to 80 FB, COMP Voltage GATE Voltage CS Voltage RESET Voltage ESD Voltage (1) Human Body Model VESD1 ± 2000 ECL 12 Machine Model Output Clamp Energy V VESD2 ±200 mJ NotesNotes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω). ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω). 2. Measured value relative to VOUT 3. Measured value relative to VIN 34670 4 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings (continued) All voltages are with respect to VIN unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit TA -40 to 85 TJ 120 TSTG -65 to 150 °C PD 800 mW Junction to Ambient RθJA 103 20LD SOIC W/B Package (9) RθJB 47 Peak Package Reflow Temperature During Reflow (5), (6) TPPRT Note 6 °C Thermal Shutdown Temperature TSHUT 180 °C Thermal Shutdown Recovery Temperature THYST 150 °C THERMAL RATINGS Operating Temperature Ambient °C (4) Junction (8), (9) Storage Temperature Power Dissipation (TA = 25 °C) (7) Thermal Resistance °C/W NotesNotes 4. The limiting factor is junction temperature; taking into account the power dissipation, thermal resistance, and heat sinking. 5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 6. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 7. Maximum power dissipation at indicated ambient temperature in free air with no heatsink used. 8. For TA = 85°C and PD = 700 mW and RθJB = 47°C/W. 9. Measured with 4 layers 2s2p JEDEC std. PCB. 34670 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 30 V ≤ VPWR ≤ 60 V, - 40°C ≤ TA ≤ 85°C, VIN = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit IOFFSET — — 10 µA RDIFF 600 — — kΩ 0 — 4.0 Class 1: RCLASS = 475 Ω 9.0 — 12 Class 2: RCLASS = 261 Ω 17 — 20 Class 3: RCLASS = 169 Ω 26 — 30 Class 4: RCLASS = 113 Ω 36 — 44 ICLASS(LIM) — — 50 mA VRCLA 4.0 4.5 5.0 V Input Inrush Current, ILIM connected to VIN IINRUSH — — 350 mA Input Inrush Current, ILIM connected via resistor RILIM to VIN IINRUSH RILIM = 12.1 kΩ 130 180 250 RILIM = 42.2 kΩ 70 110 165 RILIM = 191 kΩ 30 65 100 VPWR — — 60 V IPWR — 4.5 7.3 mA Default Turn-On Voltage (UVLO = VIN) VUVLO(ON) — — 40 V Default Turn-Off Voltage (UVLO = VIN) VUVLO(OFF) 30 — — V UVLO Hysteresis when set internally VHYST(INT) 6.0 — — V External UVLO Programming Range VUVLO(PR) 25 — 50 V UVLO Reference Voltage VUVLO(REF) 1.96 2.0 2.04 V UVLO Hysteresis when set externally VHYST(EXT) — 15 — % IUVLO(B) — — 1.0 µA RDS(ON) — — 500 mΩ ILIM 380 — 700 mA SIGNATURE DETECTION Input Offset Current (1.4 V ≤ VPORT ≤ 9.5 V) Differential Input Resistance (1.4 V ≤ VPORT ≤ 9.5 V) CLASSIFICATION Classification Current (13.5 V ≤ VPORT ≤ 20 V) ICLASS Class 0: RCLASS = 4.42 kΩ Classification Current Limit RCLA Reference Voltage (13.5 V ≤ VPORT ≤ 20 V) mA INRUSH CURRENT LIMITATION (37 V ≤ VPORT ≤ 60 V) (RLIM) NORMAL OPERATION (VPWR, UVLO) Supply Voltage Supply Current (10) UVLO Bias Current ISOLATION SWITCH (ILIM) On-Resistance (VPORT = 48 V, IPORT = 350 mA) (11) Isolation Switch Current Limit in Normal Operation Mode Notes 10. GATE pin open, PWM controller running. 11. Measured across VIN and VOUT. 34670 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics(continued) Characteristics noted under conditions 30 V ≤ VPWR ≤ 60 V, - 40°C ≤ TA ≤ 85°C, VIN = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit VCOMP 1.3 — 4.0 V ICOMP(B) — — 1.8 mA VDDREG 8.0 9.0 10 V VDDReg +0.5 — V PWM COMPARATOR (COMP) COMP Control Voltage Range COMP Input Bias Current HIGH VOLTAGE REGULATOR Regulator Output Voltage Regulator Turn-Off Voltage (12) VREG(OFF) Regulator Current Limitation (13) IREGLIM 7.0 — 15 mA Regulator Continuous Current IREGDC — — 5.0 mA Gate Driver UVLO, Rising VGATE(R) VDD-0.5 — — V Gate Driver UVLO, Falling VGATE(F) — — 6.5 V VCS 320 400 480 mV ICS(B) — — 30 µA VREF 1.164 1.2 1.236 V OVLO Threshold, Rising VOV(R) 66 — 72 V OVLO Threshold, Falling VOV(F) 63 — 69 V VOV(HYS) — 3.0 — V SS Output Voltage VSS — 2.0 — V SS Source Current ISS(OUT) 3.25 5.0 6.75 µA SS Sink Current ISS(IN) — 2.0 2.25 mA Shutdown Threshold Voltages VSS(R) 0.48 0.6 0.72 V VSS(F) 0.24 0.3 0.40 TSHUTDOWN 150 165 180 °C THYS — 30 — °C GATE DRIVER (UVLO) CURRENT LIMIT (CS) CS Threshold Voltage CS Bias Current ERROR AMPLIFIER Reference Voltage OVERVOLTAGE SHUTDOWN OVLO Hysteresis SOFT-START (SS) THERMAL SHUTDOWN Thermal Shutdown Temperature Thermal Hysteresis Notes 12. An external voltage has to be applied. 13. Thermal limitations of the device might derate usable current range. 34670 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 30 V ≤ VPWR ≤ 60 V, - 40°C ≤ TA ≤ 85°C, VIN = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Turn-On Filter Time tFILT(ON) — 200 — µs Turn-Off Filter Time tFILT(OFF) — 200 — µs fPWM = 100 kHz m100 — 10 — fPWM = 250 kHz m250 — 25 — fPWM = 400 kHz m400 — 40 — DMAX — — 48 % Rise Time (10% - 90%), CLoad = 2.0 nF, VDDREG = 9.0 V tR — — 50 ns Fall Time (90% - 10%), CLoad = 2.0 nF, VDDREG = 9.0 V tF — — 30 ns tBLANK 40 50 60 ns fPWM 175 225 325 kHz Oscillator Frequency Adjusting Resistor Range RFREQ 121 — 499 kΩ Oscillator Frequency Range, RFREQ = 121 kΩ fRANGE 320 — 480 kHz Oscillator Frequency Range, RFREQ = 499 kΩ fRANGE 80 — 120 kHz Gain Bandwidth (14) GBW 1.0 — — MHz DC Open Loop Gain AVOL — 80 — dB VRESET,LOW — — 0.8 V tRESET — 20 — µs NORMAL OPERATION PWM COMPARATOR Slope Compensation Ramp as a Function of Switching Frequency Duty Cycle Limit (14) mV/µs GATE DRIVER CURRENT LIMIT Blanking Time (14) PWM OSCILLATOR Default Clock Frequency (FREQ connected to VIN) ERROR AMPLIFIER RESET OUTPUT RESET Output Low Voltage (IRESET, SINK = 20 mA) RESET Output Filter Time Notes 14. Guaranteed by design. Not production tested. 34670 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TYPICAL SWITCHING WAVEFORMS TYPICAL SWITCHING WAVEFORMS w/o snubber w/ snubber w/ snubber w/o snubber Figure 4. Drain Voltage of Switching MOSFET Figure 6. Secondary Voltage before Diode Figure 5. Secondary and Output Voltage Figure 7. Gate Voltage and Voltage at CS pin 34670 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES ELECTRICAL PERFORMANCE CURVES MC34670 Efficiency Plot: Vo = 5V, w/o bias winding, Coilcraft DA2142-AL 90.00 85.00 80.00 % 75.00 70.00 65.00 60.00 57V 55.00 48V 36V 50.00 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 I O [A] MC34670 Efficiency Plot: Vo = 5V, w/ bias winding, Coilcraft DA2362-AL 90.00 85.00 80.00 % 75.00 70.00 65.00 60.00 57V 48V 55.00 36V 50.00 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 I O [A] Figure 8. Efficiency Plot 34670 10 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 34670 combines a Power Interface Port for IEEE 802.3af Powered Devices (PD) and a high performance current mode switching regulator. It allows a designer to build PDs with a minimum of external components by means of integrating the required IEEE 802.3af functions and all functions necessary to build a high efficiency DC/DC converter. Thus 34670 gives the system designer a device that drastically reduces cost and board space. On the PD side the 34670 fully supports the IEEE802.3af standard and provides complete signature detection and power classification functions. It controls inrush current limiting and incorporates an adjustable undervoltage lockout. The 34670 includes thermal protection circuitry to protect the device in case of high power dissipation. The 34670 also offers an input overvoltage detection to protect the external switching MOSFET by disabling the gate driver in case of input line overvoltage. The switching regulator provides excellent line and load regulation. It drives an external power MOSFET with sense resistor. The switching frequency is adjustable between 100 kHz and 400 kHz. The output voltage feedback information can be accomplished by an optocoupler, if isolation is required. An internal logic control block manages the sequencing of signature detection, classification and proper turn on and turn off of the DC/DC converter. FUNCTIONAL PIN DESCRIPTION POSITIVE SUPPLY VOLTAGE INPUT (VPWR) RESET OUTPUT (RESET) This is the most positive power supply input. The load connects between this pin and the VOUT pin. This is an active-low RESET output signal. This pin is referenced to VOUT. CLASSIFICATION RESISTOR (RCLA) SOFT START INPUT (SS) Connect a resistor between RCLA and VIN to select the class of the PD. Connect an external capacitor to SS. The internal current source charges the capacitor and generates a soft-start ramp. UNDERVOLTAGE LOOKOUT (UVLO) Used to adjust the undervoltage lookout threshold voltage, connected to VIN to use the default threshold voltage. TEST PINS (TEST1, TEST2) Connect to VIN in application mode. FREQUENCY ADJUSTMENT (FREQ) Adjusts the internal oscillator frequency by connecting a resistor between FREQ and VIN. INRUSH CURRENT LIMIT (ILIM) COMPENSATION PIN (COMP) COMP is the output of the error amplifier and is available for feedback compensation. COMP is pulled-up by an internal 5.0 kΩ resistor to 5.0 V. FEEDBACK INPUT (FB) This is the inverting input of the error amplifier. In nonisolated applications it’s connected to the secondary output through a resistor divider. CURRENT SENSE (CS) Used to adjust the inrush current limit of the isolation switch, add a resistor between ILIM and VIN. The current sense pin CS senses a voltage that is proportional to the current through the sense resistor. NEGATIVE SUPPLY VOLTAGE (VIN) GATE DRIVER OUTPUT (GATE) This is the most negative power supply input. OUTPUT VOLTAGE (VOUT) This pin is the drain of the internal Power MOSFET (high current path and low current path). GATE drives the gate of the external power MOSFET. GATE sources and sinks up to 1.0 A. VDD OUTPUT (VDD) VDD mainly supplies the gate of the external power MOSFET. Connect a capacitor from VDD to VOUT. 34670 Analog Integrated Circuit Device Data Freescale Semiconductor 11 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES POWER DEVICES (PD) INTERFACE The PD interface of the 34670 has been designed to comply with the requirements of the IEEE standard 802.3af. The device operates in three different modes, depending on the input voltage. I PD OPERATING MODES The IEEE 802.3af standard defines three operating modes in general. These modes are summarized in Table 5. Table 5. PD Operating Modes Operating Mode Voltage at PD Input Connector Signature Resistor Detection 2.7 V - 10.1 V Classification 14.5 V - 20.5 V Normal Operation Mode 37 V - 57 V A PD shall present a valid detection signature at the PD input connector to get properly detected as a power over LAN enabled pin. Valid and non-valid detection signature regions are separated by guard bands. See Figure 9 for valid and non-valid signature regions. valid region non-valid region Signature [kΩ] 12 23.75 26.25 I1 V1 SIGNATURE RESISTOR DETECTION non-valid region I2 45 V2 V V –V 2 1 dR = -------------------I2 – I1 Figure 10. dR Measurement It can be seen in Figure 11, that a signature resistor of 25 kΩ as defined in IEEE 802.3af and two diodes in series would lead to an effective resistance out of the valid region specified in Figure 9. At low voltages the effective resistance is above the maximum allowed value of 26.25 kΩ, as illustrated in Figure 11. Therefore one has to adjust the signature resistor RSIG (R1 and R2, see UVLO Adjustment on page 13) to a value below 25 kΩ to stay within the valid region. Figure 9. Signature Resistance Guard Bands The effective resistance across the input pins is calculated by two subsequent voltage-current measurements made during the detection process by the PSE. VALID PD DETECTION SIGNATURE CHARACTERISTICS During signature detection phase the Power Sourcing Equipment (PSE) applies a voltage in the range 2.7 V 10.1 V on the PI connector and looks for the 25 kΩ signature resistor. Since the PD circuitry includes bridge rectifiers, the PD has to compensate for the voltage drop across the diodes and the diodes serial resistance. The effective signature resistance dR is obtained by the V-I-Slope measurement of the PSE (Figure 10). Figure 11. dR at Low Input Voltages 34670 12 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES CLASSIFICATION CLASSIFICATION SIGNATURE LOAD CURRENT A PD may optionally be classified by the PSE. The intent of classification is to provide a method for more efficient power allocation through the PSE. The PD classification allows the PSE to identify four different (power) classes depending on the required power that the PD will draw during normal operation. The classes and the corresponding maximum power drawn by the PD is shown in Table 6. The implementation for the classification circuitry is shown in Figure 12. +VPORT 34670 Table 6. PD Classes Vref Class Usage Maximum Power [W] 0 Default 0.44 - 12.95 1 Optional 0.44 - 3.84 2 Optional 3.84 - 6.49 3 Optional 6.49 - 12.95 4 Reserved — PD CLASSES During classification probing by the PSE, the PD applies the appropriate load current onto the line. The PSE measures the load current and can determine the classification as described in Table 7. . Table 7. PD Class vs. Classification Current Class Classification Current [mA] Min Max 0 0 4 1 9 12 2 17 20 3 26 4 36 Condition 14.5 - 20.5 Volts measured at PD input connector VPWR + - EN RCLA ICLASS VIN RCLASS -VPORT Figure 12. Classification Circuitry A constant voltage is applied at pin RCLA and depending on the resistor RCLASS, a current from +VPORT to -VPORT is flowing with the following relation: V RCLA I CLASS = -------------------R CLASS ICLASS is the classification current that is measured by the PSE. The values for the RCLASS resistor corresponding to the appropriate class are listed in Table 8. Table 8. PD Class vs. Classification Resistor RCLASS Class Classification Current [mA] RCLASS [Ω] 0 2.0 4.42k 30 1 10.5 475 44 2 18.5 261 3 28 169 4 40 113 UVLO ADJUSTMENT The 34670 has default UVLO settings that corresponds to the IEEE 802.3af standard. Nevertheless the user can adjust the UVLO by an external resistor divider as sketched in Figure 13. Since the UVLO resistor divider replaces the 34670 Analog Integrated Circuit Device Data Freescale Semiconductor 13 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES signature resistor, the total resistance of R1+R2 must equal 25 kΩ. R 1 = R SIG – R 2 V UVLO ( OFF ) = V UVLO ( ON ) ⋅ 0.85 +VPORT VPWR RCLA R1 UVLO R2 ILIM VIN -VPORT Figure 13. UVLO Adjustment by External Resistor Divider The typical turn-off voltage VUVLO(OFF) is 85% of the turn on voltage VUVLO(ON). INRUSH CURRENT LIMITATION The 34670 has been designed to interface also with legacy PoE-PSEs which do not meet the inrush current requirement of the IEEE 802.3af specification. By setting the initial inrush current limit to a low level, a PD using the 34670 minimizes the current drawn from the PSE during start-up. The maximum inrush current level can be set by connecting a resistor from ILIM to VIN as illustrated in Figure 15. +VPORT VPWR To use the default settings for UVLO, the pin UVLO must be connected to VIN. In this case, a valid signature resistor has to be placed between -VPORT and +VPORT. This configuration can be seen in Figure 14. RCLASS RCLA RSIG 25kΩ +VPORT RILIM UVLO ILIM VPWR VIN RCLA -VPORT RSIG 25kΩ UVLO ILIM VIN Figure 15. Inrush Current Limitation by External Resistor RILIM The following table shows the selectable current limits and the corresponding resistor value that has to be connected between pins ILIM and VIN: -VPORT Figure 14. Default UVLO Settings To calculate the values for R1 and R2 the following equations should be used: R 1 + R 2 = R SIG V UVLO ( REF ) R 2 = ---------------------------------- ⋅ R SIG V UVLO ( ON ) where VUVLO(ON) is the desired turn-on voltage threshold and VUVLO(ref) the UVLO reference voltage. Table 9. Inrush Current Limit vs. RILIM Inrush Current Limit [mA] RILIM Value [kΩ] 180 12.1 110 42.2 65 191 After powering up, the 34670 switches to the high level current limit, thereby allowing the PD to consume up to 12.95 W if a 802.3af PSE is present. PULSE WITH MODULATOR CONTROLLER CURRENT-MODE CONTROL OPERATION The 34670 offers current-mode control operation with leading-edge blanking. The current-limit comparator monitors the CS pin at all times and provides cycle-by-cycle current limit. The CS signal contains a leading-edge spike that is the result of the MOSFET gate charge current, capacitive and diode reverse recovery current of the power circuit. The leading-edge blanking of the CS signal prevents the PWM comparator from premature termination of the on cycle. The 34670 limits the duty cycle to 50%. This is advantageous for applications which are not allowed to exceed an on-time of 50 % of the switching period TS. Beside the duty-cycle limit, slope compensation is provided to stabilize the inner current loop and avoid oscillations for 34670 14 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES converters running in continuos conduction mode (CCM). The value of the slope compensation depends on the switching frequency. See Table 10. T1 NP Table 10. Slope Compensation Values Switching Frequency [kHz] Slope Compensation [mV/µs] 100 10 250 25 400 50 NS RV ISOLATED OPTOCOUPLER FEEDBACK Isolated voltage feedback can be accomplished by using an optocoupler and a shunt regulator (see Figure 19). The output voltage accuracy is a function of the accuracy of the shunt regulator and feedback resistor divider tolerance, therefore the feedback resistors should have an appropriate accuracy. Since the error amplifier function is implemented on the secondary side by the optocoupler and a 3-pin adjustable shunt regulator, the internal error amplifier of the 34670 is not used. The FB pin is connected to VOUT, thus disabling the internal open-drain error amplifier. The bias voltage for the optocoupler is accomplished through the internal 5.0 kΩ pull-up resistor between COMP and an internal 5.0 V reference. When a TL431 or TLV431 shunt regulator is used for output voltage regulation, the output voltage is set by the ratio of resistors R1 and R2, see Figure 16 for details. The output voltage is given by the following equation: R 1⎞ ⎛ V O = V REF ⋅ ⎜ 1 + -------⎟ R 2⎠ ⎝ where VREF = 1.24 V for the TLV431 (VREF = 2.5 V for the TL431). R1 R2 TLV431 Figure 16. Isolated Optocoupler Feedback ISOLATED PRIMARY CONTROL FEEDBACK Another option to accomplish isolated feedback is the use of a tertiary winding (see Figure 21). The advantage of this solution without optocoupler and shunt regulator is clearly the cost effectiveness. Nevertheless the line and load regulation is worse than with optocoupler feedback. When isolated primary feedback is used, the loop compensation components are connected between pins COMP and FB. INTERNAL REGULATORS The internal high voltage regulator of the 34670 regulates from the input voltage across VPWR and VIN down to the VDD voltage. During start-up the high voltage regulator provides the necessary voltage for the internal gate driver to commence switching. If the external MOSFET gate drive pulls less than 3.0 mA under all circumstances, an auxiliary transformer winding that usually provides the bias voltage for the chip and the gate driver is not required. In cases where the external MOSFET gate drive pulls more than 5.0 mA, an auxiliary winding is needed to reduce the power dissipation in the internal high voltage LDO. See Figure 18 for an application drawing. It is recommended to add a 0.1 µF ceramic capacitor in parallel with the existing load capacitor. This reduces noise at the VDD pin caused by the auxiliary winding. The high voltage regulator is disabled when the VDD pin is forced by an external voltage above the VDD regulation point. 34670 Analog Integrated Circuit Device Data Freescale Semiconductor 15 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES VDD This reduces power dissipation in the device and improves overall efficiency. 12 VREG(OFF) VGATE(R) 10 CURRENT-SENSE COMPARATOR 8 VGATE(F) When the overvoltage protection is triggered (VPWR > VOV(R)), the gate driver is immediately disabled. At the same time, the slow discharge of CSS is initiated. While the soft-start capacitor is discharging, the gate driver remains disabled. Once VSS = 0.3 V and the overvoltage (VPWR < VOV(F)) condition disappears, operation resumes through a regular soft-start. 6 4 2 t GATE enable HVReg enable Figure 17. VDD and MOSFET Driver Output Behavior A load capacitor connected to VDD ensures a proper filtering of the VDD voltage. The minimum capacitance value for this load capacitor should be at least 10 µF. An electrolytic type capacitor is sufficient. Please refer to application note A/N3279 for further information about the size of the capacitor. If VDD falls below the UVLO threshold, the voltage regulator is disabled and the MOSFET driver output (GATE) is held low. PWM CONTROLLER UVLO, SOFT-START, AND SHUTDOWN FUNCTION The soft-start function provided by the 34670 allows the output voltage to ramp up in a controlled way, thus eliminating output voltage overshoot. While the PWM controller is in undervoltage lockout, the capacitor CSS connected to the SS pin is fully discharged. After coming out of undervoltage lockout, an internal current source starts charging the capacitor CSS to initiate soft-start. When VSS has reached 0.6 V, the gate driver is enabled and PWM operation begins. The duty cycle during soft-start is primarily controlled by the internal sawtooth voltage and the voltage at the SS pin. If the voltage at the SS pin is above 2.6 V, the regular PWM control through pins CS, COMP, and FB takes over and soft-start is finished. The following equation calculates the total soft-start time: t SS [ ms ] = 0.4 ⋅ C SS [ nF ] OVERVOLTAGE SHUTDOWN The 34670 includes an overvoltage protection (OVP) feature that turns off the external MOSFET when the input voltage exceeds the overvoltage threshold. The current-sense (CS) comparators and its associated circuitry limits the peak current through the MOSFET. Current is sensed at CS pin as a voltage across the sense resistor RCS between the source of the MOSFET and VOUT. The CS input has two voltage trip levels, a 600mV high limit and a 400 mV low limit. When the voltage on CS produced by a current through the current sense resistor exceeds the high limit threshold, the current ON-cycle is immediately terminated and the GATE output is pulled low. If the low limit threshold is exceeded for longer than 50 ns (typical blanking time), the current ON-cycle is also terminated. The blanking time ensures a false termination of the switching cycle caused by the leading-edge spike on the sense waveform. The current-sense resistor RCS is selected according to the following equation: 400mV R CS = ---------------------------------------I LIM ( primary ) where ILIM(primary) is the maximum peak primary-side current. In case of an overcurrent in the external MOSFET the current switching cycle is terminated and GATE is pulled low. The soft-start capacitor CSS is discharged and after removal of the faulty condition the PWM is re-started through a regular soft start. PWM OSCILLATOR A default 250 kHz oscillator sets the switching frequency of the PWM controller. The frequency of the oscillator can be adjusted between 100 kHz and 400 kHz by an optional external resistor RFREQ connected from the FREQ pin of the integrated circuit to VIN. The appropriate switching frequency fPWM can be calculated as shown below: 47920 f PWM [ kHz ] = ------------------------------------ + 4 R FREQ [ kΩ ] where fPWM is the PWM switching frequency and RFREQ is the frequency adjusting resistor. To use the default frequency of 250 kHz the FREQ pin can be connected to VIN or can be left open. RESET OUTPUT The RESET pin is an open drain output. The reset control circuit supervises the FB voltage and recognizes if the output 34670 16 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES voltage is out of regulation. In this case the RESET pin is pulled low. The RESET output can only be used in non-isolated applications. There is a 20 µs delay filter preventing erroneous RESET output pulses. During soft-start, RESET is held low. RESET is released when the PWM controller is in regulation. N-CHANNEL MOSFET GATE DRIVER GATE drives an N-channel MOSFET. GATE sources and sinks large transient currents up to 1.0 A to charge and discharge the MOSFET gate. The GATE output is supplied by the internal generated VDD voltage, which is internally set to approximately 9.0 V. For Power-over-Ethernet applications, the used MOSFET must be able to withstand a DC level of ~60 V plus the reflected voltage at the primary side of the transformer. This requires a MOSFET rated at 150 V or 200 V. 34670 Analog Integrated Circuit Device Data Freescale Semiconductor 17 TYPICAL APPLICATIONS TYPICAL APPLICATIONS Please refer to application note AN3279 for further information of PD design and layout recommendations. T1 NAUX +VPORT VOUT = [email protected] 3 NP 34670 RX NS VPWR 6 RESET 1 RCLA VDD TX 2 R1 CIN RCLASS UVLO R2 4 GATE 5 CDD 0.1 F RV CPORT CS ILIM VIN M1 RCS SS FREQ COMP FB VOUT -VPORT CSS 7 8 Figure 18. Isolated Flyback Converter with Bias Winding +VPORT T1 VOUT = [email protected] + 3 RX NP 34670 RX D1 VPWR 6 RX RESET + 1 TX RCLA VPORT TX NS VDD 2 TX R1 CIN RCLASS UVLO R2 4 5 GATE CDD CPORT RV CS ILIM VIN M1 RCS SS FREQ COMP FB VOUT SPARE+ -VPORT 7 SPARE- CSS 8 Figure 19. Isolated Flyback Converter without Bias Winding 34670 18 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS T1 +VPORT NR 3 NP 34670 RX NS VPWR 6 RESET 1 RCLA VDD TX 2 R1 CIN UVLO R2 4 M1 GATE RCLASS CDD RV CPORT CS ILIM RCS Rv1 5 VIN SS FREQ COMP FB VOUT Rv2 -VPORT CSS 7 8 Figure 20. Isolated Forward Converter T1 CAUX NAUX +VPORT VOUT = [email protected] 3 NP 34670 RX NS VPWR 6 RESET 1 RCLA VDD TX 2 R1 CIN RCLASS UVLO R2 4 5 GATE CDD CPORT CS ILIM VIN M1 RCS SS FREQ COMP -VPORT CSS FB VOUT C2 R2 7 C1 8 Figure 21. Isolated Flyback with Primary Control 34670 Analog Integrated Circuit Device Data Freescale Semiconductor 19 TYPICAL APPLICATIONS +VPORT T1 3 NP 34670 RX VOUT = [email protected] NS D1 CO VPWR 6 RESET 1 RCLA VDD TX 2 R3 CIN RCLASS UVLO R4 4 5 VIN CDD CPORT CS ILIM RCS SS FREQ COMP -VPORT CSS FB VOUT C2 R1 R2 7 8 M1 GATE Rb C1 Figure 22. Non-Isolated Flyback Converter 34670 20 Analog Integrated Circuit Device Data Freescale Semiconductor REFERENCE DOCUMENTS REFERENCE DOCUMENTS Table 11. Reference Documents Title IEEE Std 802.3af™-2003 MC34670 Usage and Configuration LIterature Order Number Publication Date IEEE Std 802.3af™-2003 18 June 2003 AN3279 34670 Analog Integrated Circuit Device Data Freescale Semiconductor 21 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EG SUFFIX (PB-FREE) 20-PIN PLASTIC PACKAGE 98ASB42343B ISSUE J 34670 22 Analog Integrated Circuit Device Data Freescale Semiconductor REVISION HISTORY REVISION HISTORY Revision Date Description of Changes 1.0 8/2006 • Initial release 2.0 9/2006 3.0 12/2006 • Change to UVLO Hysteresis when set internally on page 6, Regulator Current Limitation (13) on page 7, OVLO Threshold, Rising on page 7, OVLO Threshold, Falling on page 7, Shutdown Threshold Voltages on page 7, and Default Clock Frequency (FREQ connected to VIN) on page 8 • Changed Data Sheet category to “Advanced Information*” • Typ and Max change to RCLA Reference Voltage (13.5 V ≤ VPORT ≤ 20 V) on page 6 • Deleted Oscillator Frequency Adjusting Resistor Range in Static Electrical Characteristics • Split Oscillator Frequent Range into two parameters, Oscillator Frequency Range, RFREQ = 121 kΩ on page 8 and Oscillator Frequency Range, RFREQ = 499 kΩ on page 8 • Added note to Duty Cycle Limit (14) on page 8, Blanking Time (14) on page 8, and Gain Bandwidth (14) on page 8 • Changed nomenclature for Peak Package Reflow Temperature During Reflow (5), (6) on page 5 • Changed name and value for Thermal Shutdown Recovery Temperature on page 5 34670 Analog Integrated Circuit Device Data Freescale Semiconductor 23 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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