AD AD7399BR

a
FEATURES
AD7398—12-Bit Resolution
AD7399—10-Bit Resolution
Programmable Power Shutdown
Single (3 V to 5 V) or Dual (ⴞ5 V) Supply Operation
3-Wire Serial SPI-Compatible Interface
Internal Power ON Reset
Double Buffered Registers for Simultaneous
Multichannel DAC Update
Four Separate Rail-to-Rail Reference Inputs
Thin Profile TSSOP-16 Package Available
Low Tempco 1.5 ppm/ⴗC
Quad, Serial-Input
12-Bit/10-Bit DACs
AD7398/AD7399
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFB
VREFA
DAC A
REGISTER
DAC A
VOUTA
INPUT
REG B
DAC B
REGISTER
DAC B
VOUTB
INPUT
REG C
DAC C
REGISTER
DAC C
VOUTC
INPUT
REG D
DAC D
REGISTER
DAC D
VOUTD
INPUT
REG A
SERIAL
REGISTER
CS
SDI
APPLICATIONS
Automotive Output Voltage Span
Portable Communications
Digitally Controlled Calibration
PC Peripherals
CLK
12/10
GENERAL DESCRIPTION
POWER
ON RESET
The AD7398/AD7399 family of quad, 12-bit/10-bit, voltageoutput digital-to-analog converters is designed to operate from a
single 3 V to 5 V or a dual ±5 V supply. Built with Analog’s robust
CBCMOS process, this monolithic DAC offers the user low
cost, and ease-of-use in single or dual-supply systems.
VSS
LDAC VREFC VREFD
RS
GND
The applied external reference VREF determines the full-scale
output voltage. Valid VREF values include VSS < VREF < VDD that
result in a wide selection of full-scale outputs. For multiplying
applications ac inputs can be as large as ± 5 VP.
Both parts are offered in the same pinout to enable users to
select the appropriate resolution for their application without
redesigning the layout. For 8-bit resolution applications see the
pin compatible AD7304 product.
The AD7398/AD7399 is specified over the extended industrial
(–40°C to +125°C) temperature range. Parts are available in
wide body SOIC-16 and ultracompact thin 1.1 mm TSSOP16 packages.
0.50
VDD = +5V
VSS = –5V
VREF = +2.5V
TA = 25ⴗC
0.40
0.30
0.20
DNL – LSB
A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI and microcontroller-compatible inputs using serialdata-in (SDI), clock (CLK), and a chip-select (CS). A common
level-sensitive load-DAC strobe (LDAC) input allows simultaneous update of all DAC outputs from previously loaded Input
Registers. Additionally, an internal power ON reset forces the
output voltage to zero at system turn ON. An external asynchronous reset (RS) also forces all registers to the zero code state. A
programmable power-shutdown feature reduces power dissipation on unused DACs.
0.10
0
–0.10
–0.20
–0.30
–0.40
–0.50
0
512
1024
1536
2560
2048
CODE – Decimal
3072
3584
4096
Figure 1. AD7398 DNL vs. Code (TA = 25 °C)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD7398/AD7399–SPECIFICATIONS
(@ V = 5 V, V
DD
SS
= 0 V; or VDD = +5 V, VSS = –5 V, VREF = +2.5 V, –40ⴗC < TA
AD7398 12-BIT VOLTAGE OUTPUT DAC < +125ⴗC, unless otherwise noted.)
3 V–5 V ⴞ 10%
ⴞ5 V ⴞ 10%
Unit
12
± 1.5
±1
7
± 2.5
1.5
12
± 1.5
±1
± 2.5
± 2.5
1.5
Bits
LSB max
LSB max
mV max
mV max
ppm/°C typ
Data = 555H, Worst-Case
0/VDD
35
5
VSS/VDD
35
5
V min/max
kΩ typ6
pF typ
IOUT
CL
Data = 800H, ∆VOUT = 4 LSB
No Oscillation
±5
200
±5
400
mA typ
pF max
VIL
VDD = 3 V
VDD = 5 V
CLK Only
0.8
4.0
2.4
1
10
V max
V max
V min
V min
µA max
pF max
Parameter
Symbol
STATIC PERFORMANCE
Resolution1
Relative Accuracy2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Tempco3
N
INL
DNL
VZSE
VFSE
TCVFS
REFERENCE INPUT
VREFIN Range4
Input Resistance5
Input Capacitance3
VREF
RREF
CREF
ANALOG OUTPUT
Output Current
Capacitive Load3
LOGIC INPUTS
Logic Input Low Voltage
Condition
Monotonic
Data = 000H
Data = FFFH
Logic Input High Voltage
VIH
Input Leakage Current
Input Capacitance3
IIL
CIL
0.5
0.8
80% VDD
2.1–2.4
1
10
INTERFACE TIMING 3, 7
Clock Frequency
Clock Width High
Clock Width Low
CS to Clock Set Up
Clock to CS Hold
Load DAC Pulsewidth
Data Setup
Data Hold
Load Setup to CS
Load Hold to CS
fCLK
tCH
tCL
tCSS
tCSH
tLDAC
tDS
tDH
tLDS
tLDH
11
45
45
10
20
45
15
10
0
20
16.6
30
30
5
15
30
10
5
0
15
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
AC CHARACTERISTICS
Output Slew Rate
Settling Time8
Shutdown Recovery
DAC Glitch
Digital Feedthrough
Feedthrough
SR
tS
tSDR
Q
QDF
VOUT/VREF
Data = 000H to FFFH to 000H
To ± 0.1% of Full Scale
2
6
6
150
15
–63
2
6
6
150
15
–63
V/µs typ
µs typ
µs typ
nVs typ
nVs typ
dB typ
SUPPLY CHARACTERISTICS
Shutdown Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
IDD_SD
IDD
ISS
PDISS
PSS
No Load
VIL = 0 V, No Load
VIL = 0 V, No Load
VIL = 0 V, No Load
∆VDD = ± 5%
30/60
1.5/2.5
1.5/2.5
5
0.006
30/60
1.6/2.7
1.6/2.7
16
0.006
µA typ/max
mA typ/max
mA typ/max
mW typ
%/% max
Code 7FFH to 800H to 7FFH
VREF = 1.5 VDC + 1 V p-p,
Data = 000H, f = 100 kHz
NOTES
1
One LSB = VREF/4096 V for the 12-bit AD7398.
2
The first eight codes (000 H, 007H) are excluded from the linearity error measurement in single supply operation.
3
These parameters are guaranteed by design and not subject to production testing.
4
When VREF is connected to either the V DD or the VSS power supply the corresponding V OUT voltage will program between ground and the supply voltage minus the
offset voltage of the output buffer, which is the same as the V ZSE error specification. See additional discussion in the Operation section of the data sheet.
5
Input resistance is code-dependent.
6
Typicals represent average readings measured at 25°C.
7
All input control signals are specified with t R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
8
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
–2–
REV. 0
AD7398/AD7399
(@ VDD = 5 V, VSS = 0 V; or VDD = +5 V, VSS = –5 V, VREF = +2.5 V, –40ⴗC < TA
AD7399 10-BIT VOLTAGE OUTPUT DAC < +125ⴗC, unless otherwise noted.)
Parameter
Symbol
STATIC PERFORMANCE
Resolution1
Relative Accuracy2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Tempco3
N
INL
DNL
VZSE
VFSE
TCVFS
REFERENCE INPUT
VREFIN Range4
Input Resistance5
Input Capacitance3
VREF
RREF
CREF
Data = 155H, Worst-Case
ANALOG OUTPUT
Output Current
Capacitive Load3
IOUT
CL
Data = 200H, ∆VOUT = 1 LSB
No Oscillation
LOGIC INPUTS
Logic Input Low Voltage
VIL
VDD = 3 V
VDD = 5 V
CLK Only
Condition
Monotonic
Data = 000H
Data = 3FFH
3 V–5 V ⴞ 10%
ⴞ5 V ⴞ 10%
Unit
10
±1
±1
7
± 15
1.5
10
±1
±1
±4
± 15
1.5
Bits
LSB max
LSB max
mV max
mV max
ppm/°C typ
0/VDD
40
5
VSS/VDD
40
5
V min/max
kΩ typ6
pF typ
200
±5
400
mA typ
pF max
0.8
4.0
2.4
1
10
V max
V max
V min
V min
µA max
pF max
Logic Input High Voltage
VIH
Input Leakage Current
Input Capacitance3
IIL
CIL
0.5
0.8
80% VDD
2.1–2.4
1
10
INTERFACE TIMING 3, 7
Clock Frequency
Clock Width High
Clock Width Low
CS to Clock Set Up
Clock to CS Hold
Load DAC Pulsewidth
Data Setup
Data Hold
Load Setup to CS
Load Hold to CS
fCLK
tCH
tCL
tCSS
tCSH
tLDAC
tDS
tDH
tLDS
tLDH
11
45
45
10
20
45
15
10
0
20
16.6
30
30
5
15
30
10
5
0
15
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
AC CHARACTERISTICS
Output Slew Rate
Settling Time8
Shutdown Recovery
DAC Glitch
Digital Feedthrough
Feedthrough
SR
tS
tSDR
Q
QDF
VOUT/VREF
Data = 000H to 3FFH to 000H
To ± 0.1% of Full Scale
2
6
6
150
15
–63
2
6
6
150
15
–63
V/µs typ
µs typ
µs typ
nVs typ
nVs typ
dB typ
SUPPLY CHARACTERISTICS
Shutdown Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
IDD_SD
IDD
ISS
PDISS
PSS
No Load
VIL = 0 V, No Load
VIL = 0 V, No Load
VIL = 0 V, No Load
∆VDD = ± 5%
30/60
1.5/2.5
1.5/2.5
5
0.006
30/60
1.6/2.7
1.6/2.7
16
0.006
µA typ/max
mA typ/max
mA typ/max
mW typ
%/% max
Code 1FFH to 200H to 1FFH
VREF = 1.5 VDC + 1 V p-p,
Data = 000H, f = 100 kHz
NOTES
1
One LSB = VREF/1024 V for the 10-bit AD7399.
2
The first two codes (000 H, 001H) are excluded from the linearity error measurement in single supply operation.
3
These parameters are guaranteed by design and not subject to production testing.
4
When VREF is connected to either the V DD or the VSS power supply the corresponding V OUT voltage will program between ground and the supply voltage minus the
offset voltage of the output buffer, which is the same as the V ZSE error specification. See additional discussion in the Operation section of the data sheet.
5
Input resistance is code-dependent.
6
Typicals represent average readings measured at 25°C.
7
All input control signals are specified with t R = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
8
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
REV. 0
–3–
AD7398/AD7399
ABSOLUTE MAXIMUM RATINGS*
Operating Temperature Range . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature
R-16 (Vapor Phase, 60 secs) . . . . . . . . . . . . . . . . . . 215°C
RU-16 (Infrared, 15 secs) . . . . . . . . . . . . . . . . . . . . 224°C
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V
VOUT to GND . . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA
Thermal Resistance θJA
16-Lead SOIC Package (R-16) . . . . . . . . . . . . . . 158°C/W
16-Lead Thin Shrink Surface Mount (RU-16) . . . 180°C/W
Maximum Junction Temperature (TJ Max) . . . . . . . . 150°C
Package Power Dissipation . . . . . . . . . . . . . (TJ Max–TA)/θJA
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Resolution
(Bits)
Temperature
Range
Package
Description
Package
Option
Container
Quantity
AD7398BR
AD7398BR-REEL7
AD7398BRU-REEL7
AD7399BR
AD7399BR-REEL7
AD7399BRU-REEL7
12
12
12
10
10
10
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
SOL-16
SOL-16
TSSOP-16
SOL-16
SOL-16
TSSOP-16
R-16
R-16
RU-16
R-16
R-16
RU-16
48
1,000
1,000
48
1,000
1,000
The AD7398 contains 3254 transistors. The die size measures 108 mil × 144 millimeters.
SDI
SA
SD
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
IN
REG
LD
CLK
tDS
tDH
tCH
tCL
tCSH
tCSS
CS
tLDH
LDAC
tLDS
tLDAC
Figure 2. AD7398 Timing Diagram (AD7399 with SDI = 14 Bits Only)
CLK
tCH
LDAC
1/fCLK
tCL
tLDH
tLDS
tLDS
tLDAC
CS
tCSH
tCSS
tCSS
Figure 3. Continuous Clock Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7398/AD7399 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD7398/AD7399
PIN CONFIGURATION
VOUTB 1
16 VOUTC
15 VOUTD
VOUTA 2
VSS 3
AD7398/
AD7399
14 VDD
13 VREFC
TOP VIEW
VREFB 5 (Not to Scale) 12 VREFD
VREFA 4
GND 6
11 SDI
LDAC 7
10 CLK
RS 8
9 CS
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
2
3
4
VOUTB
VOUTA
VSS
VREFA
5
VREFB
6
7
GND
LDAC
8
9
RS
CS
10
11
12
CLK
SDI
VREFD
13
VREFC
14
15
16
VDD
VOUTD
VOUTC
DAC B Voltage Output.
DAC A Voltage Output.
Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can
be tied to VDD or VSS pin.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can
be tied to VDD or VSS pin.
Ground Pin.
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all Input Register data to
DAC registers. Asynchronous active low input. See Control Logic Truth Table for operation.
Resets Input and DAC Registers to All Zero Codes. Shift Register contents unchanged.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers Serial Register Data to the Input Register when CS returns High. Does not effect LDAC operation.
Schmitt Triggered Clock Input, Positive Edge Clocks Data into Shift Register.
Serial Data Input. Input data loads directly into the shift register.
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can
be tied to VDD or VSS pin.
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can
be tied to VDD or VSS pin.
Positive Power Supply Input. Specified range of operation 3 V to 5 V ± 10%.
DAC D Voltage Output.
DAC C Voltage Output.
REV. 0
–5–
AD7398/AD7399
Table I. Control Logic Truth Table
CS
CLK
LDAC
Serial Shift Register Function
Input Register Function
DAC Register
H
L
L
L
↑+
H
H
X
L
↑+
H
L/H
X
X
H
H
H
H
H
L
↑+
No Effect
No Effect
Shift-Register-Data Advanced One Bit
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
Latched
Latched
Updated with SR Contents
Latched
Latched
No Effect
No Effect
Latched
Latched
Latched
Transparent
Latched
NOTES
1. ↑+ Positive logic transition; ↓– Negative logic transition; X Don’t Care; SR shift register.
2. At power ON, both the Input Register and the DAC Register are loaded with all zeros.
3. During Power Shutdown, reprogramming of any internal registers can take place, but the output amplifiers will not produce the new values until the part is taken
out of Shutdown mode.
4. LDAC input is a level-sensitive input that controls the four DAC registers.
Table II. AD7398 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
Bit Position B15
AD7398
SA
B14
SD
B13
A1
B12
A0
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
LSB
B0
D0
NOTE
Bit positions B14 and B15 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to
Logic 1, the address decoded by Bits B12 and B13 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state.
Table III. AD7399 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
Bit Position B13
AD7399
SA
B12
SD
B11
A1
B10
A0
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
LSB
B0
D0
NOTE
Bit positions B12 and B13 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to
Logic 1, the address decoded by Bits B10 and B11 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state.
Table IV. AD7398/AD7399 Address Decode Control
SA
SD
A1
A0
DAC Channel Affected
1
0
0
0
0
0
0
0
0
X
1
1
1
1
0
0
0
0
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
All DACs Shutdown
DAC A Shutdown
DAC B Shutdown
DAC C Shutdown
DAC D Shutdown
DAC A Input Register Decoded
DAC B Input Register Decoded
DAC C Input Register Decoded
DAC D Input Register Decoded
–6–
REV. 0
AD7398/AD7399
TERMINOLOGY
Relative Accuracy, INL
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL versus code plot can be seen in TPC 1.
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by 1 LSB
at the major carry transition (midscale transition). A plot of the
glitch impulse is shown in TPC 10.
Digital Feedthrough, Q DF
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. TPC 3 illustrates a typical DNL
versus code plot.
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC, but
is measured when the DAC output is not updated. CS is held
high, while the CLK and SDI signals are toggled. It is specified in nV-s and is measured with a full-scale code change on
the data bus, i.e., from all 0s to all 1s and vice versa. A typical plot of digital feedthrough is shown in TPC 11.
Zero-Scale Error, V ZSE
Power Supply Sensitivity, PSS
Differential Nonlinearity, DNL
Zero-scale error is a measure of the output voltage error from
zero voltage when zero code is loaded to the DAC register.
Full-scale error is a measure of the output voltage error from fullscale voltage when full-scale code is loaded to the DAC register.
This specification indicates how the output of the DAC is
affected by changes in the power supply voltage. Power supply
sensitivity is quoted in terms of % change in output per %
change in VDD for full-scale output of the DAC. VDD is varied
by ± 10%.
Full-Scale Temperature Coefficient, TC VFS
Reference Feedthrough, V OUT/VREF
This is a measure of the change in full-scale error with a change
in temperature. It is expressed in ppm/°C or mV/°C.
This is a measure of the feedthrough from the VREF input to
the DAC output when the DAC is loaded with all 0s. A 100 kHz,
1 V p-p is applied to VREF. Reference feedthrough is expressed
in dB or mV p-p.
Full-Scale Error, VFSE
DAC Glitch Impulse, Q
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
REV. 0
–7–
AD7398/AD7399–Typical Performance Characteristics
0.50
1.50
AD7398
VDD = +5V
VSS = –5V
VREF = +2.5V
TA = 25ⴗC
1.25
1.00
0.30
0.20
DNL – LSB
INL – LSB
0.75
0.50
0.25
0
–0.30
–0.75
–0.40
–1.00
–0.50
512
1024
2560
1536
2048
CODE – Decimal
3072
3584
4096
DNL – LSB
INL – LSB
TA = 25ⴗC
VDD = +5V
VSS = –5V
VREF = +2.5V
0
0
128
256
384
512
640
CODE – Decimal
768
896
0
DNL – LSB
DAC–C
TA = 25ⴗC
VDD = +5V
VSS = –5V
VREF = +2.5V
–0.25
0
128
256
384
512
640
CODE – Decimal
768
896
2560
1536
2048
CODE – Decimal
3072
3584
4096
0
0
DNL – LSB
DAC–B
0
–0.25
0
128
256
384
512
640
CODE – Decimal
768
896
0.50
DNL – LSB
0
TA = 25ⴗC, VDD = +5V
VSS = –5V, VREF = +2.5V
–0.25
0
128
256
384
512
640
CODE – Decimal
768
896
0
768
896
1024
DAC–C
128
256
384
512
640
CODE – Decimal
768
TA = 25ⴗC, VDD = +5V
VSS = –5V, VREF = +2.5V
0.25
896
1024
DAC–B
0
–0.25
0
128
256
384
512
640
CODE – Decimal
768
TA = 25ⴗC, VDD = +5V
VSS = –5V, VREF = +2.5V
0.25
896
1024
DAC–A
0
–0.25
–0.50
1024
384
512
640
CODE – Decimal
0
0.50
DAC–A
0.25
256
–0.25
–0.50
1024
128
0.50
TA = 25ⴗC, VDD = +5V
0.25 VSS = –5V, VREF = +2.5V
0.50
TA = 25ⴗC, VDD = +5V
VSS = –5V, VREF = +2.5V
DAC–D
–0.25
–0.50
1024
0.50
0.25
–0.50
1024
TA = 25ⴗC, VDD = +5V
VSS = –5V, VREF = +2.5V
0.25
–0.50
1024
0.50
0.25
–0.50
512
0.50
–0.25
–0.50
0
TPC 3. AD7398 DNL vs. Code (TA = 25 °C)
DAC–D
0.25
–0.50
INL – LSB
–0.10
–0.20
0.50
INL – LSB
0
–0.25
TPC 1. AD7398 INL vs. Code (TA = 25 °C)
INL – LSB
0.10
–0.50
0
AD7398
VDD = +5V
VSS = –5V
VREF = +2.5V
TA = 25ⴗC
0.40
0
128
256
384
512
640
768
896
1024
CODE – Decimal
TPC 4. AD7399 DNL vs. Code (TA = 25 °C)
TPC 2. AD7399 INL vs. Code (TA = 25 °C)
–8–
REV. 0
AD7398/AD7399
10.0
1.00
AD7398
TA = 25ⴗC
VDD = +5V
VSS = –5V
0.75
DNL
0.25
⌬VOUT – mV
INL, DNL, FSE – LSB
0.50
8.0
INL
0
FSE
–0.25
6.0
VDD = +3V, VSS = 0V
4.0
VDD = +5V, VSS = –5V
2.0
0
VDD = +5V, VSS = 0V
–2.0
–4.0
SOURCING CURRENT FROM VOUT
–0.50
VDD = +5V, VSS = –5V
VDD = +5V, VSS = 0V
VDD = +3V, VSS = 0V
–6.0
–0.75
–1.00
–5
–8.0
–4
–3
–2
–1
0
1
2
REFERENCE VOLTAGE – Volts
3
4
–10.0
–20
5
–15
–10
–5
0
5
10
15
SOURCE OR SINK CURRENT FROM VOUT – mA
20
TPC 8. ∆VOUT vs. Load Current
TPC 5. AD7398 INL, DNL, FSE vs. Reference Voltage
25
100.00
AD7398
SAMPLE SIZE = 125
–40ⴗC TO +125ⴗC
AD7398
TA = 25ⴗC
VDD = +5V
VSS = –5V
VREF = +2.5V
90.00
80.00
70.00
20
60.00
COUNTS
REFERENCE INPUT CURRENT – ␮A
AD7398/AD7399
TA = 25ⴗC
SINKING CURRENT INTO VOUT
50.00
40.00
15
10
30.00
5
20.00
10.00
0
0
512
1024
1536
2048
2560
CODE – Decimal
3072
3584
0
0.4
4096
TPC 6. AD7398 Reference Input Current vs. Code
0.6
0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
FULL SCALE ERROR TEMPCO – ppm/ⴗC
2.4
2.6
TPC 9. AD7398 Full-Scale Error Tempco
REFERENCE INPUT RESISTANCE – k⍀
1000
AD7398
VDD = +5V
VSS = –5V
TA = 25ⴗC
100
90
100
CS (5V/DIV)
VOUT (0.2V/DIV)
10
0%
TIME – 2␮s/DIV
10
0
512
1024
1536
2048
2560
CODE – Decimal
3072
3584
4096
TPC 7. AD7398 Reference Input Resistance vs. Code
REV. 0
TPC 10. AD7398 Midscale Glitch
–9–
AD7398/AD7399
FFFH
800H
400H
200H
100H
080H
040H
020H
010H
008H
004H
002H
001H
90
VOUT (50mV/DIV)
–12
–24
–36
–48
–60
–72
–84
CLOCK (5V/DIV)
10
0%
VDD = +5V
VSS = –5V
VREF = 100mV rms
TA = 25ⴗC
000H
TIME – 100ns/DIV
1k
100
100k
–96
–108
1M
TPC 14. AD7398 Multiplying Gain vs. Frequency
TPC 11. AD7398 Digital Feedthrough
5
VDD = 5V, VSS = –5V, VREF = 5V
4
SUPPLY CURRENT – mA
VOUT (2V/DIV)
100
90
10k
FREQUENCY – Hz
ATTENUATION – dB
100
0
10
0%
CS (5V/DIV)
3
TA = 25ⴗC
1. VDD = +5V, VSS = –5V, CODE = 000H, FFFH
2. VDD = +5V, VSS = –5V, CODE = 555H
3. VDD = +5V, VSS = 0V, CODE = 000H, FFFH
4. VDD = +5V, VSS = 0V, CODE = 555H
5. VDD = +3V, VSS = 0V, CODE = 000H, FFFH
6. VDD = +3V, VSS = 0V, CODE = 555H
2
4
1
6
2
3
5
1
TIME – 5␮s/DIV
0
1.E+03
POWER SUPPLY CURRENT – mA
VOUT (2V/DIV)
CS (5V/DIV)
10
1.E+07
1.E+08
2.0
VDD = 5V, VSS = –5V, VREF = 5V
90
1.E+06
1.E+05
CLOCK FREQUENCY – Hz
TPC 15. AD7398 Supply Current vs. Clock Frequency
TPC 12. AD7398 Large Signal Settling Time
100
1.E+04
0%
AD7398
TA = 25ⴗC
VREF = 2.5V
ⴞ5V
DUAL SUPPLIES
1.75
ⴞ3V
SINGLE SUPPLY
1.5
1.25
TIME – 2␮s/DIV
1.0
TPC 13. AD7398 Shutdown Recovery
2
4
3
5
POWER SUPPLY VOLTAGE – V
6
TPC 16. AD7398 Supply Current vs. Supply Voltage
–10–
REV. 0
AD7398/AD7399
3.0
AD7398/AD7399
VDD = +5V
VSS = –5V
NOMINAL CHANGE IN VOLTAGE – mV
SUPPLY CURRENT – mA
2.5
1.0
2.0
1.5
1.0
0.5
0
–50
0
50
100
SHUTDOWN CURRENT – ␮A
AD7398/AD7399
VDD = +5V
VSS = –5V
34
33
32
–20
0
20
40
60
80
TEMPERATURE – ⴗC
100
120
140
TPC 18. Shutdown Current vs. Temperature
REV. 0
0.25
CODE = 000H
100
200
400
300
HOURS OF OPERATION AT 150ⴗC
500
TPC 19. AD7398 Long-Term Drift
36
–40
CODE = FFFH
0.5
0
TPC 17. Supply Current vs. Temperature
31
–60
0.75
0
150
TEMPERATURE – ⴗC
35
AD7398
SAMPLE SIZE = 135
VREF = 2.5V
–11–
600
AD7398/AD7399
VREF A B C D
VDD
AD7398/AD7399
CS
INPUT
REGISTER
DAC
REGISTER
DAC A
VOUTA
INPUT
REGISTER
DAC
REGISTER
DAC B
VOUTB
INPUT
REGISTER
DAC
REGISTER
DAC C
VOUTC
INPUT
REGISTER
DAC
REGISTER
DAC D
VOUTD
CLK
ADDRESS
DECODE
4
SDI
SERIAL
REGISTER
12/10
POWER
ON RESET
GND
RS
LDAC
VSS
Figure 4. Simplified Block Diagram
CIRCUIT OPERATION
The AD7398 and AD7399 contain four, 12-bit and 10-bit,
voltage-output, digital-to-analog converters respectively. Each
DAC has its own independent multiplying reference input. Both
AD7398/AD7399 use 3-wire SPI-compatible serial data interface,
with an asynchronous RS pin for zero-scale reset. In addition, a
LDAC strobe enables four channel simultaneous updates for
hardware synchronized output voltage changes.
The nominal DAC output voltage is determined by the externally applied VREF and the digital data (D) as:
VOUT = VREF ×
D
4096
(For AD7398)
(1)
VOUT = VREF ×
D
1024
(For AD7399)
(2)
Where D is the 12-bit or 10-bit decimal equivalent of the data
word. VREF is the externally applied reference voltage.
D/A Converter Section
VDD
AD7398/AD7399
VREF
VOUTA
R
GND
R
VSS
Figure 5. Simplified DAC Channel
DAC OPERATION
The internal R-2R ladder of the AD7398 and AD7399 operate
in the voltage switching mode maintaining an output voltage
that is the same polarity as the input reference voltage. A proprietary scaling technique is used to attenuate the input reference
voltage in the DAC. The output buffer amplifies the internal
DAC output to achieve a VREF to VOUT gain of unity.
In order to maintain good analog performance, bypass power
supplies with 0.01 µF ceramic capacitors (mount them close to
the supply pins) and 1 µF–10 µF Tantalum capacitors in parallel. In additions, clean power supplies with low ripple voltage
capability should be used. Switching power supplies may be
used for this application but beware of its higher ripple voltage
and PSS frequency-dependent characteristics. It is also best to
supply the AD7398/AD7399’s power from the system’s analog
supply voltages. (Don’t use the digital 5 V supply).
The reference input resistance is code dependent exhibiting
worst case 35 kΩ for AD7398 when the DAC is loaded with
alternating codes 010101010101. Similarly, the reference input
resistance is 40 kΩ for AD7399 when the DAC is loaded with
0101010101.
OPERATION WITH V REF EQUAL TO THE SUPPLY
The AD7398/AD7399 is designed to approach the full output
voltage swing from ground to VDD or VSS. The maximum output
swing is achieved when the corresponding VREF input pin is tied
to the same power supply. This power supply should be low
noise and low ripple, preferably operated by a suitable reference
voltage source such as ADR292 and REF02. The output swing
–12–
REV. 0
AD7398/AD7399
is limited by the internal buffer offset voltage and the output
drive current capability of the output stage. One should at least
budget the VZSE offset voltage as the closest the output voltage
can get to either supply voltage under a no load condition. Under
a loaded output, degrade the headroom by a factor of 2 mV per
1 mA of load current. Also note that the internal op amp has an
offset voltage so that the first eight codes of AD7398 may not
respond at either the supply voltage or at ground until the internal
DAC voltage exceeds the output buffers offset voltage. Similarly, the first two codes of AD7399 should not be used.
POWER SUPPLY SEQUENCING
VDD/VSS of AD7398/AD7399 should be powered from the system
analog supplies. In addition, VIN of the external reference should
also be coming from the same supply. Such practice will avoid
a possible latch-up when the reference is powered on prior to
VDD/VSS, or powered off subsequent to VDD/VSS. If VDD/VSS
and VREF are separate power sources, then ensure VDD/VSS is
powered on before VREF and powered off after VREF. In addition,
VREF pins of the unused DACs should also be connected to GND
or some power sources to ensure similar power-up/-down sequence.
serial data is in 8-bit bytes, two right-justified data bytes can be
written to the AD7398 and AD7399. Keeping the CS line low
between the first and second bytes transfer will result in a successful serial register update.
Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new data to the target
DAC register, determined by the decoding of address Bits A1
and A0. For the AD7398, Tables I, II, IV, and Figures 2 and
3 define the characteristics of the software serial interface. For
the AD7399, Tables I, III, IV, and Figure 3 (with 14-bits exception) define the characteristics of the software serial interface.
Figures 6 and 7 show the equivalent logic interface for the key
digital control pins for AD7398 and AD7399.
An asynchronous RS provides hardware control reset to zerocode state over the preset function and DAC Register loading. If
this function is not needed, the RS pin can be tied to logic high.
TO INPUT REGISTER
ADDRESS
DECODER
CS
PROGRAMMABLE POWER SHUTDOWN
The two MSBs of the serial input register, SA and SD, are used
to program various shutdown modes. If SA is set to Logic 1, all
DACs will be in shutdown mode. If SA = 0 and SD = 1, a corresponding DAC will be shut down addressed by Bits A0 and
A1, See Tables II–IV.
EN
A
B
C
D
SHIFT REGISTER
CLK
SDI
Figure 6. Equivalent Logic Interface
WORST CASE ACCURACY
POWER-ON RESET
Assuming a perfect reference, the worst-case output voltage may
be calculated from the following equation.
When the VDD power supply is turned ON, an internal reset
strobe forces all the Input and DAC registers to the zero-code
state. The VDD power supply should have a smooth positive
ramp without drooping in order to have consistent results,
especially in the region of VDD = 1.5 V to 2.2 V. The VSS supply has no effect on the power-on reset performance. The
DAC register data will stay at zero until a valid serial register
data load takes place.
VOUT =
D
× (VREF + VFSE ) + VZSE + INL
2N
(3)
where
D = Decimal Code Loaded to DAC Ranges 0 ≤ D ≤ 2N–1
N = Number of Bits
VREF = Applied Reference Voltage
VFSE = Full-Scale Error in Volts
VZSE = Zero-Scale Error in Volts
INL = Integral Nonlinearity in Volts INL is 0 at Full Scale
or Zero Scale
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND) and VDD as shown in Figure 7.
VDD
DIGITAL INPUTS
SERIAL DATA INTERFACE
The AD7398/AD7399 uses a 3-wire (CS, SDI, CLK) SPIcompatible serial data interface. Serial data of the AD7398 and
AD7399 is clocked into the serial input register in a 16-bit and
14-bit data-word format respectively. MSB bits are loaded first.
Table II defines the 16 data-word bits for AD7398. Table III
defines the 14 data-word bits for the AD7399. Data is placed on
the SDI pin, and clocked into the register on the positive clock
edge of CLK subject to the data setup and data hold time
requirements specified in the Interface Timing specifications.
Data can only be clocked in while the CS chip select pin is
active low. For the AD7398, only the last 16 bits which are
clocked into the serial register, will be interrogated when the CS
pin returns to the logic high state, extra data bits are ignored.
For the AD7399, only the last 14 bits, which are clocked into
the serial register, will be interrogated when the CS pin returns
to the logic high state. Since most microcontrollers’ output
REV. 0
5k⍀
GND
Figure 7. Equivalent ESD Protection Circuits
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD7398/AD7399 is via a
serial bus that uses standard protocol compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire interface consisting of a clock signal, a data signal
and a synchronization signal. The AD7398/AD7399 requires a
16-bit/14-bit data word with data valid on the rising edge of CLK.
The DAC update may be done automatically when all the data
is clocked in, or it may be done under control of LDAC.
–13–
AD7398/AD7399
ADSP-2101/ADSP-2103 to AD7398/AD7399 Interface
80C51/80L51 to AD7398/AD7399 Interface
Figure 8 shows a serial interface between the AD7398/AD7399
and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103
is set to operate in the SPORT (Serial Port) transmit alternate
framing mode. The ADSP-2101/ADSP-2103 is programmed
through the SPORT control register and should be configured
as follows: Internal Clock Operation, Active Low Framing,
16-Bit-Word Length. For the AD7398, transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. For the AD7399, the first two bits are don’t care as the
AD7399 will keep the last 14 bits. Similarly, transmission is
initiated by writing a word to the Tx register after the SPORT
has been enabled. Because of the edge-triggered difference, an
inverter is required at the SCLKs between the DSP and the DAC.
A serial interface between the AD7398/AD7399 and the 80C51/
80L51 microcontroller is shown in Figure 11. TxD of the microcontroller drives the CLK of the AD7398/AD7399, while RxD
drives the serial data line of the DAC. P3.3 is a bit programmable pin on the serial port which is used to drive CS.
FO
ADSP-2101/ TFS
ADSP-2103* DT
SCLK
SDI
AD7398/
AD7399
CLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 8. ADSP-2101/ADSP-2103 to AD7398/AD7399
Interface
68HC11 to AD7398/AD7399 Interface
Figure 9 shows a serial interface between the AD7398/AD7399
and the 68HC11 microcontroller. SCK of the 68HC11 drives
the CLK of the DAC, while the MOSI output drives the serial
data lines SDI. CS signal is driven from one of the port lines.
The 68HC11 is configured for master mode; MSTR = 1, CPOL = 0,
and CPHA = 0. Data appearing on the MOSI output is valid on
the rising edge of SCK.
PC6
PC7
68HC11/
68L11* MOS1
SCK
LDAC
CS
SDI
P3.4
LDAC
P3.3
CS
RXD
SDI
TXD
CLK
AD7398/
AD7399
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. 80C51/80L51 to AD7398/AD7399 Interface
Note that the 80C51/80L51 provides the LSB first, while the
AD7398/AD7399 expect the MSB of the 16-bit/14-bit word
first. Care should be taken to ensure the transmit routine takes
this into account. It can usually be done through software by
shifting out and accumulating the bits in the correct order
before inputting to the DAC. In addition, 80C51 outputs two
byte words/16 bits data, thus for AD7399, the first two bits,
after rearrangement, should be Don’t Care as they will be
dropped from the AD7399’s 14-bit word.
LDAC
CS
80C51/
80L51*
AD7398/
AD7399
CLK
*ADDITIONAL PINS OMITTED FOR CLARITY
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock
must be inverted as the DAC clocks data into the input shift
register on the rising edge of the serial clock. The 80C51/80L51
transmits its data in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. As AD7399 requires a 14-bit
word, P3.3 (or any one of the other programmable bits) is the CS
input signal to the DAC, so P3.3 should be brought low at the
beginning of the 16-bit write cycle 2 × 8 bit words, and held low
until the 16-bit 2 × 8 cycle is completed. After that, P3.3 is
brought high again and the new data loads to the DAC. Again,
the first two bits, after rearranging, should be don’t care. LDAC
on the AD7398/AD7399 may also be controlled by the 80C51/
80L51 serial port output by using another bit-programmable
pin, P3.4.
Figure 9. 68HC11/68L11 to AD7398/AD7399 Interface
MICROWIRE to AD7398/AD7399 Interface
Figure 10 shows an interface between the AD7398/AD7399 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and into the AD7398/
AD7399 on the rising edge of the serial clock. No glue logic is
required as the DAC clocks data into the input shift register on
the rising edge.
CS
MICROWIRE*
SO
SCK
CS
SDI
CLK
AD7398/
AD7399
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 10. MICROWIRE to AD7398/AD7399 Interface
–14–
REV. 0
AD7398/AD7399
APPLICATIONS
VREF
STAIRCASE WINDOWS COMPARATOR
WINDOW 2
VOUTD
Figure 15. Overlapping Windows Range
V+
10k⍀
VREF
WINDOW 1
VDD
VREFA
V+
10k⍀
WINDOW 2
VOUTA
AD7398/
AD7399
VOUTB
VOUTC
VREFC
V+
10k⍀
WINDOW 3
With AD7398/AD7399’s flexibility, one of the internal DACs
can be used to control a common programmable VREFX for the
rest of the DACs.
V+
10k⍀
WINDOW 4
The circuit configuration is shown in Figure 16. The relationship of VREFX to VREF is dependent upon the digital code and
the ratio of R1 and R2, and is given by:

R2 
D R2
VREFX = VREF × 1 +
 – VREFX × N ×

R1 
2
R1
V+
10k⍀
WINDOW 5
1/2 AD8564
VREFD
The nonoverlapping circuit employs one AD7398/AD7399 and
ten comparators to achieve five voltage windows. These windows
range between VREF and analog ground as shown in Figure 13.
Similarly, the overlapping circuit employs six comparators to
achieve three overlapping windows, Figure 15.
PROGRAMMABLE DAC REFERENCE VOLTAGE
AD8564
VREFB
VOUTD
GND
VREFX
Figure 12. Nonoverlapping Windows Comparator
(5)

R2 
VREF × 1 +


R1 
=

D R2 
1 + N ×

 2
R1 
(6)
Where D = Decimal Equivalent of Input Code
N = Number of Bits
VREF = Applied External Reference
VREFX = Reference Voltage for DAC A to D
VREF
WINDOW 1
VOUTA
VOUTB
WINDOW 3
VOUTC
GND
VTEST
AD8564
WINDOW 1
VOUTB
VOUTA
Many applications need to determine whether voltage levels are
within predetermined limits. Some requirements are for nonoverlapping windows and others for overlapping windows. Both
circuit configurations are shown in Figures 12 and 13 respectively.
WINDOW 2
WINDOW 3
VOUTC
WINDOW 4
VOUTD
GND
Table V. VREFX vs. R1 and R2
WINDOW 5
Figure 13. Nonoverlapping Windows Range
VTEST
V+
AD8564
VREF
10k⍀
WINDOW 1
VDD
VREFA
VOUTA
VREFB
VOUTB
V+
10k⍀
WINDOW 2
AD7398/
AD7399
VREFC
VOUTC
VREFD
VOUTD
1/2 AD8564
R1, R2
Digital Code
VREFX
R1 = R2
R1 = R2
R1 = R2
R1 = 3R2
R1 = 3R2
R1 = 3R2
0000
1000
1111
0000
1000
1111
2 VREF
1.3 VREF
VREF
4 VREF
1.6 VREF
VREF
0000
0000
1111
0000
0000
1111
The accuracy of VREFX will be affected by the quality of R1 and
R2 and therefore, tight tolerance low tempco thin film resistors
should be used.
V+
10k⍀
WINDOW 3
GND
Figure 14. Overlapping Windows Comparator
REV. 0
0000
0000
1111
0000
0000
1111
–15–
AD7398/AD7399
R2ⴞ0.1%
VREFA
VOUTA
DAC A
R1ⴞ0.1%
VREF
VIN
VREFB
C02179–4.5–10/00 (rev. 0)
ADR293
VOUTB
DAC B
VREFC
VOUTC
TO OTHER
COMPONENTS
DAC C
VREFD
VOUTD
DAC D
AD7398/AD7399
Figure 16. Programmable DAC Reference
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Wide SOIC
(R-16)
16-Lead TSSOP
(RU-16)
0.4133 (10.50)
0.3977 (10.00)
9
16
9
0.2992 (7.60)
0.2914 (7.40)
1
8
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
0.4193 (10.65)
0.3937 (10.00)
1
PIN 1
0.050 (1.27)
BSC
0.0118 (0.30)
0.0040 (0.10)
0.1043 (2.65)
0.0926 (2.35)
8ⴗ
0.0192 (0.49) SEATING
0ⴗ
0.0125
(0.32)
0.0138 (0.35) PLANE
0.0091 (0.23)
8
PIN 1
0.0291 (0.74)
ⴛ 45ⴗ
0.0098 (0.25)
0.006 (0.15)
0.002 (0.05)
0.0500 (1.27)
0.0157 (0.40)
SEATING
PLANE
–16–
0.0433 (1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
REV. 0
PRINTED IN U.S.A.
16
0.201 (5.10)
0.193 (4.90)