a CMOS 200 MHz Quadrature Digital Upconverter AD9856 APPLICATIONS HFC Data, Telephony and Video Modems Wireless and Satellite Communications Cellular Basestations FEATURES Universal Low Cost Modulator Solution for Communications Applications DC to 80 MHz Output Bandwidth Integrated 12-Bit D/A Converter Programmable Sample Rate Interpolation Filter Programmable Reference Clock Multiplier Internal SIN(x)/x Compensation Filter >52 dB SFDR @ 40 MHz AOUT >48 dB SFDR @ 70 MHz AOUT >80 dB Narrowband SFDR @ 70 MHz A OUT +3 V Single Supply Operation Space-Saving Surface-Mount Packaging Bidirectional Control Bus Interface Supports Burst and Continuous Tx Modes Single Tone Mode for Frequency Synthesis Applications Four Programmable, Pin-Selectable Modulator Profiles Direct Interface to AD8320/AD8321 PGA Cable Driver GENERAL DESCRIPTION The AD9856 integrates a high speed direct-digital synthesizer (DDS), a high performance, high speed 12-bit digital-to-analog converter (DAC), clock multiplier circuitry, digital filters and other DSP functions onto a single chip, to form a complete quadrature digital upconverter device. The AD9856 is intended to function as a universal I/Q modulator and agile upconverter for communications applications, where cost, size, power dissipation and dynamic performance are critical attributes. The AD9856 is available in a space-saving surface mount package and specified to operate over the extended industrial temperature range of –40°C to +85°C. COMPLEX DATA IN TxENABLE (I/Q SYNC) DEMULTIPLEXER AND SERIAL-TO-PARALLEL CONVERTER FUNCTIONAL BLOCK DIAGRAM 12 12 43–83 SELECTABLE INTERPOLATING HALFBANDS 43–83 SELECTABLE INTERPOLATING HALFBANDS 43–203PROG. CLOCK MULTIPLIER REFERENCE CLOCK IN 12 23 TO 633 SELECTABLE INTERPOLATOR 12 AD9856 12 12 12 23 TO 633 SELECTABLE INTERPOLATOR 12 12 SINE INV 12 SINC 12 PROFILE SELECT 3–4 DC-80 MHz OUTPUT DAC RSET 12 COSINE DDS AND CONTROL FUNCTIONS PROFILE SELECT 1–2 12-BIT DAC MASTER RESET SPI INTERFACE TO AD8320/AD8321 PROGRAMMABLE CABLE DRIVER AMPLIFIER BIDIRECTIONAL SPI CONTROL INTERFACE: 32-BIT FREQUENCY TUNING WORD FREQUENCY UPDATE INTERPOLATION FILTER RATE REFERENCE CLOCK MULTIPLIER RATE SPECTRAL PHASE INVERSION ENABLE CABLE DRIVER AMPLIFIER CONTROL REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 (VS = +3 V ⴞ 5%, RSET = 3.9 k⍀, External reference clock frequency = 10 MHz AD9856–SPECIFICATIONS with REFCLK Multiplier enabled at 20ⴛ). Parameter Temp Test Level REF CLOCK INPUT CHARACTERISTICS Frequency Range REFCLK Multiplier Disabled REFCLK Multiplier Enabled at 4× REFCLK Multiplier Enabled at 20× Duty Cycle Input Capacitance Input Impedance Full Full Full +25°C +25°C +25°C VI VI VI V V V DAC OUTPUT CHARACTERISTICS Resolution Full-Scale Output Current Gain Error Output Offset Differential Nonlinearity Integral Nonlinearity Output Capacitance Phase Noise @ 1 kHz Offset, 40 MHz AOUT REFCLK Multiplier Enabled at 20× REFCLK Multiplier at 4× REFCLK Multiplier Disabled Voltage Compliance Range Wideband SFDR: 1 MHz Analog Out 20 MHz Analog Out 42 MHz Analog Out 65 MHz Analog Out 80 MHz Analog Out Narrowband SFDR: (± 100 kHz Window) 70 MHz Analog Out Min AD9856 Typ 5 5 5 Max Units 2001 50 10 MHz MHz MHz % pF MΩ 50 3 100 5 –10 12 10 20 +10 10 Bits mA %FS µA LSB LSB pF +25°C +25°C +25°C +25°C +25°C I I V V V +25°C +25°C +25°C +25°C V V V I +25°C +25°C +25°C +25°C +25°C IV IV IV IV IV 70 65 60 55 50 dBc dBc dBc dBc dBc +25°C IV 80 dBc MODULATOR CHARACTERISTICS Adjacent Channel Power (CH Power = –6.98 dBm) Error Vector Magnitude I/Q Offset Inband Spurious Emissions Pass Band Amplitude Ripple (DC to 80 MHz) +25°C +25°C +25°C +25°C +25°C IV IV IV IV V TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulsewidth High (tPWH) Minimum Clock Pulsewidth Low (tPWL) Maximum Clock Rise/Fall Time Minimum Data Setup Time (tDS ) Minimum Data Hold Time (tDH) Maximum Data Valid Time (tDV) Wake-Up Time2 Minimum RESET Pulsewidth High (tRH) Full Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV IV CMOS LOGIC INPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance +25°C +25°C +25°C +25°C +25°C I I I I V –2– 0.5 1 5 –85 –100 –110 –0.5 1.5 50 50 45 1 55 50 ± 0.3 2 10 30 30 1 25 0 30 1 5 +2.6 +0.4 12 12 3 dBc/Hz dBc/Hz dBc/Hz V dBm % dB dBc dB MHz ns ns ms ns ns ns ms REFCLK Cycles V V µA µA pF REV. B AD9856 Parameter Temp Test Level CMOS LOGIC OUTPUTS (1 mA LOAD) Logic “1” Voltage Logic “0” Voltage +25°C +25°C I I POWER SUPPLY +VS Current Full Operating Conditions2 Burst Operation (25%) Single Tone Mode 160 MHz Clock 120 MHz Clock Power-Down Mode +25°C +25°C +25°C +25°C +25°C +25°C I I I I I I Min AD9856 Typ Max Units 0.4 mA mA 530 450 495 445 345 2 mA mA mA mA mA mA 2.7 NOTES 1 For 200 MHz operation in Modulation Mode at +85 °C operating temperature, V S must be +3 V min. 2 Assuming 1.3 kΩ and 0.01 µF loop filter components. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS Maximum Junction Temperature . . . . . . . . . . . . . . . .+165°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4 V Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . .+300°C Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 38°C/W Test Level I – III – IV – V – VI – *Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. 100% Production Tested. Sample Tested Only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. Devices are 100% production tested at +25°C and guaranteed by design and characterization testing for industrial operating temperature range. ORDERING GUIDE Model Temperature Range Package Description Package Option AD9856AST AD9856/PCB –40°C to +85°C Thin Quad Flatpack ST-48 +25°C Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9856 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –3– WARNING! ESD SENSITIVE DEVICE AD9856 PIN FUNCTION DESCRIPTIONS Pin # Pin Name Pin Function Pin # Pin Name Pin Function 1 TxENABLE 29 IOUTB 2 3 4, 10, 21, 44 5, 11, 20, 43 6–9 12–16 17 D11 D10 Input Pulse that Synchronizes the Data Stream Input Data (Most Significant Bit) Input Data 30 IOUT DVDD Digital Supply Voltage DGND D9–D6 D5–D1 D0 Digital Ground Input Data Input Data Input Data (Least Significant Bit) NC No Internal Connection AGND BG REF BYPASS DAC RSET DAC REF BYPASS AVDD Analog Ground No External Connection* RSET Resistor Connection No External Connection* Analog Supply Voltage 32 33 34 35 36 37 38 39 40 41 42 45 46 47 48 PLL GND PLL FILTER PLL SUPPLY CA ENABLE CA DATA CA CLK CS SDO SDIO SCLK SYNC I/O PS0 PS1 REFCLK RESET Complementary Analog Current Output of the DAC True Analog Current Output of DAC PLL Ground PLL Loop Filter Connection PLL Voltage Supply Cable Driver Amp Enable Cable Driver Amp Data Cable Driver Amp Clock Chip Select Serial Data Output Serial Port I/O Serial Port Clock Performs I/O Synchronization Profile Select 0 Profile Select 1 Reference Clock Input Master Reset 18, 19, 22 23, 28, 31 24 25 26 27 *In most cases optimal performance is achieved with no external connection. For extremely noisy environments BG REF BYPASS can be bypassed with up to a 0.1 µF capacitor to AGND (Pin 23). DAC REF BYPASS can be bypassed with up to a 0.1 µF capacitor to AVDD (Pin 27). CS CA CLK SDO SYNC I/O SCLK SDIO PS0 DVDD DGND RESET REFCLK PS1 PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 TxENABLE 1 D11 2 36 PIN 1 IDENTIFIER D10 3 DVDD 4 DGND 5 AD9856 D9 6 TOP VIEW (Not to Scale) D8 7 D7 8 35 CA DATA CA ENABLE 34 PLL SUPPLY 33 32 PLL FILTER PLL GND 31 AGND 30 IOUT 29 IOUTB D6 9 DVDD 10 28 27 AGND AVDD DGND 11 26 DAC REF BYPASS D5 12 25 DAC RSET –4– BG REF BYPASS AGND DGND DVDD NC NC NC D1 D0 13 14 15 16 17 18 19 20 21 22 23 24 D4 D3 D2 NC = NO CONNECT REV. B AD9856 FUNCTIONAL BLOCK AND MODE DESCRIPTION Operating Modes 1. Complex quadrature modulator mode. 2. Single tone output mode. Input Data Format Programmable: 12-bit, 6-bit, or 3-bit input formats. Data input to the AD9856 is 12-bit, twos complement. Complex I/Q symbol component data is required to be at least 2× oversampled, depending upon configuration. Up to 50 Msamples/s @ 200 MHz SYSCLK rate. For DC-80 MHz AOUT operation (200 MHz SYSCLK rate): w/REFCLK Multiplier enabled: 10 MHz–50 MHz, programmable via control bus w/REFCLK Multiplier disabled: 200 MHz. Note: For optimum data synchronization, the AD9856 Reference Clock, and the input data clock, should be derived from the same clock source. Programmable in integer steps over the range of 4×–20×. Can be disabled (effective REFCLK Multiplier = 1) via control bus. Output of REFCLK Multiplier = SYSCLK rate, which is the internal clock rate applied to the DDS and DAC function. Four pin-selectable, preprogrammed formats. Available for modulation and single tone operating modes. Fixed 4×, selectable 2× and selectable 2×–63× range. Interpolating filters that provide upsampling and reduce the effects of the CIC passband roll-off characteristics. When Burst Mode is enabled via the control bus, the rising edge of the applied TxENABLE pulse should be coincident with, and frame, the input data packet. This establishes data sampling synchronization. When continuous mode is enabled via the control bus, the TxENABLE pin becomes an I/Q control line. A Logic “1” on TxENABLE indicates I data is being presented to the AD9856. A Logic “0” on TxENABLE indicates Q data is being presented to the AD9856. Each rising edge of TxENABLE resynchronizes the AD9856 input sampling capability. Precompensates for SIN(x)/x roll-off of DAC; user bypassable. [I × Cos(ωt) + Q × Sin(ωt)] or [I × Cos(ωt) – Q × Sin(ωt)] (default), configurable via control bus, per profile. Power dissipation reduced to less than 6 mW when Full Sleep Mode active, programmable via control bus. Input Sample Rate Input Reference Clock Frequency Internal Reference Clock Multiplier Profile Select Interpolating Range Half-Band Filters TxENABLE Function–Burst Mode TxENABLE Function–Continuous Mode Inverse SINC Filter I/Q Channel Invert Full Sleep Mode REV. B –5– AD9856 Typical Modulated Output Spectral Plots REF LVL –25dBm RBW VBW SWT 10kHz 1kHz 12.5s RF ATT 10dB Unit REF LVL –25dBm dBm 0 0 –8 –8 1AP –24 RF ATT Unit 10dB dBm 1AP –24 –32 dBm –32 dBm 10kHz 1kHz 20s –16 –16 –40 –40 –48 –48 –56 –56 –64 –64 –72 –72 –80 START 0Hz –80 5MHz/ START 0Hz STOP 50MHz REF LVL –30dBm RBW VBW SWT 10kHz 1kHz 10s RF ATT 10dB UNIT dBm REF LVL –30dBm STOP 80MHz RBW VBW SWT 10kHz 1kHz 12.5s RF ATT UNIT 10dB dBm 0 0 –8 –8 –16 –16 1AP –24 1AP –24 8MHz/ Figure 3. 16-QAM at 65 MHz and 2.56 MS/s; 10.24 MHz External Clock with REFCLK Multiplier = 18, CIC = 9, HB3 Off, 2× Data Figure 1. QPSK at 42 MHz and 2.56 MS/s; 10.24 MHz External Clock with REFCLK Multiplier = 12, CIC = 3, HB3 On, 2× Data –32 dBm –32 dBm RBW VBW SWT –40 –40 –48 –48 –56 –56 –64 –64 –72 –72 –80 START 0Hz –80 START 0Hz 4MHz/ STOP 40MHz 5MHz/ STOP 50MHz Figure 4. 256-QAM at 38 MHz and 6 MS/s; 48 MHz External Clock with REFCLK Multiplier = 4, CIC = 2, HB3 Off, 4× Data Figure 2. 64-QAM at 28 MHz and 6 MS/s; 36 MHz External Clock with REFCLK Multiplier = 4, CIC = 2, HB3 Off, 3× Data –6– REV. B AD9856 Typical Single Tone Output Spectral Plots RBW VBW SWT REF LVL –5dBm 3kHz 3kHz 28s RF ATT UNIT 20dB RBW VBW SWT REF LVL –5dBm dB 0 3kHz 3kHz 28s RF ATT UNIT 20dB dB 0 A A –10 –10 –20 –20 –30 –30 1AP 1AP –40 dBm dBm –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 START 0Hz 10MHz/ STOP 100MHz START 0Hz Figure 5. 21 MHz CW Output RBW VBW SWT REF LVL –5dBm 3kHz 3kHz 28s RF ATT UNIT 10MHz/ STOP 100MHz Figure 7. 42 MHz CW Output 20dB RBW VBW SWT REF LVL –5dBm dB 0 3kHz 3kHz 28s RF ALT UNIT 20dB dB 0 A A –10 –10 –20 –20 –30 –30 1AP 1AP –40 dBm dBm –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 START 0Hz 10MHz/ STOP 100MHz START 0Hz Figure 6. 65 MHz CW Output REV. B 10MHz/ STOP 100MHz Figure 8. 79 MHz CW Output –7– AD9856 Typical Narrowband SFDR Spectral Plots REF LVL –5dBm RBW VBW SWT 100Hz 100Hz 50s RF ATT UNIT 20dB REF LVL –5dBm dB RBW VBW SWT 100Hz 100Hz 50s RF ATT UNIT 20dB dB 0 0 A A –10 –12 –20 –24 –36 –30 1AP 1AP –48 dBm dBm –40 –50 –60 –60 –72 –70 –84 –80 –96 –90 –100 –120 –100 CENTER 70.1MHz 10kHz/ CENTER 70.1MHz SPAN 100kHz 10kHz/ SPAN 100kHz Figure 11. 70.1 MHz Narrowband SFDR, 200 MHz External Clock with REFCLK Multiplier Disabled Figure 9. 70.1 MHz Narrowband SFDR, 10 MHz External Clock with REFCLK Multiplier = 20× Typical Phase Noise Spectral Plots REF LVL 0dBm 0 RBW VBW SWT 30Hz 30Hz 28s RF ATT UNIT 30dB REF LVL 0dBm dB FXD –2.248dBm 0 RBW VBW SWT 30Hz 30Hz 28s RF ATT UNIT 30dB dB FXD –2.248dBm A A –12 –12 –24 –24 –36 –36 1AP 1AP –48 dBm dBm –48 –60 –60 –72 –72 –84 –84 –96 –96 –100 –108 FXD FXD –120 –120 CENTER 40.1MHz 500Hz/ CENTER 40.1MHz SPAN 5kHz 500Hz/ SPAN 5kHz Figure 12. 40.1 MHz Output, 200 MHz External Clock with REFCLK Multiplier Disabled Figure 10. 40.1 MHz Output, 10 MHz External Clock with REFCLK Multiplier = 20 × –8– REV. B AD9856 Typical Plots of Output Constellations TRACE A: CH 1 16QAM MEAS TIME 1.25 TRACE A: CH 1 QPSK MEAS TIME 1.5 CONST CONST 300 M /DIV 250 M /DIV –1.25 –1.5 –1.9607843757 –1.6339869797 1.96078437567 Figure 13. QPSK, 65 MHz, 2.56 MS/s Figure 15. 16-QAM, 65 MHz, 2.56 MS/s TRACE A: CH 1 64QAM MEAS TIME 1 TRACE A: CH 1 256QAM MEAS TIME 1 CONST CONST 200 M /DIV 200 M /DIV –1 –1 –1.3071895838 1.30718958378 –1.3071895838 Figure 14. 64-QAM, 42 MHz, 6 MS/s 1.30718958378 Figure 16. 256-QAM, 42 MHz, 6 MS/s TRACE A: CH 1 MSK1 MEAS TIME 1.5 CONST 300 M /DIV –1.5 –1.9607843757 1.96078437567 Figure 17. GMSK Modulation, 13 MS/s REV. B 1.63398697972 –9– AD9856 Power Consumption 1600 +VS = +3V CIC = 2 +258C POWER CONSUMPTION – mW POWER CONSUMPTION – mW 1600 1400 HB3 = OFF 1200 HB3 = ON 1000 800 120 +VS = +3V CIC = 2 200MHz +258C 1500 HB3 = OFF 1400 1300 HB3 = ON 1200 140 160 CLOCK SPEED – MHz 180 0 200 Figure 18. Power Consumption vs. Clock Speed; +VS = +3 V, CIC = 2, +25 °C 16 32 CIC RATE 48 64 Figure 19. Power Consumption vs. CIC Rate; +VS = +3 V, 200 MHz, +25 °C POWER CONSUMPTION – mW 1450 1350 +VS = +3V CIC = 2 200MHz +258C 1250 1150 1050 25 50 75 Tx ENABLE DUTY CYCLE 100 Figure 20. Power Consumption vs. Burst Duty Cycle; +VS = +3 V, CIC = 2, 200 MHz, +25 °C –10– REV. B AD9856 Table I. Serial Control Bus Register Layout Register AD9856 Register Layout Address (hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default (hex) Profile 00 SDO Active LSB First REFCLK Mult.<4> REFCLK Mult.<3> REFCLK Mult.<2> REFCLK Mult.<1> REFCLK Mult.<0> Reserved 15 N/A 01 CIC Gain Continuous Mode Full Sleep Mode Single Tone Mode Bypass Inverse Sinc Filter Bypass REFCLK Mult. Input Format Select <1> Input Format Select <0> 06 N/A 02 Frequency Tuning Word <7:0> 04 1 03 Frequency Tuning Word <15:8> 00 1 04 Frequency Tuning Word <23:16> 00 1 05 Frequency Tuning Word <31:24> 00 1 FC 1 06 Interpolator Rate <5> Interpolator Rate <4> Interpolator Rate <3> Interpolator Rate <2> Interpolator Rate <1> Interpolator Rate <0> Spectral Inversion Bypass the Third Half Band Filter 07 AD8320/AD8321 Gain Control Bits <7:0> 00 1 08 Frequency Tuning Word <7:0> 00 2 09 Frequency Tuning Word <15:8> 00 2 0A Frequency Tuning Word <23:16> 00 2 0B Frequency Tuning Word <31:24> 80 2 1E 2 0C Interpolator Rate <5> Interpolator Rate <4> Interpolator Rate <3> Interpolator Rate <2> Interpolator Rate <1> Interpolator Rate <0> Spectral Inversion Bypass the Third Half Band Filter 0D AD8320/AD8321 Gain Control Bits <7:0> 00 2 0E Frequency Tuning Word <7:0> Unset 3 0F Frequency Tuning Word <15:8> Unset 3 10 Frequency Tuning Word <23:16> Unset 3 11 Frequency Tuning Word <31:24> Unset 3 Unset 3 12 Interpolator Rate <5> Interpolator Rate <4> Interpolator Rate <3> Interpolator Rate <2> Interpolator Rate <1> Interpolator Rate <0> Spectral Inversion Bypass the Third Half Band Filter 13 AD8320/AD8321 Gain Control Bits <7:0> 00 3 14 Frequency Tuning Word <7:0> Unset 4 15 Frequency Tuning Word <15:8> Unset 4 16 Frequency Tuning Word <23:16> Unset 4 17 Frequency Tuning Word <31:24> Unset 4 Unset 4 00 4 18 19 REV. B Interpolator Rate <5> Interpolator Rate <4> Interpolator Rate <3> Interpolator Rate <2> Interpolator Rate <1> Interpolator Rate <0> AD8320/AD8321 Gain Control Bits <7:0> –11– Spectral Inversion Bypass the Third Half Band Filter AD9856 REGISTER BIT DEFINITIONS Control Bits—Register Address 00h and 01h SDO Active—Register Address 00h, Bit 7. Active high indicates serial port uses dedicated in/out lines. Default low configures serial port as single line I/O. LSB First—Register Address 00h, Bit 6. Active high indicates serial port access is LSB to MSB format. Default low indicates MSB to LSB format. INPUT FORMAT SELECT—Register Address 01h, Bits 1 and 0, form the Input Format Mode bits. 10b = 12-bit mode 01b = 6-bit mode 00b = 3-bit mode Default value is 10b (12-bit mode). Profile 1 Registers—Active when PROFILE Inputs Are 00b REFCLK Multiplier—Register Address 00h, Bits 5, 4, 3, 2, 1 form the reference clock multiplier. Valid entries range from 4–20 (decimal). Straight binary to decimal conversion is implemented. For example, to multiply the reference clock by 19 decimal, Program Register Address 00h, Bits 5–1, as 13h. Default value is 0A (hex). FREQUENCY TUNING WORD (FTW)—The frequency tuning word for Profile 1 is formed via a concatenation of register addresses 05h, 04h, 03h and 02h. Bit 7 of register address 05h is the most significant bit of the Profile 1 frequency tuning word. Bit 0 of register address 02h is the least significant bit of the Profile 1 frequency tuning word. The output frequency equation is given as: fOUT = (FTW × SYSCLK)/232. RESERVED BIT—Register Address 00h, Bit 0. This bit is reserved. Always set this bit to Logic 1 when writing to this register. INTERPOLATION RATE—Register Address 06h, Bits 7 through 2 form the Profile 1 CIC filter interpolation rate value. Allowed values range from 2 to 63 (decimal). CIC GAIN—Register Address 01h, Bit 7. The CIC GAIN bit multiplies the CIC filter output by 2. See the Cascaded Integrated Comb Filter section of this data sheet for more details. Default value is 0 (inactive). SPECTRAL INVERSION—Register Address 06h, Bit 1. Active high, Profile 1 Spectral Inversion bit. When active, inverted modulation is performed [I × Cos(ωt) + Q × Sin(ωt)]. Default is inactive, logic zero, noninverted modulation [I × Cos(ωt) – Q × Sin(ωt)]. CONTINUOUS MODE—Register Address 01h, Bit 6 is the continuous mode configuration bit. Active high, configures the AD9856 to accept continuous mode timing on the TxENABLE input. A low configures the device for burst mode timing. Default value is 0 (burst mode). FULL SLEEP MODE—Register Address 01h, Bit 5. Active high full sleep mode bit. When activated, the AD9856 enters a full shutdown mode, consuming less than 2 mA, after completing a shutdown sequence. Default value is 0 (awake). SINGLE TONE MODE—Register Address 01h, Bit 4. Active high configures the AD9856 for single tone applications. The AD9856 will supply a single frequency output as determined by the frequency tuning word (FTW) selected by the active profile. In this mode, the 12 input data pins are ignored but should be tied high or low. Default value is 0 (inactive). BYPASS HALF-BAND FILTER 3—Register Address 06h, Bit 0. Active high, causes the AD9856 to bypass the third half-band filter stage that precedes the CIC interpolation filter. Bypassing the third half-band filter negates the 2× upsample inherent with this filter and reduces the overall interpolation rate of the halfband filter chain from 8× to 4×. Default value is 0 (half-band 3 enabled). AD8320/AD8321 GAIN CONTROL—Register Address 07h, Bits 7 through 0 form the Profile 1 AD8320/AD8321 gain bits. The AD9856 dedicates three output pins, which directly interface to the AD8320/AD8321 cable driver amp. This allows direct control of the cable driver via the AD9856. See the Programming/Writing the AD8320/AD8321 Cable Driver Gain Control section of this data sheet for more details. Bit 7 is the MSB, Bit 0 is the LSB. Default value is 00h. BYPASS INVERSE SINC FILTER—Register Address 01h, Bit 3. Active high, configures the AD9856 to bypass the SIN(x)/ x compensation filter. Defaults value is 0 (Inverse SINC Filter Enabled). Profile 2 Registers—Active when PROFILE Inputs Are 01b BYPASS REFCLK Multiplier—Register Address 01h, Bit 2. Active high, configures the AD9856 to bypass the REFCLK Multiplier function. When active, effectively causes the REFCLK Multiplier factor to be 1. Defaults value is 1 (REFCLK Multiplier bypassed). Profile 3 Register functionality is identical to Profile 1, with the exception of the register addresses. Profile 2 Register functionality is identical to Profile 1, with the exception of the register addresses. Profile 3 Registers—Active when PROFILE Inputs Are 10b Profile 4 Registers—Active when PROFILE Inputs Are 11b Profile 4 Register functionality is identical to Profile 1, with the exception of the register addresses. –12– REV. B AD9856 THEORY OF OPERATION After passing through the half-band filter stages, the I/Q data streams are fed to a Cascaded Integrator-Comb (CIC) filter. This filter is configured as an interpolating filter, which allows further upsampling rates of any integer value between 2 and 63, inclusive. The CIC filter, like the half-bands, has a built-in lowpass characteristic. Again, this provides for suppression of the spectral images produced by the upsampling process. To gain a general understanding of the functionality of the AD9856 it is helpful to refer to Figure 21, which displays a block diagram of the device architecture. The following is a general description of the device functionality. Later sections will detail each of the data path building blocks. Modulation Mode Operation The AD9856 accepts 12-bit data words, which are strobed into the Data Assembler via an internal clock. The input, TxENABLE, serves as the “valve” which allows data to be accepted or ignored by the Data Assembler. The user has the option to feed the 12-bit data words to the AD9856 as single 12-bit words, dual 6-bit words, or quad 3-bit words. This provides the user with the flexibility to use fewer interface pins, if so desired. Furthermore, the incoming data is assumed to be complex, in that alternating 12-bit words are regarded as the inphase (I) and quadrature (Q) components of a symbol. The digital quadrature modulator stage following the CIC filters is used to frequency shift the baseband spectrum of the incoming data stream up to the desired carrier frequency (this process is known as upconversion). The carrier frequency is controlled numerically by a Direct Digital Synthesizer (DDS). The DDS uses its internal reference clock (SYSCLK) to generate the desired carrier frequency with a high degree of precision. The carrier is applied to the I and Q multipliers in quadrature fashion (90° phase offset) and summed to yield a data stream that is the modulated carrier. It should be noted at this point that the incoming data has been converted from an input sample rate of f IN to an output sample rate of SYSCLK (see the block diagram). The rate at which the 12-bit words are presented to the AD9856 will be referred to as the Input Sample Rate (fIN). It should be pointed out that fIN is not the same as the baseband data rate provided by the user. As a matter of fact, it is required that the user’s baseband data be upsampled by at least a factor of two (2) before being applied to the AD9856 in order to minimize the frequency-dependent attenuation associated with the CIC filter stage (detailed in a later section). The Data Assembler splits the incoming data word pairs into separate I/Q data streams. The rate at which the I/Q data word pairs appear at the output of the Data Assembler will be referred to as the I/Q Sample Rate (fIQ ). Since two 12-bit input data words are used to construct the individual I and Q data paths, it should be apparent that the input sample rate is twice the I/Q sample rate (i.e., fIN = 2 × fIQ). The sampled carrier is ultimately destined to serve as the input data to the digital-to-analog converter (DAC) integrated on the AD9856. The DAC output spectrum is distorted due to the intrinsic zero-order hold effect associated with DAC-generated signals. This distortion is deterministic, however, and follows the familiar SIN(x)/x (or SINC) envelope. Since the SINC distortion is predictable, it is also correctable. Hence, the presence of the optional Inverse SINC filter preceding the DAC. This is a FIR filter, which has a transfer function conforming to the inverse of the SINC response. Thus, when selected, it modifies the incoming data stream so that the SINC distortion, which would otherwise appear in the DAC output spectrum is virtually eliminated. Once through the Data Assembler, the I/Q data streams are fed through two half-band filters (half-band filters #1 and #2). The combination of these two filters results in a factor of four (4) increase of the sample rate. Thus, at the output of half-band filter #2, the sample rate is 4 × fIQ. In addition to the sample rate increase, the half-band filters provide the low-pass filtering characteristic necessary to suppress the spectral images produced by the upsampling process. Further upsampling is available via an optional third half-band filter (half-band filter #3). When selected, this provides an overall upsampling factor of eight (8). Thus, if half-band filter #3 is selected, then the sample rate at its output is 8 × fIQ. As mentioned earlier, the output data is sampled at the rate of SYSCLK. Since the AD9856 is designed to operate at SYSCLK frequencies up to 200 MHz, there is the potential difficulty of trying to provide a stable input clock (REFCLK). Although stable, high frequency oscillators are available commercially they tend to be cost prohibitive. To alleviate this problem, the AD9856 has a built-in programmable clock multiplier circuit. This allows the user to use a relatively low frequency (thus, less expensive) oscillator to generate the REFCLK signal. The low frequency REFCLK signal can then be multiplied in frequency by an integer factor of between 4 and 20, inclusive, to become the SYSCLK signal. DATA IN DATA HALF-BAND HALF-BAND HBF #3 ASSEMBLER FILTER #1 FILTER #2 BYPASS 12 12 12 I 3, 6, 12 QUADRATURE MODULATOR HALF-BAND FILTER #3 CIC FILTER 12 MUX COS 12 INV SINC TxENABLE 12 12 12 DAC AOUT 12 MUX HBF #3 BYPASS (F1) SIN (F2) DDS MUX 2 2 M = 4...20 REFCLK MULTIPLIER (M) HBF #3 BYPASS (F3) (F5) MUX 2 (F4) N (SYSCLK) N = 2...63 Figure 21. AD9856 Block Diagram REV. B MUX 12 12 Q RSET INV SINC BYPASS –13– MUX REFCLK AD9856 Single Tone Output Operation The AD9856 can be configured for frequency synthesis applications by writing the single tone bit true. In single tone mode, the AD9856 disengages the modulator and preceding datapath logic to output a spectrally pure single frequency sine wave. The AD9856 provides for a 32-bit frequency tuning word, which results in a tuning resolution of 0.046 Hz at a SYSCLK rate of 200 MHz. A good rule of thumb when using the AD9856 as a frequency synthesizer is to limit the fundamental output frequency to 40% of SYSCLK. This avoids generating aliases too close to the desired fundamental output frequency, thus minimizing the cost of filtering the aliases. All applicable programming features of the AD9856 apply when configured in single tone mode. These features include: 1. Frequency hopping via the PROFILE inputs and associated tuning word, which allows Frequency Shift Keying (FSK) modulation. 2. Ability to bypass the REFCLK Multiplier, which results in lower phase noise and reduced output jitter. 3. Ability to bypass the SIN(x)/x compensation filter. 4. Full power-down mode. INPUT WORD RATE (f W) vs. REFCLK RELATIONSHIP There is a fundamental relationship between the input word rate (fW) and the frequency of the clock that serves as the timing source for the AD9856 (REFCLK). fW is defined as the rate at which K-bit data words (K = 3, 6 or 12) are presented to the AD9856. There are, however, a number of factors that affect this relationship. They are: • • • • The interpolation rate of the CIC filter stage. Whether or not Half-Band Filter #3 is bypassed. The value of REFCLK Multiplier (if selected). Input Word Length. This relationship can be summed up with the following equation: Where H, N, I and M are integers and are determined as follows: M = I = N = | 1: Half-Band Filter #3 Bypassed | 2: Half-Band Filter #3 Enabled | 1: REFCLK Multiplier Bypassed | 4 ≤ M ≤ 20: REFCLK Multiplier Enabled | 1: Full Word Input Format | 2: Half Word Input Format | 4: Quarter Word Input Format For burst mode input timing, no external data clock needs to be provided as the data is oversampled at the D<11:0> pins using the system clock (SYSCLK). The TxENABLE pin is required to frame the data burst as the rising edge of TxENABLE is used to synchronize the AD9856 to the input data rate. The AD9856 registers the input data at the approximate center of the data valid time. It should be obvious that for larger CIC interpolation rates, more SYSCLK cycles are available to oversample the input data, maximizing clock jitter tolerances. For continuous mode input timing, the TxENABLE pin can be thought of as a data input clock running at 1/2 the input sample rate (fW/2). In addition to synchronization, for continuous mode timing, the TxENABLE input indicates to the AD9856 whether an I or Q input is being presented to the D<11:0> pins. It is intended that data is presented in alternating fashion such that I data is followed by Q data. Stated another way, the TxENABLE pin should maintain approximately a 50/50 duty cycle. As in burst mode, the rising edge of TxENABLE synchronizes the AD9856 to the input data rate and the data is registered at the approximate center of the data valid time. The continuous operating mode can only be used in conjunction with the full word input format. Burst Mode Input Timing Figures 22–26 describe the input timing relationship between TxENABLE and the 12-bit input data word for all three input format modes when the AD9856 is configured for burst input timing. Also shown in these diagrams is the time-aligned, 12-bit parallel I/Q data as assembled by the AD9856. Figure 22 describes the classic burst mode timing, for full word input mode, in which TxENABLE frames the input data stream. Note that sequential input of alternating I/Q data, starting with I data, is required. REFCLK = (2 HNf W)/MI H = form a 12-bit word. The quarter word mode accepts multiple 3-bit I and Q data inputs to form a 12-bit word. For all word length modes, the AD9856 assembles the data for signal processing into time aligned, parallel 12-bit I/Q pairs. In addition to the word length flexibility, the AD9856 operates in two “input timing” modes, burst or continuous, programmable via the serial port. The input sample rate for full word mode, when the third halfband filter is engaged, is given by: fIN = SYSCLK/4N where N is the CIC interpolation rate. The input sample rate for full word mode, when the third halfband filter is not engaged is given by: fIN = SYSCLK/2N CIC interpolation rate (2 ≤ N ≤ 63) where N is the CIC interpolation rate It should be obvious from these conditions that REFCLK and fW have an integer ratio relationship. It is of utmost importance that the user chooses a value of REFCLK, which will ensure that this integer ratio relationship is maintained. I/Q DATA SYNCHRONIZATION As mentioned above, the AD9856 accepts I/Q data pairs, twos complement numbering system, in three different word length modes. The full word mode accepts 12-bit parallel I and Q data. The half word mode accepts dual 6-bit I and Q data inputs to Figure 23 describes an alternate timing method for TxENABLE when the AD9856 is configured in full word, burst mode operation. The benefit of this timing is that the AD9856 will resynchronize the input sampling logic when the rising edge of TxENABLE is detected. The low time on TxENABLE is limited to one input sample period and must be low during the Q data period. The maximum high time on TxENABLE is unlimited. It should be clear that unlimited high time on TxENABLE results in the timing diagram of Figure 22. See Figure 26 for the ramifications of violating the TxENABLE low time constraint when operating in burst mode. –14– REV. B AD9856 Figure 24 describes the input timing for half word mode, burst input timing operation. Figure 25 describes the input timing for quarter word, burst input timing operation. In half word mode, data is input on the D<11:6> inputs. The D<5:0> inputs are unused in this mode and should be tied to DGND or DVDD. The AD9856 expects the data to be input in the following manner: I<11:6>,I<5:0>,Q<11:6>,Q<5:0>. Data is twos complement, the sign bit is D<11> in notation I<11:0>,Q<11:0>. In quarter word mode, data is input on the D<11:9> inputs. The D<8:0> inputs are unused in this mode and should be tied to DGND or DVDD. The AD9856 expects the data to be input in the following manner: I<11:9>, I<8:6>, I<5:3>, I<2:0>, Q<11:9>, Q<8:6>, Q<5:3>, Q<2:0>. Data is twos complement, the sign bit is D<11> in notation I<11:0>, Q<11:0>. The input sample rate for half word mode, when the third halfband filter is engaged, is given by: The input sample rate for quarter word mode, when the third half-band filter is engaged, is given by: fIN = SYSCLK/N fIN = SYSCLK/2N where N is the CIC interpolation rate. where N is the CIC interpolation rate. The input sample rate for half word mode, when the third halfband filter is not engaged is given by: Please note that Half-Band Filter #3 must be engaged when operating in quarter word mode. fIN = SYSCLK/N where N is the CIC interpolation rate. TxENABLE D(11:0) I0 Q0 I1 Q1 I2 Q2 INTERNAL I I0 I1 INTERNAL Q Q0 Q1 I3 Q3 I4 Q4 I2 I3 Q2 Q3 Figure 22. 12-Bit Input Mode, Classic Burst Timing TxENABLE D(11:0) I0 Q0 I1 Q1 I2 Q2 I3 Q3 I4 Q4 INTERNAL I I0 I1 I2 I3 INTERNAL Q Q0 Q1 Q2 Q3 Figure 23. 12-Bit Input Mode, Alternate TxENABLE Timing TxENABLE D(11:6) I0(11:6) I0(5:0) Q0(5:0) Q0(11:6) I1(11:6) I1(5:0) Q1(11:6) Q1(5:0) I2(11:6) I2(5:0) INTERNAL I I0 I1 INTERNAL Q Q0 Q1 Figure 24. 6-Bit Input Mode, Burst Mode Timing TxENABLE D(11:9) I0(11:9) I0(8:6) I0(5:3) I0(2:0) Q0(11:9) Q0(8:6) Q0(5:3) Q0(2:0) I1(8:6) INTERNAL I I0 INTERNAL Q Q0 Figure 25. 3-Bit Input Mode, Burst Mode Timing REV. B I1(11:9) –15– AD9856 Figure 26 describes the end of burst timing and internal data assembly. It’s important to note that in burst mode operation, if the TxENABLE input is low for more than one input sample period, numerical zeros are internally generated and passed to the data path logic for signal processing. This is not valid for continuous mode operation, as will be discussed later. greater than one input sample period. Please note that the timing diagram of Figures 27 and 28 detail INCORRECT timing relationships between TxENABLE and data. They are only presented to indicate that the AD9856 will resynchronize properly after detecting a rising edge of TxENABLE. It should also be noted that the significant difference between burst and continuous mode operation is that in addition to synchronizing the data, TxENABLE is used to indicate whether an I or Q input is being sampled. To ensure proper operation, the minimum time between falling and rising edges of TxENABLE is one input sample period. Continuous Mode Input Timing The AD9856 is configured for continuous mode input timing by writing the Continuous Mode bit true (Logic 1). The Continuous Mode bit is in register address 01h, Bit 6. The AD9856 must be configured for full word input format when operating in continuous mode input timing. The input data rate equations described above, for full word mode, apply for continuous mode. Figure 23, which is the alternate burst mode timing diagram, is also the continuous mode input timing. Figures 27 and 28 describe what the internal data assembler will present to the signal processing logic when the TxENABLE input is held static for Do not engage continuous mode simultaneously with the REFCLK multiplier function. This has been found to corrupt the CIC interpolating filter, forcing unrecoverable mathematical overflow that can only be resolved by issuing a RESET command. The problem is due to the PLL failing to be locked to the reference clock while nonzero data is being clocked into the interpolation stages from the data inputs. The recommended sequency is to first engage the REFCLK multiplier function (allowing at least 1 ms for loop stabilization) and then engage continuous mode via software. TxENABLE IN D(11:0) QN I0 Q0 I1 Q1 INTERNAL I IN–2 IN–1 IN LOGIC 0 I0 INTERNAL Q QN–2 QN–1 QN LOGIC 0 Q0 Figure 26. Burst Mode Input Timing—End of Burst TxENABLE D(11:0) QN INTERNAL I IN–1 INTERNAL Q QN–1 IN+1 QN+1 IN+2 IN QN+2 IN+3 IN+1 QN+3 IN+4 IN+2 QN QN+4 IN+5 IN+3 IN+4 QN+3 QN+4 Figure 27. Continuous Mode Input Timing—TxENABLE Static High TxENABLE D(11:0) IN QN INTERNAL I IN–1 INTERNAL Q QN–1 IN+1 QN+1 IN+2 QN+2 IN+3 QN+3 IN+4 IN QN QN+1 QN+4 IN+3 QN+2 QN+3 Figure 28. Continuous Mode Input Timing—TxENABLE Static Low –16– REV. B AD9856 Before presenting a detailed description of the HBFs, recall that the input data stream is representative of complex data; i.e., two input samples are required to produce one I/Q data pair. The I/Q sample rate is one-half the input data rate. The I/Q sample rate (the rate at which I or Q samples are presented to the input of the first half-band filter) will be referred to as fIQ. Since the AD9856 is a quadrature modulator, fIQ represents the baseband of the internal I/Q sample pairs. It should be emphasized here that fIQ is not the same as the baseband of the user’s symbol rate data, which must be upsampled before presentation to the AD9856 (as will be explained later). The I/Q sample rate (fIQ) puts a limit on the minimum bandwidth necessary to transmit the fIQ spectrum. This is the familiar Nyquist limit and is equal to onehalf fIQ, which hereafter will be referred to as fNYQ . data where the value of α is such that 0 ≤ α ≤ 1. A value of 0 causes the data bandwidth to correspond to the Nyquist bandwidth. A value of 1 causes the data bandwidth to be extended to twice the Nyquist bandwidth. Thus, with 2× oversampling of the baseband data and α = 1, the Nyquist bandwidth of the data will correspond with the I/Q Nyquist bandwidth. As stated earlier, this results in problems near the upper edge of the data bandwidth due to the frequency response of HBF 1 and 2. 10 0 –10 –20 MAGNITUDE – dB HALF-BAND FILTERS (HBFs) HBF 1 is a 47-tap filter that provides a factor-of-two increase in sampling rate. HBF 2 is a 15-tap filter offering an additional factor-of-two increase in sampling rate. Together, HBF 1 and 2 provide a factor-of-four increase in the sampling rate (4 × fIQ or 8 × fNYQ). Their combined insertion loss is a mere 0.01 dB, so virtually no loss of signal level occurs through the first two HBFs. HBF 3 is an 11-tap filter and, if selected, increases the sampling rate by an additional factor of two. Thus, the output sample rate of HBF 3 is 8 × fIQ or 16 × fNYQ . HBF 3 exhibits 0.03 dB of signal level loss. As such, the loss in signal level through all three HBFs is only 0.04 dB and may be ignored for all practical purposes. –50 –60 –80 –90 –100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW 4.0 a. Half-Band 1 and 2 Frequency Response 1 0 MAGNITUDE – dB –1 In addition to knowledge of the insertion loss and phase response of the HBFs, some knowledge of the frequency response of the HBFs is useful as well. The combined frequency response of HBF 1 and 2 is shown in Figure 29. REV. B –40 –70 In relation to phase response, all three HBFs are linear phase filters. As such, virtually no phase distortion is introduced within the passband of the filters. This is an important feature as phase distortion is generally intolerable in a data transmission system. The usable bandwidth of the filter chain puts a limit on the maximum data rate that can be propagated through the AD9856. A look at the passband detail of the HBF 1 and 2 response indicates that in order to maintain an amplitude error of no more than 1 dB, we are restricted to signals having a bandwidth of no more than about 90% of fNYQ . Thus, in order to keep the bandwidth of the data in the flat portion of the filter passband, the user must oversample the baseband data by at least a factor of two prior to presenting it to the AD9856. Note that without oversampling, the Nyquist bandwidth of the baseband data corresponds to the fNYQ. As such, the upper end of the data bandwidth will suffer 6 dB or more of attenuation due to the frequency response of HBF 1 and 2. Furthermore, if the baseband data applied to the AD9856 has been pulse shaped there is an additional concern. Typically, pulse shaping is applied to the baseband data via a filter having a raised cosine response. In such cases, an α value is used to modify the bandwidth of the –30 –2 –3 –4 –5 –6 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.1 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW 1.0 b. Passband Detail Figure 29. Combined Frequency Response of HBF 1 and 2 To reiterate, the user must oversample their baseband data by at least a factor of two (2). In addition, there is a further restriction on pulse shaping. That is, the maximum value of α that can be implemented is 0.8. This is because the data bandwidth becomes: 1/2(1 + α) fNYQ = 0.9 fNYQ, which puts the data bandwidth at the extreme edge of the flat portion of the filter response. If a particular application requires an α value between 0.8 and 1, then the user must oversample the baseband data by at least a factor of four (4). –17– AD9856 In addition to the ability to provide a change in sample rate between input and output, a CIC filter also has an intrinsic lowpass frequency response characteristic. The frequency response of a CIC filter is dependent on three factors: In applications requiring both a low data rate and a high output sample rate, a third HBF is available (HBF 3). Selection of HBF 3 offers an upsampling ratio of eight (8) instead of four (4). The combined frequency response of HBF 1, 2 and 3 is shown in Figure 30. Comparing the passband detail of HBF 1 and 2 with the passband detail of HBF 1, 2 and 3, it becomes evident that HBF 3 has virtually no impact on frequency response from 0 to 1 (where 1 corresponds to fNYQ). 1. The rate change ratio, R. 2. The order of the filter, N. 3. The number of unit delays per stage, M. It can be shown that the system function, H(z), of a CIC filter is given by: 10 0 1– z – RM H (z ) = 1– z –1 –10 MAGNITUDE – dB –20 N RM –1 = ∑ z –k k= 0 N –30 The form on the far right has the advantage of providing a result for z = 1 (corresponding to zero frequency or dc). The alternate form yields an indeterminate form (0/0) for z = 1, but is otherwise identical. The only variable parameter for the AD9856’s CIC filter is R. M and N are fixed at 1 and 4, respectively. Thus, the CIC system function for the AD9856 simplifies to: –40 –50 –60 –70 –80 –90 4 –100 0 2 3 4 5 6 7 1 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW 1– z – R R –1 – k H (z ) = = ∑ z 1– z –1 k=0 8 a. Half-Band 1, 2 and 3 Frequency Response The transfer function is given by: 1 4 1– e – j (2 π fR ) R –1 – j (2 π fk) H( f ) = = ∑ e 1– e – j (2 π f ) k=0 0 –1 MAGNITUDE – dB 4 4 The frequency response in this form is such that f is scaled to the output sample rate of the CIC filter. That is, f = 1 corresponds to the frequency of the output sample rate of the CIC filter. H(f/R) will yield the frequency response with respect to the input sample of the CIC filter. Figure 31 reveals the CIC frequency response and passband detail for R = 2 and R = 63 and with HBF 3 bypassed. Figure 32 is similar but with HBF 3 selected. Note the flatter passband response when HBF 3 is employed. –2 –3 –4 –5 –6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW b. Passband Detail Figure 30. Combined Frequency Response of HBF 1, 2 and 3 CASCADED INTEGRATOR-COMB (CIC) FILTER A CIC filter is unlike a typical FIR filter in that it offers the flexibility to handle differing input and output sample rates (only in integer ratios, however). In the purest sense, a CIC filter can provide either an increase or a decrease in sample rate at the output relative to the input, depending on the architecture. If the integration stage precedes the comb stage, the CIC filter provides sample rate reduction (decimation). When the comb stage precedes the integrator stage the CIC filter provides an increase in sample rate (interpolation). In the AD9856, the CIC filter is configured as an interpolator. In fact, it is a programmable interpolator and provides a sample rate increase, R, such that 2 ≤ R ≤ 63. As with the case of the HBFs, consideration must be given to the frequency dependent attenuation that the CIC filter introduces over the frequency range of the data to be transmitted. Note that the CIC frequency response plots have fNYQ as their reference frequency; i.e., unity (1) on the frequency scale corresponds to fNYQ. If the incoming data that is applied to the AD9856 is oversampled by a factor of 2 (as required), then the Nyquist bandwidth of the applied data is one-half fNYQ on the CIC frequency response plots. A look at the 0.5 point on the passband detail plots reveals a worst case attenuation of about 0.25 dB (HBF 3 bypassed, R = 63). This, of course, assumes pulse shaped data with α = 0 (minimum bandwidth scenario). When a value of α = 1 is used, the bandwidth of the data corresponds to fNYQ (the point, 1.0 on the CIC frequency scale). Thus, the worst case attenuation for α = 1 is about 0.9 dB. –18– REV. B AD9856 0 0 –10 –0.5 –20 –30 –1.0 –50 MAGNITUDE – dB MAGNITUDE – dB –40 –60 –70 –80 –90 –100 –110 –1.5 –2.0 –2.5 –3.0 –120 –130 –3.5 –140 –150 0 –4.0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW a. CIC Frequency Response (R = 2, HBF 3 Bypass) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW c. Passband Detail (R = 2, HBF 3 Bypass) 0 0 –10 –20 –0.5 –30 –1.0 –50 MAGNITUDE – dB MAGNITUDE – dB –40 –60 –70 –80 –90 –100 –110 –1.5 –2.0 –2.5 –3.0 –120 –130 –3.5 –140 –150 0 –4.0 36 72 108 144 180 216 252 288 324 360 396 432 468 504 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW b. CIC Frequency Response (R = 63, HBF 3 Bypass) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW d. Passband Detail (R = 63, HBF 3 Bypass) Figure 31. CIC Filter Frequency Response (HB 3 Bypassed and R = 2, 63) The degree of the impact of the attenuation introduced by the CIC filter over the Nyquist bandwidth of the data is application specific. The user must decide how much attenuation is acceptable. If less attenuation is desired, then additional oversampling of the baseband data must be employed. Alternatively, the user can precompensate the baseband data before presenting it to the AD9856. That is, if the data is precompensated through a filter that has a frequency response characteristic, which is the inverse of the CIC filter response, then the overall system response can be nearly perfectly flattened over the bandwidth of the data. Another issue to consider with the CIC filters is insertion loss. Unfortunately, CIC insertion loss is not fixed but is a function of R, M and N. Since M and N are fixed for the AD9856, the CIC insertion loss is a function of R, only. Interpolation rates that are an integer power-of-2 result in no insertion loss. However, all noninteger power-of-2 interpolation rates result in a specific amount of insertion loss. To help overcome the insertion loss problem, the AD9856 provides the user a means to boost the gain through the CIC REV. B stage by a factor of 2 (via the CIC Gain bit—see the AD9856 control register description). The reason for this feature is to allow the user to take advantage of the full dynamic range of the DAC, thus maximizing the signal-to-noise ratio (SNR) at the output of the DAC stage. Obviously, it is desirable to operate the DAC over its full-scale range in order to minimize the inherent quantization effects associated with a DAC. Any significant loss through the CIC stage will be reflected at the DAC output as a reduction in SNR. The degradation in SNR can be overcome by boosting the CIC output level. Table II (The CIC Interpolation Filter Insertion Loss Table) tabulates insertion loss as a function of R. The values are provided in linear and decibel form, both with and without the factor-of-two gain employed. A word of caution: When the CIC Gain bit is active, the user must ensure that the data supplied to the AD9856 is scaled down to yield an overall gain of unity (1) through the CIC filter stage. Gains in excess of unity are likely to cause overflow errors in the data path, thereby compromising the validity of the analog output signal. –19– AD9856 0 0 –10 –0.5 –20 –30 –1.0 MAGNITUDE – dB MAGNITUDE – dB –40 –50 –60 –70 –80 –90 –100 –110 –1.5 –2.0 –2.5 –3.0 –120 –130 –3.5 –140 –150 –4.0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW c. Passband Detail (R = 2, HBF 3 Selected) a. CIC Frequency Response (R = 2, HBF 3 Selected) 0 0 –10 –0.5 –20 –30 –1.0 MAGNITUDE – dB MAGNITUDE – dB –40 –50 –60 –70 –80 –90 –100 –110 –1.5 –2.0 –2.5 –3.0 –120 –130 –3.5 –140 –4.0 –150 0 72 144 216 288 360 432 504 576 648 720 792 864 936 1008 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW d. Passband Detail (R = 63, HBF 3 Active) b. CIC Frequency Response (R = 63, HBF 3 Active) Figure 32. CIC Filter Frequency Response (HB 3 Selected and R = 2, 63) DIGITAL QUADRATURE MODULATOR Following the CIC filter stage the I and Q data (which have been processed independently up to this point) are mixed in the modulator stage to produce a digital modulated carrier. The carrier frequency is selected by programming the direct digital synthesizer (see the DDS section) with the appropriate 32-bit tuning word via the AD9856 control registers. The DDS simultaneously generates a digital (sampled) sine and cosine wave at the programmed carrier frequency. The digital sine and cosine data is multiplied by the Q and I data, respectively, to create the quadrature components of the original data upconverted to the carrier frequency. The quadrature components are digitally summed and passed on to the subsequent stages. The key point is that the modulation is done digitally, which eliminates the phase and gain imbalance and crosstalk issues typically associated with analog modulators. Note that the modulated “signal” is actually a number stream sampled at the rate of SYSCLK, which is the same rate at which the DAC is clocked (see Figure 21, the AD9856 block diagram). It should be pointed out that the architecture of the quadrature modulator results in a 3 dB loss of signal level. To visualize this, assume that both the I data and Q data are fixed at the maximum possible digital value, x. Then the output of the modulator, y, is: y = x × cos(ω) + x × sin(ω) = x × [cos(ω) + sin(ω)] From this equation it can be shown that y assumes a maximum value of x√2 (a gain of 3 dB). However, if the same number of bits were used to represent the y values, as is used to represent the x values, an overflow would occur. To prevent this possibility, an effective “divide-by-two” is implemented on the y values, which reduces the maximum value of y by a factor of two. Since division by two results in a 6 dB loss, the modulator yields an overall loss of 3 dB (3 dB – 6 dB = –3 dB, or 3 dB of loss). –20– REV. B AD9856 Table II. CIC Interpolation Filter Insertion Loss Table Interpolation Rate 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 REV. B Default Gain (Linear) (dB) (Linear) 2ⴛ Gain (dB) 1.0000 0.8438 1.0000 0.9766 0.8438 0.6699 1.0000 0.7119 0.9766 0.6499 0.8438 0.5364 0.6699 0.8240 1.0000 0.5997 0.7119 0.8373 0.9766 0.5652 0.6499 0.7426 0.8438 0.9537 0.5364 0.6007 0.6699 0.7443 0.8240 0.9091 1.0000 0.5484 0.5997 0.6542 0.7119 0.7729 0.8373 0.9051 0.9766 0.5258 0.5652 0.6066 0.6499 0.6952 0.7426 0.7921 0.8438 0.8976 0.9537 0.5060 0.5364 0.5679 0.6007 0.6347 0.6699 0.7065 0.7443 0.7835 0.8240 0.8659 0.9091 0.9539 0.000 –1.476 0.000 –0.206 –1.476 –3.480 0.000 –2.951 –0.206 –3.743 –1.476 –5.411 –3.480 –1.682 0.000 –4.441 –2.951 –1.543 –0.206 –4.955 –3.743 –2.585 –1.476 –0.412 –5.411 –4.427 –3.480 –2.565 –1.682 –0.827 0.000 –5.219 –4.441 –3.686 –2.951 –2.237 –1.543 –0.866 –0.206 –5.583 –4.955 –4.342 –3.743 –3.157 –2.585 –2.024 –1.476 –0.938 –0.412 –5.917 –5.411 –4.914 –4.427 –3.949 –3.480 –3.018 –2.565 –2.120 –1.682 –1.251 –0.827 –0.410 2.0000 1.6875 2.0000 1.9531 1.6875 1.3398 2.0000 1.4238 1.9531 1.2998 1.6875 1.0728 1.3398 1.6479 2.0000 1.1995 1.4238 1.6746 1.9531 1.1305 1.2998 1.4852 1.6875 1.9073 1.0728 1.2014 1.3398 1.4886 1.6479 1.8183 2.0000 1.0967 1.1995 1.3084 1.4238 1.5458 1.6746 1.8103 1.9531 1.0517 1.1305 1.2132 1.2998 1.3905 1.4852 1.5842 1.6875 1.7952 1.9073 1.0120 1.0728 1.1358 1.2014 1.2693 1.3398 1.4129 1.4886 1.5669 1.6479 1.7317 1.8183 1.9077 6.021 4.545 6.021 5.815 4.545 2.541 6.021 3.069 5.815 2.278 4.545 0.610 2.541 4.339 6.021 1.580 3.069 4.478 5.815 1.065 2.278 3.436 4.545 5.609 0.610 1.593 2.541 3.455 4.339 5.193 6.021 0.802 1.580 2.335 3.069 3.783 4.478 5.155 5.815 0.437 1.065 1.679 2.278 2.863 3.436 3.996 4.545 5.082 5.609 0.104 0.610 1.106 1.593 2.072 2.541 3.002 3.455 3.901 4.339 4.770 5.193 5.610 –21– AD9856 INVERSE SINC FILTER (ISF) The AD9856 is almost entirely a digital device. The input “signal” is made up of a time series of digital data words. These data words propagate through the device as numbers. Ultimately, this number stream must be converted to an analog signal. To this end, the AD9856 incorporates an integrated DAC. The output waveform of the DAC is the familiar “staircase” pattern typical of a signal that is sampled and quantized. The staircase pattern is a result of the finite time that the DAC holds a quantized level until the next sampling instant. This is known as a zero-order hold function. The spectrum of the zero-order hold function is the familiar SIN(x)/x, or SINC, envelope. The series of digital data words presented at the input of the DAC represent an impulse stream. It is the spectrum of this impulse stream, which is the desired output signal. Due to the zero-order hold effect of the DAC, however, the output spectrum is the product of the zero-order hold spectrum (the SINC envelope) and the Fourier transform of the impulse stream. Thus, there is an intrinsic distortion in the output spectrum, which follows the SINC response. The SINC response is deterministic and totally predictable. Thus, it is possible to pre-distort the input data stream in a manner, which compensates for the SINC envelope distortion. This can be accomplished by means of an ISF. The ISF incorporated on the AD9856 is a 17-tap, linear phase FIR filter. Its frequency response characteristic is the inverse of the SINC envelope. Data sent through the ISF is altered in such a way as to correct for the SINC envelope distortion. It should be noted, however, that the ISF is sampled at the same rate as the DAC. Thus, the effective range of the SINC envelope compensation only extends to the Nyquist frequency (1/2 of the DAC sample rate). Figure 33 is a plot that shows the effectiveness of the ISF in correcting for the SINC distortion. The plot includes a graph of the SINC envelope, the ISF response and the SYSTEM response (which is the product of the SINC and ISF responses). It should be mentioned at this point that the ISF exhibits an insertion loss of 3.1 dB. Thus, signal levels at the output of the AD9856 with the ISF bypassed are 3.1 dB higher than with the ISF engaged. However, for modulated output signals, which have a relatively wide bandwidth, the benefits of the SINC 4.0 3.5 3.0 2.5 2.0 dB 1.5 1.0 SYSTEM The direct digital synthesizer (DDS) block generates the sine/ cosine carrier reference signals that are digitally modulated by the I/Q data paths. The DDS function is frequency tuned via the serial control port with a 32-bit tuning word. This allows the AD9856’s output carrier frequency to be very precisely tuned while still providing output frequency agility. The equation relating output frequency of the AD9856 digital modulator to the frequency tuning word (FTWORD) and the system clock (SYSCLK) is given as: A OUT = (FTWORD × SYSCLK)/232 Where: A OUT and SYSCLK frequencies are in Hz and FTWORD is a decimal number from 0 to 4,294,967,296 (231) Example: Find the FTWORD for AOUT = 41 MHz and SYSCLK = 122.88 MHz If AOUT = 41 MHz and SYSCLK = 122.88 MHz, then: FTWORD = 556AAAAB hex Loading 556AAAABh into control bus registers 02h–05h (for Profile 1) programs the AD9856 for AOUT = 41 MHz, given a SYSCLK frequency of 122.88 MHz. D/A CONVERTER A 12-bit digital-to-analog converter (DAC) is used to convert the digitally processed waveform into an analog signal. The worst case spurious signals due to the DAC are the harmonics of the fundamental signal and their aliases (please see the AD9851 Complete-DDS data sheet for a detailed explanation of aliased images). The wideband 12-bit DAC in the AD9856 maintains spurious-free dynamic range (SFDR) performance of –60 dBc up to AOUT = 42 MHz and –55 dBc up to AOUT = 65 MHz. The conversion process will produce aliased components of the fundamental signal at n × SYSCLK ± FCARRIER (n = 1, 2, 3). These are typically filtered with an external RLC filter at the DAC output. It is important for this analog filter to have a sufficiently flat gain and linear phase response across the bandwidth of interest so as to avoid modulation impairments. A relatively inexpensive 7th order elliptical low-pass filter is sufficient to suppress the aliased components for HFC network applications. RSET = 39.936/IOUT For example, if a full-scale output current of 20 mA is desired, then RSET = (39.936/0.02), or approximately 2 kΩ. Every doubling of the RSET value will halve the output current. Maximum output current is specified as 20 mA. SINC –2.0 –2.5 –3.0 –3.5 –4.0 DIRECT DIGITAL SYNTHESIZER FUNCTION The AD9856 provides true and complement current outputs on pins 30 and 29 respectively. The full-scale output current is set by the RSET resistor at Pin 25. The value of RSET for a particular IOUT is determined using the following equation: ISF 0.5 0 –0.5 –1.0 –1.5 compensation usually outweigh the 3 dB loss in output level. The decision of whether or not to use the ISF is an application specific system design issue. 0 0.1 0.2 0.3 0.4 FREQUENCY NORMALIZED TO SAMPLE RATE Figure 33. Inverse SINC Filter Response 0.5 The full-scale output current range of the AD9856 is 5 mA– 20 mA. Full-scale output currents outside of this range will degrade SFDR performance. SFDR is also slightly affected by output matching, that is, the two outputs should be terminated equally for best SFDR performance. –22– REV. B AD9856 The output load should be located as close as possible to the AD9856 package to minimize stray capacitance and inductance. The load may be a simple resistor to ground, an op amp current-to-voltage converter, or a transformer-coupled circuit. It is best not to attempt to directly drive highly reactive loads (such as an LC filter). Driving an LC filter without a transformer requires that the filter be doubly terminated for best performance, that is, the filter input and output should both be resistively terminated with the appropriate values. The parallel combination of the two terminations will determine the load that the AD9856 will see for signals within the filter passband. For example, a 50 Ω terminated input/output low-pass filter will look like a 25 Ω load to the AD9856. The output compliance voltage of the AD9856 is –0.5 V to +1.5 V. Any signal developed at the DAC output should not exceed +1.5 V, otherwise, signal distortion will result. Furthermore, the signal may extend below ground as much as 0.5 V without damage or signal distortion. The use of a transformer with a grounded center-tap for common-mode rejection results in signals at the AD9856 DAC output pins that are symmetrical about ground. As previously mentioned, by differentially combining the two signals the user can provide some degree of common mode signal rejection. A differential combiner might consist of a transformer or an op amp. The object is to combine or amplify only the difference between two signals and to reject any common, usually undesirable, characteristic, such as 60 Hz hum or “clock feedthrough” that is equally present on both input signals. The AD9856 true and complement outputs can be differentially combined using a broadband 1:1 transformer with a grounded, center-tapped primary to perform differential combining of the two DAC outputs. REFERENCE CLOCK MULTIPLIER Due to the fact that the AD9856 is a DDS-based modulator, a relatively high frequency system clock is required. For DDS applications, the carrier is typically limited to about 40% of SYSCLK. For a 65 MHz carrier, the system clock required is above 160 MHz. To avoid the cost associated with these high frequency references, and the noise coupling issues associated with operating a high frequency clock on a PC board, the AD9856 provides an on-chip programmable clock multiplier (REFCLK Multiplier). The available clock multiplier range is from 4× to 20×, in integer steps. With the REFCLK Multiplier enabled, the input reference clock required for the AD9856 can be kept in the 10 MHz to 50 MHz range for 200 MHz system operation, which results in cost and system implementation savings. The REFCLK Multiplier function maintains clock integrity as evidenced by the AD9856’s system phase noise characteristics of –105 dBc/Hz (AOUT = 40 MHz, REFCLK Multiplier = 6, Offset = 1 kHz) and virtually no clock-related spurii in the output spectrum. External loop filter components consisting of a series resistor (1.3 kΩ) and capacitor (0.01 µF) provide the compensation zero for the REFCLK Multiplier PLL loop. The overall loop performance has been optimized for these component values. REV. B THROUGHPUT AND LATENCY Data latency through the AD9856 is easiest to describe in terms of SYSCLK clock cycles. Latency is a function of the AD9856 configuration; primarily affected by the CIC interpolation rate and whether the third half-band filter is engaged. When the third half-band filter is engaged the AD9856 latency is given by: 126 N + 37 SYSCLK clock cycles where N is the CIC interpolation rate. If the AD9856 is configured to bypass the third half-band filter, the latency is given by: 63 N + 37 SYSCLK clock cycles. These equations should be considered estimates as observed latency may be data dependent. The latency was calculated using the linear delay model for the FIR filters. In single tone mode, frequency hopping is accomplished via changing the PROFILE input pins. The time required to switch from one frequency to another is less than 50 SYSCLK cycles with the Inverse SINC Filter engaged. With the Inverse SINC Filter bypassed, the latency drops to less than 35 SYSCLK cycles. CONTROL INTERFACE The AD9856 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola 6905/11 SPI and Intel 8051 SSR protocols. The interface allows read/write access to all registers that configure the AD9856. Single or multiple byte transfers are supported as well as MSB first or LSB first transfer formats. The AD9856’s serial interface port can be configured as a single pin I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO). GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a communication cycle with the AD9856. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9856, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9856 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer (1–4), and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9856. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9856 and the system controller. Phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. Normally, using one communication cycle in a multibyte transfer is the preferred method. However, single byte communication cycles are useful to reduce CPU overhead when register access requires one byte only. Examples of this may be to write the AD9856 SLEEP bit, or an AD8320/AD8321 gain control byte. –23– AD9856 INSTRUCTION BYTE At the completion of any communication cycle, the AD9856 serial port controller expects the next 8 rising SCLK edges to be the instruction byte of the next communication cycle. The instruction byte contains the following information as shown below (see Table III): All data input to the AD9856 is registered on the rising edge of SCLK. All data is driven out of the AD9856 on the falling edge of SCLK. Table III. Instruction Byte Information Figures 34–37 are useful in understanding the general operation of the AD9856 Serial Port. MSB D6 D5 D4 D3 D2 D1 LSB R/W N1 N0 A4 A3 A2 A1 A0 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I7 I5 I6 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 34. Serial Port Writing Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I6 I7 I5 I4 I3 I2 I1 I0 DON'T CARE DO 7 SDO DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0 Figure 35. Three-Wire Serial Port Read Timing—Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 36. Serial Port Write Timing—Clock Stall High INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I7 I6 I5 I4 I3 I2 I1 I0 DO 7 DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0 Figure 37. Two-Wire Serial Port Read Timing—Clock Stall High –24– REV. B AD9856 CA ENABLE—Output Enable pin to the AD8320/AD8321. If using the AD9856 to control the AD8320/AD8321 Programmable Cable Driver Amplifier, connect this pin to the DATAEN input of the AD8320/AD8321. R/W–Bit 7 of the instruction byte determines whether a read or write data transfer will occur after the instruction byte write. Logic high indicates read operation. Logic zero indicates a write operation. N1, N0—Bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle of the communications cycle. The bit decodes are shown in Table IV. MSB/LSB TRANSFERS The AD9856 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by the REG0<6> bit. The default value of REG0<6> is low (MSB first). When REG0<6> is set active high, the AD9856 serial port is in LSB first format. The instruction byte must be written in the format indicated by REG0<6>. That is, if the AD9856 is in LSB first mode, the instruction byte must be written from least significant bit to most significant bit. Multibyte data transfers in MSB format can be completed by writing an instruction byte that includes the register address of the most significant byte. In MSB first mode, the serial port internal byte address generator decrements for each byte required of the multibyte communication cycle. Multibyte data transfers in LSB first format can be completed by writing an instruction byte that includes the register address of the least significant byte. In LSB first mode, the serial port internal byte Table IV. N1, N2 Decode Bits N1 N0 Description 0 0 1 1 0 1 0 1 Transfer 1 Byte Transfer 2 Bytes Transfer 3 Bytes Transfer 4 Bytes A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9856. address generator increments for each byte required of the multibyte communication cycle. SERIAL INTERFACE PORT PIN DESCRIPTION SCLK—Serial Clock. The serial clock pin is used to synchronize data to and from the AD9856 and to run the internal state machines. SCLK maximum frequency is 10 MHz. CS—Chip Select. Active low input that allows more than one device on the same serial communications lines. The SDO and SDIO pins will go to a high impedance state when this input is high. If driven high during any communications cycle, that cycle is suspended until CS is reactivated low. Chip Select can be tied low in systems that maintain control of SCLK. SDIO—Serial Data I/O. Data is always written into the AD9856 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of register address 0h. The default is logic zero, which configures the SDIO pin as bidirectional. SDO—Serial Data Out. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9856 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. SYNC I/O—Synchronizes the I/O port state machines without affecting the addressable registers contents. An active high input on the SYNC I/O pin causes the current communication cycle to abort. After SYNC I/O returns low (Logic 0) another communication cycle may begin, starting with the instruction byte write. CA CLK—Output clock pin to the AD8320/AD8321. If using the AD9856 to control the AD8320/AD8321 Programmable Cable Driver Amplifier, connect this pin to the CLK input of the AD8320/AD8321. CA DATA—Output data pin to the AD8320/AD8321. If using the AD9856 to control the AD8320/AD8321 Programmable Cable Driver Amplifier, connect this pin to the SDATA input of the AD8320/AD8321. REV. B NOTES ON SERIAL PORT OPERATION The AD9856 serial port configuration bits reside in Bits 6 and 7 of register address 0h. It is important to note that the configuration changes immediately upon writing to this register. For multibyte transfers, writing to this register may occur during the middle of a communication cycle. Care must be taken to compensate for this new configuration for the remainder of the current communication cycle. The AD9856 serial port controller address can roll from 19h to 0h for multibyte I/O operations if the MSB first mode is active. The serial port controller address can roll from 0h to 19h for multibyte I/O operations if the LSB first mode is active. The system must maintain synchronization with the AD9856 or the internal control logic will not be able to recognize further instructions. For example, if the system sends an instruction byte for a 2-byte write, then pulses the SCLK pin for a 3-byte write (24 additional SCLK rising edges), communication synchronization is lost. In this case, the first 16 SCLK rising edges after the instruction cycle will properly write the first two data bytes into the AD9856, but the next eight rising SCLK edges are interpreted as the next instruction byte, not the final byte of the previous communication cycle. In the case where synchronization is lost between the system and the AD9856, the SYNC I/O pin provides a means to reestablish synchronization without re-initializing the entire chip. The SYNC I/O pin enables the user to reset the AD9856 state machine to accept the next eight SCLK rising edges to be coincident with the instruction phase of a new communication cycle. By applying and removing a “high” signal to the SYNC I/O pin, the AD9856 is set to once again begin performing the communication cycle in synchronization with the system. Any information that had been written to the AD9856 registers during a valid communication cycle prior to loss of synchronization will remain intact. –25– AD9856 t SCLK t PRE CS t DSU t SCLKPWH t SCLKPWL SCLK t DHLD SDIO 1ST BIT SYMBOL t PRE t SCLK t DSU t SCLKPWH t SCLKPWL t DHLD 2ND BIT DEFINITION MIN CS SETUP TIME 30ns PERIOD OF SERIAL DATA CLOCK 100ns SERIAL DATA SETUP TIME 30ns SERIAL DATA CLOCK PULSEWIDTH HIGH 40ns SERIAL DATA CLOCK PULSEWIDTH LOW 40ns SERIAL DATA HOLD TIME 0ns Figure 38. Timing Diagram for Data Write to AD9856 CS SCLK SDIO 1ST BIT SDO 2ND BIT t DV SYMBOL t DV DEFINITION MAX DATA VALID TIME 30ns Figure 39. Timing Diagram for Read from AD9856 PROGRAMMING/WRITING THE AD8320/AD8321 CABLE DRIVER AMPLIFIER GAIN CONTROL Programming the Gain Control register of the AD8320/AD8321 programmable cable driver amplifier can be accomplished via the AD9856 serial port. Four 8-bit registers (one per profile) within the AD9856 store the gain value to be written to the AD8320/AD8321. The AD8320/AD8321 is written via three dedicated AD9856 output pins that are directly connected to the AD8320/AD8321’s serial input port. The transfer of data from the AD9856 to the AD8320/AD8321 requires 136 SYSCLK clock cycles and occurs upon detection of three conditions. Each is described below: 1. Power-up Reset—Upon initial power up, the AD9856 clears (Logic 0) the contents of control registers 07h, 0Dh, 13h, and 19h, which defines the lowest gain setting of the AD8320/ AD8321. Thus, the AD9856 writes all 0s out of the AD8320/ AD8321 serial interface. 2. Change in profile selection bits (PS1, PS0)—The AD9856 samples the PS1, PS0 input pins and writes to the AD8320/ AD8321 gain control register when a change in profile is determined. The data written to the AD8320/AD8321 comes from the AD9856 gain control register associated with the current profile. 3. Serial Port Write of AD9856 Registers that Contain AD8320/AD8321 Data—The AD9856 will write to the AD8320/AD8321 with data from the gain control register associated with the current profile whenever ANY AD9856 gain control register is updated. The user does not have to write the AD9856 in any particular order or be concerned with time between writes. If the AD9856 is currently writing to the AD8320/AD8321 while one of the four AD9856 gain control registers is being addressed, the AD9856 will immediately terminate the AD8320/AD8321 write sequence (without updating the AD8320/AD8321) and begin a new AD8320/AD8321 write sequence. –26– REV. B AD9856 VALID DATA WORD G1 MSB...LSB CA DATA t DS VALID DATA WORD G2 t CK t WH CA CLK t ES t EH 8 CLOCK CYCLES CA ENABLE GAIN TRANSFER G2 GAIN TRANSFER G1 SYMBOL t DS t DH t WH t CK t ES t EH DEFINITION MIN CA DATA SETUP TIME 6.5ns CA DATA HOLD TIME 2ns CA CLOCK PULSE HIGH 9ns CA CLOCK PERIOD 25ns CA ENABLE SETUP TIME 17ns CA ENABLE HOLD TIME 2.0ns Figure 40. Programmable Cable Driver Amplifier Output Control Interface Timing and its inherent 2× interpolation rate is applied. When this bit is Logic 1, the third half-band filter is bypassed and the 2× interpolation rate is negated. This allows users to input higher data rates—rates that may be too high for the minimum interpolation rate if all three half-band filters with their inherent 2× interpolation rate are engaged. The overall effect is to reduce minimum interpolation rate from 8× to 4×. UNDERSTANDING AND USING PIN SELECTABLE MODULATOR PROFILES The AD9856 Quadrature Digital Upconverter is capable of storing four preconfigured modulation modes called “profiles” that define the following: • • • • • Output Frequency—32 Bits Interpolation Rate—6 Bits Spectral Inversion Status—1 Bit Bypass 3rd Half-Band Filter—1 Bit Gain Control of AD8320/AD8321—8 Bits Output Frequency: This attribute consists of four 8-bit words loaded into four register addresses to form a 32-bit frequency tuning word (FTW) for each profile. The lowest register address corresponds to the least significant 8-bit word. Ascending addresses correspond to increasingly significant 8-bit words. The output frequency equation is given as: fOUT = (FTW × SYSCLK)/232. Interpolation Rate: Consists of a 6-bit word representing the allowed interpolation values from 2 to 63. Interpolation is the mechanism used to “up-sample” or multiply the input data rate such that it exactly matches that of the DDS sample rate (SYSCLK). This implies that the system clock must be an exact multiple of the symbol rate. This 6-bit word represents the 6 MSBs of the eight bits allocated for that address. The remaining two bits contain the spectral inversion status bit and half-band bypass bit. Spectral Inversion: Single bit that when at Logic 0 the default or “noninverted” output from the adder is sent to the following stages. A Logic 1 will cause the inverted output to be sent to the following stages. The noninverted output is described as I × Cos(ωt) – Q × Sin(ωt). The inverted output is described as I × Cos(ωt) + Q × Sin(ωt). This bit is located adjacent to the LSB at the same address as the interpolation rate (see above). Bypass Third Half-Band Filter: A single bit located in the LSB position of the same address as the interpolation rate. When this bit is Logic 0, the third half-band filter is engaged REV. B AD8320/AD8321 Gain Control: An 8-bit word that controls the gain of an AD8320/AD8321 Programmable Gain Amplifier connected to the AD9856 with the 3-bit SPI interface bus. Gain range is from –10 dB (00 hex) to +26 dB (FFhex). The gain is linear in V/V/LSB and follows the equation: AV = 0.316 + 0.077 × Code. Where “Code” is the decimal equivalent of the 8-bit gain word. Profile Selection: After profiles have been loaded into the appropriate registers, the user may select which profile to use with two input pins: PS0 and PS1, Pins 45 and 46. Profiles are selected according to the table below. Table V. Profile Select Matrix PS1 PS0 PROFILE 0 0 1 1 0 1 0 1 1 2 3 4 Except while in single tone mode, it is recommended that users suspend the TxENABLE function by bringing that pin to Logic 0 prior to changing from one profile to another and then reasserting TxENABLE afterwards. This assures that any dis-continuities resulting from register data transfer are not transmitted up or downstream. Furthermore, changing interpolation rates during a burst may create an unrecoverable digital overflow condition that would interrupt transmission of the current burst until a RESET and reloading procedure would be completed. –27– AD9856 POWER DISSIPATION CONSIDERATIONS The majority of the AD9856 power dissipation comes from digital switching currents. As such, power dissipation is highly dependent upon chip configuration. Obviously, the major contributor to switching current is the maximum clock rate at which the device is operated, but other factors can play a significant role. Factors such as the CIC interpolation rate, and whether the third half-band filter and inverse SINC filters are active, can affect the power dissipation of the device. It is important for the user to consider all of these factors when optimizing performance for power dissipation. For example, there are two ways to achieve a 6 MS/s transmission rate with the AD9856. The first method uses an fMAX of 192 MHz; the other method uses an fMAX of 144 MHz, which reduces power dissipation by nearly 25%. For the first method, the input data must be externally 4× upsampled. The AD9856 must be configured for a CIC interpolation rate of three while bypassing the 3rd half-band filter. This results in an I/Q input sample rate of 24 MHz which is further upsampled by a factor of 8 to 192 MHz. the power dissipation by nearly a factor of 10. In this case, both the REFCLK Multiplier function and the DAC, which use relatively little power, remain fully powered. The REFCLK Multiplier circuit is locked to the 16 MHz external reference clock but its output is driving a very small load, hence very little power dissipation. When the REFCLK Multiplier is reactivated, the acquisition time is small. In this power-reduction technique, the larger the REFCLK Multiplier factor, the larger the power savings. The AD9856 is specified for operation at +3.0 V ± 5% and the thermal impedance of the AD9856 in the 48-LQFP plastic package is 38°C/W. At 200 MHz operation, power dissipation is 1.5 W. This permits operation over the industrial temperature range without exceeding the maximum junction temperature of 150°C. To realize this quoted thermal impedance, all power and ground pins must be soldered down to a multilayer PCB with power and ground copper planes directly available at the package pins. Under worst case conditions, that is, with power supplies at +2.85 V and ambient temperatures of +85°C, device operation at 200 MHz is guaranteed for single tone mode only. For modulation mode at 200 MHz, +85°C operation, the minimum power supply voltage is +3.0 V. The second method requires an fMAX of 144 MHz with externally 2× upsampled input data. The AD9856 is configured for a CIC interpolation rate of 3 while bypassing the 3rd half-band filter. The input I/Q sample rate is 12 MHz, which is further upsampled by a factor of 12 MHz to 144 MHz. AD9856 EVALUATION BOARD For burst applications with relatively long nonbursting periods, the sleep bit is useful for saving power. When in sleep mode, power is reduced to below 6 mW. Consideration must be given to wake-up time, which will generally be in the 400 µs to 750 µs range. For those applications that cannot use the sleep bit due to this wake-up time, there is an alternate method of reducing power dissipation when not transmitting. By writing the “Bypass REFCLK Multiplier” bit active, the power is reduced by nearly the REFCLK Multiplier factor. For example, if the external reference clock is 16 MHz and REFCLK Multiplier is set to 10×, all clocks will divide down by a factor of 10 when the REFCLK Multiplier is bypassed. This effectively scales down An evaluation board is available for the AD9856 quadrature digital upconverter that facilitates bench and system analysis of the device. The AD9856/PCB contains the AD9856 device and Windows software that allows control of the device via the printer port of a PC. The DAC output is provided on a jack for spectral analysis. The AD9856/PCB circuit board provides a single-ended 65 MHz, 50 Ω, elliptical low-pass filter on the output of the DAC. There is also a provision for the user to implement the AD8320/ AD8321 programmable cable driver amplifier on the AD9856/ PCB evaluation board. The AD8320/AD8321 gain is programmed through the AD9856 via the menu driven control software. –28– REV. B AD9856 J6 J8 SYNC I/O PS0 J4 SCLK J7 PS1 SDIO J5 DVDD GND R7 50V J3 RST RESET W6 E8 P1 1 2 DVDD GND 3 4 5 6 DVDD GND CA DATA CA ENABLE PLL SUPPLY PLL FILTER PLL GND DUT AGND AD9856 IOUT IOUTB AGND AVDD DAC REF BYPASS DAC RSET TxENABLE D11 D10 DVDD DGND D9 D8 D7 D6 DVDD DGND D5 21 THRU 40 ARE GND W4 E9 R5 C16 1.3kV 0.01mF GND E12 R3 25V W9 E11 C18 33pF C19 22pF L1 120nH L2 100nH L3 100nH C11 100pF C12 82pF C13 56pF 65MHz LOW PASS FILTER +3.3V W11 E20 E21 E22 R6 1.3kV GND C7 0.1mF CADATA CACLK CAEN R11 10kV R10 10kV 1 LATCH SCLK SDIO CS 2 3 4 5 6 7 RST SYNC I/O U8 DVDD 1A 4B 1B 4A 1Y 4Y 2A 3B 2B 3A 2Y 3Y DGND U7 74HC574 OE VCC D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 GND CLOCK 14 +3.3V 13 12 11 RBE 10 9 8 20 +3.3V 19 18 17 16 15 14 13 12 11 J11 POWER DOWN CONTROL +12V J12 75V OUTPUT U4 AD8320/21 SDATA CLK DATEN GND VOCM PD +12V +12V +12V VOUT VCC1 VIN VREF VCC GND 1 GND 2 BYP GND 3 GND 4 GND 5 U6 74HC244A 2A4 2A3 2A2 2A1 1A4 1A3 1A2 1A1 GND 1G W3 +3.3V E24 GND +12V C26 0.1mF 0.1mF R9 62V J13 50V INPUT C28 0.1mF C23 0.1mF 1 VCC 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 2G 19 E16 E17 R8 10kV 20 +3.3V 3 5 7 9 12 14 16 18 W2 E18 E19 SCLK CS SYNC I/O RST PS0 PS1 +3.3V GND RBE SDO +12V 1 2 3 4 RBE 5 SDO 6 7 RBE GND +3.3V 20 19 18 17 16 15 14 13 12 11 RBE 17 15 13 11 8 6 4 2 10 E23 C21 0.1mF 1 2 3 4 5 6 7 8 9 10 DVDD AVDD GND U3 1G 1A 1Y 2G 2A 2Y GND VCC 4G 4A 4Y 3G 3A 3Y 74HC125A C3 C29 C24 C30 C31 C4 C27 C22 C25 C14 C8 C5 C20 C1 C2 10mF 0.1mF 0.1mF 0.1mF 0.1mF 10mF 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF 0.1mF 10mF 10mF GND Figure 41. AD9856/PCB Evaluation Board Electrical Schematic REV. B J10 AVDD C9 0.1mF 74HC132 1 2 3 4 5 6 7 8 9 10 C17 7pF C10 68pF E14 W7 E15 +3.3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AVDD W8 E13 J9 R4 50V NC = NO CONNECT P2 5 C15 0.1mF AVDD 20 +12V PODN DVDD J1 4 CAENB E10 R1 3.92V +3.3V CADAT 13 14 15 16 17 18 19 20 21 22 23 24 8 9 10 11 12 13 THRU 20 ARE NC W5 E4 E7 36 35 34 33 32 31 30 29 28 27 26 25 D4 D3 D2 D1 D0 NC NC DGND DVDD NC AGND BG REF BYPASS 7 1 2 3 4 5 6 7 8 9 10 11 12 RESET REFCLK PS1 PS0 DVDD DGND SYNC I/O SCLK SDIO SDO CS CA CLK TxENABLE 3 CACLK E6 2 E26 CS GND E1 48 47 46 45 44 43 42 41 40 39 38 37 J2 GND AVDD W1 E3 E2 E5 1 E25 W10 J14 SDO REFCLKIN P3 DVDD J15 –29– 14 13 12 11 10 9 8 +3.3V RBE SDIO +3.3V AD9856 a. Layer 1 (Top)—Signal Routing and Ground Plane c. Layer 3—DUT +V, +5 V and +12 V Power Plane EDIS MOTTOB .A.S.U NI EDAM C .VER 6589DA b. Layer 2—Ground Plane d. Layer 4 (Bottom)—Signal Routing Figure 42. PCB Layout Patterns for Four-Layer AD9856-PCB Evaluation Board –30– REV. B AD9856 ENABLE AND GAIN CONTROL BUS AD9856 QUADRATURE DIGITAL UPCONVERTER AD8320/21 75V LP FILTER 75V 75V 8-20MHz REF CLOCK IN PROGRAMMABLE CABLE DRIVER AMPLIFIER UPSTREAM TO DOWNSTREAM DEMODULATOR DIRECT CONTROL LINES DIPLEXER DATA IN TO 75V CABLE PLANT CONTROL BUS CIU CONTROL PROCESSOR Figure 43. Basic Implementation of AD9856 Digital Modulator and AD8320/AD8321 Programmable Cable Driver Amplifier in 5 MHz–65 MHz HFC Return-Path Application VDD VDD VDD DIGITAL OUT DIGITAL IN IOUT IOUTB Figure 44. Equivalent I/O Circuits REV. B –31– AD9856 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 0.354 (9.00) BSC 0.057 (1.45) 0.053 (1.35) 0.276 (7.0) BSC 37 36 48 1 SEATING PLANE 0.276 0.354 (7.0) (9.00) BSC BSC TOP VIEW (PINS DOWN) 08 – 78 08 MIN 0.007 (0.18) 0.004 (0.09) 12 13 0.019 (0.5) BSC 25 24 0.011 (0.27) 0.006 (0.17) PRINTED IN U.S.A. 0.006 (0.15) 0.002 (0.05) C3476a–0–9/99 48-Lead Quad Flatpack IC Package (LQFP) (ST-48) –32– REV. B