BB ADS7811

®
ADS7811
ADS
781
1
16-Bit 250kHz Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● 250kHz SAMPLING RATE
● COMPLETE WITH S/H, REF, CLOCK, ETC.
● 96dB min SFDR WITH 100kHz INPUT
The ADS7811 is a complete 16-bit sampling analogto-digital (A/D) converter featuring excellent AC
performance and a 250kHz throughput rate. The design includes a 16-bit capacitor-based SAR A/D
converter with an inherent sample and hold (S/H), a
precision reference, and an internal clock. Spuriousfree dynamic range with a 100kHz full-scale sinewave
input is typically greater than 100dB. The ±2.5V input
range allows development of precision systems using
only ±5V supplies. The converter is available in a
28-lead SOIC package specified for operation over
the industrial –25°C to +85°C temperature range.
● 84dB min SINAD
● ±2.5V INPUT RANGE
● 28-LEAD SOIC
APPLICATIONS
● WIRELESS BASE STATIONS
● SPECTRUM ANALYSIS
● IMAGING SYSTEMS
● DATA ACQUISITION
R/C
Clock
Successive Approximation Register and Control Logic
CS
BUSY
CDAC
Output
±2.5V Input
Latches
and
Comparator
Three
Parallel
Data
Bus
State
Drivers
Buffer
5kΩ
REF Out/In
Internal
+2.5V Ref
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
©
1997 Burr-Brown Corporation
PDS-1300A
1
ADS7811
Printed in U.S.A. November, 1997
SPECIFICATIONS
At TA = –25°C to +85°C, fS = 250kHz, +VS = +5V, and –VS = –5V, using internal reference, unless otherwise specified.
ADS7811U
PARAMETER
CONDITIONS
MIN
TYP
RESOLUTION
ANALOG INPUT
Voltage Range
Impedance
Capacitance
DC ACCURACY
Integral Linearity Error
No Missing Codes
Transition Noise(2)
Full Scale Error(3)
Full Scale Error Drift
Full Scale Error(3)
Full Scale Error Drift
Bipolar Zero Error
Bipolar Zero Error Drift
Power Supply Sensitivity
AC ACCURACY
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
Signal-to-Noise
Usable Bandwidth(5)
Aperture Delay
REFERENCE
Internal Reference Voltage
Internal Reference Source Current
Internal Reference Drift
External Reference Voltage Range
External Reference Current Drain
Acquire and Convert
V
MΩ
pF
4.0
µs
kHz
±4
LSB(1)
Bits
LSB
%
ppm/°C
%
ppm/°C
mV
ppm/°C
LSB
15
0.8
External 2.5000V Reference
External 2.5000V Reference
±7
±0.2
2
+VS ±5%, –VS ±5%
±2
±6
fIN = 100kHz
fIN = 100kHz
fIN = 100kHz
–60dB Input
fIN = 100kHz
96
84
84
2.48
100
–98
87
28
87
1
40
2.5
1
15
2.5
VREF = +2.5V
–0.3
+2.8
Output Capacitance
Bits
250
DIGITAL INPUTS
Logic Levels
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Data Coding
VOL
VOH
Leakage Current
UNITS
16
±2.5V
100
30
After Input Capacitor is Charged
THROUGHPUT SPEED
Conversion Cycle
Throughput Rate
MAX
±0.5
±10
±16
–96
2.52
dB(4)
dB
dB
dB
dB
MHz
ns
100
V
µA
ppm/°C
V
µA
+0.8
+VS +0.3V
±10
±10
V
V
µA
µA
+0.4
±5
V
V
µA
15
pF
83
83
ns
ns
+5.25
–4.75
250
V
V
mA
mA
mW
+85
+125
°C
°C
Parallel 16 bits
Binary Two’s Complement
ISINK = 1.6mA
ISOURCE = 200µA
High-Z State,
VOUT = 0V to VDIG
High-Z State
+4
DIGITAL TIMING
Bus Access Time
Bus Relinquish Time
POWER SUPPLIES
+VS
–VS
+IS
–IS
Power Dissipation
+4.75
–5.25
TEMPERATURE RANGE
Specified Performance
Storage
–25
–55
+5
–5
+30
–10
200
NOTES: (1) LSB means Least Significant Bit. For the 16-bit, ±2.5V input ADS7811, one LSB is 76µV. (2) Typical rms noise at worst case transitions and
temperatures. (3) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided by the transition
voltage (not divided by the full-scale range) and includes the effect of offset error. (4) All specifications in dB are referred to a full-scale ±2.5V input. (5) Usable
Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy.
®
ADS7811
2
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDERING INFORMATION
Analog Inputs: VIN .............................................. –VS – 0.3V to +VS + 0.3V
REF ................................................... – 0.3V to +VS + 0.3V
CAP ............................................... Indefinite Short to GND
Momentary Short to +VS
+VS ......................................................................................................... 7V
–VS ...................................................................................................... –7V
Digital Inputs .............................................................. –0.3V to +VS + 0.3V
Maximum Junction Temperature ................................................... +165°C
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ................................................ +300°C
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
ADS7811U
28-Pin SOIC
217
TEMPERATURE
RANGE
–25°C to +85°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
3
ADS7811
PIN #
NAME
1
2
3
VIN
GND
REF
4
5
6
CAP
GND
D15 (MSB)
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
D14
D13
D12
D11
D10
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
23
24
–VS
R/C
25
CS
26
BUSY
27
28
+VS
+VS
DESCRIPTION
Analog Input. Full-scale input range is ±2.5V.
Ground.
Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system reference. In
both cases, connect to ground with a 0.1µF ceramic capacitor in parallel with 2.2µF tantalum capacitor.
Reference compensation capacitor. Use a parallel combination of a 0.1µF ceramic capacitor and a 2.2µF tantalum capacitor.
Ground.
Data Bit 15. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, when R/C is LOW or when a
conversion is in progress.
Data Bit 14. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 13. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 12. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 11. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 10. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 9. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 8. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Ground.
Data Bit 7. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 6. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 5. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 4. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 3. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 2. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 1. Hi-Z state when CS is HIGH, when R/C is LOW or when a conversion is in progress.
Data Bit 0. Least Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, when R/C is LOW or when a
conversion is in progress.
Negative supply input. Nominally –5V. Decouple to analog ground with 0.1µF ceramic and 10µF tantalum capacitors.
Read/convert input. With R/C HIGH, CS going LOW will enable the output data bits if a conversion is not in progress. With
R/C LOW, CS going LOW will start a conversion if one is not already in progress.
Chip select. With R/C LOW, CS going LOW will initiate a conversion if one is not already in progress. With R/C HIGH, CS
going LOW will enable the output data bits if a conversion is not in progress.
Busy output. Falls when a conversion is started, and remains LOW until the conversion is completed. With CS LOW and
R/C HIGH, output data will be valid when BUSY rises, so that the rising edge can be used to latch the data. CS or R/C must
be HIGH within 250ns after BUSY rises or another conversion will start without time for signal acquisition.
Positive supply input. Nominally +5V. Connect directly to pin 28.
Positive supply input. Nominally +5V. Connect directly to pin 27. Decouple to ground with 0.1µF ceramic and 10µF
tantalum capacitors.
TABLE I. Pin Assignments.
PIN CONFIGURATION
Top View
SOIC
VIN
1
28 +VS
GND
2
27 +VS
REF
3
26 BUSY
CAP
4
25 CS
GND
5
24 R/C
D15 (MSB)
6
23 –VS
D14
7
22 D0 (LSB)
ADS7811
D13
8
21 D1
D12
9
20 D2
D11 10
19 D3
D10 11
18 D4
D9 12
17 D5
D8 13
16 D6
GND 14
15 D7
®
ADS7811
4
TYPICAL PERFORMANCE CURVES
At TA = –25°C to +85°C, fS = 250kHz, +VS = +5V, and –VS = –5V, using internal reference, unless otherwise specified.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 99kHz, –0.5dB)
0
0
–20
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 9.9kHz, –0.5dB)
–60
–80
–100
–60
–80
–100
–120
–120
–140
–140
0
25
50
75
100
0
125
25
50
100
125
INTEGRAL LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs OUTPUT CODE
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 247kHz, –0.5dB)
0
ILE (LSB)
4
–20
–40
–60
2
0
–2
–4
–80
4
–100
2
DLE (LSB)
Amplitude (dB)
75
Frequency (kHz)
Frequency (kHz)
–120
–140
0
25
50
75
100
0
–2
–4
8000h
125
C000h
0000h
4000h
7FFFh
Frequency (kHz)
Hex BTC Code
REFERENCE VOLTAGE
vs TEMPERATURE
3.70
2.520
3.65
2.515
3.60
2.510
Reference Voltage (V)
Conversion Time (µs)
CONVERSION TIME (t2 + t4)
vs TEMPERATURE
3.55
3.50
3.45
3.40
2.505
2.500
2.495
2.490
2.485
3.35
2.480
3.30
–30
–10
10
30
50
70
–30
90
–10
10
30
50
70
90
Temperature (°C)
Temperature (°C)
®
5
ADS7811
BASIC OPERATION
is placed on these outputs. In the circuit shown in Figure 1,
the rising edge of BUSY latches the result into the 74HC574s.
Figure 1 shows the recommended circuit for operation of the
ADS7811. A falling edge on the convert pulse signal places
the sample and hold into the hold mode and initiates a
conversion. When the conversion is complete, the pins D15
through D0 become active and the result of the conversion
After the conversion is complete, the ADS7811 sample and
hold returns to the sample mode and begins acquiring the
input signal for the next conversion. Allowing 4µs between
falling edges of the convert pulse signal assures adequate
acquisition time for the internal sample and hold.
R1
75Ω
+5V
R2
10Ω
OPA628
–5V
2.2µF
C3
2.2µF
C4
+
+
0.1µF
C5
0.1µF
C6
1
VIN
+VS 28
2
GND
+VS 27
3
REF
BUSY 26
4
CAP
CS 25
5
GND
R/C 24
6
D15
–VS 23
7
8
D0 22
D14
ADS7811
D1 21
D13
9
D12
D2 20
10
D11
D3 19
11
D10
D4 18
2
12
D9
D5 17
3
13
D8
D6 16
4
14
GND
D7 15
5
0.1µF
C1
+
+5V
10µF
C2
Convert Pulse
74HC00
0.1µF
C7
–5V
100ns min
3.3µs max
10µF
+ C8
OC
1
10
6
7
8
9
OC
CLK
1D
1Q
2D
2Q
3D
3Q
4D
4Q
5D
5Q
6D
6Q
7D
7Q
8D
8Q
µProcessor
Bus
74HC574
1
10
2
3
4
5
6
7
8
9
OC
CLK
1D
1Q
2D
2Q
3D
3Q
4D
4Q
5D
5Q
6D
6Q
7D
7Q
8D
8Q
74HC574
FIGURE 1. Basic Operation.
®
ADS7811
6
µProcessor
Bus
TIMING
the digital outputs tri-stating while the sample and hold
transitions to the hold mode. The change in digital outputs
results in noise being coupled onto the hold capacitor.
The timing shown in Figure 2 and Table II is the recommended method of operating the ADS7811. The falling edge
of CS initiates the conversion. During the conversion, the
digital outputs are tri-stated and BUSY is LOW. Near the
end of the conversion, the digital outputs become active with
the most recent conversion result. After a brief delay (see
time t11 in Figure 2 and Table II), BUSY rises. The rising
edge of BUSY is used to latch the digital result in Figure 1.
If a conversion is not in progress or is just about to finish, the
digital outputs will be active when R/C is HIGH and CS is
LOW. This is shown in Figure 2 and Figure 3. It is possible
to return CS HIGH during the initial part of the conversion
(as is done with R/C) and prevent the digital outputs from
becoming active. At a later time, the digital results could be
read by taking CS LOW. It is also possible to leave R/C
LOW, take CS HIGH during the conversion, and read the
results at a later time by taking R/C HIGH and CS LOW.
R/C AND CS
The R/C (read/convert) and CS signals control the start of
conversion and, when a conversion is not in progress, the
status of the digital outputs D15 through D0. It is possible to
start a conversion by taking CS LOW and then taking R/C
LOW. However, this is not recommended and will result in
a significant decrease in signal-to-noise ratio. This is due to
SYMBOL
DESCRIPTION
MIN
t2
TYP
MAX
UNITS
200
ns
t1
CS to R/C Delay
t2
CS to BUSY Delay
40
ns
t3
Aperture Delay
40
ns
3.5
µs
t4
BUSY LOW
t5
R/C LOW to CS LOW
t6
BUSY HIGH to CS HIGH
t7
Bus Access Time
t8
Bus Relinquish Time
83
ns
t9
Throughput Time
4
µs
100
t10
Conversion Time
Data Valid to BUSY HIGH
25
t12
CS to R/C Setup Time
40
R/C and CS should remain static prior to that start of
conversion and during the later part of a conversion. To start
t12
R/C
ns
10
t11
Following a conversion, if R/C and CS are both LOW 250ns
after BUSY rises, then a new conversion will be initiated
without allowing the proper acquisition period for the sample
and hold. R/C must remain HIGH or CS must be taken
HIGH within 250ns of BUSY rising.
250
ns
83
ns
3.4
µs
35
ns
t7
t8
CS
D15 - D0
DataValid
Hi-Z State
Hi-Z State
Acquire
MODE
ns
TABLE II. Conversion Timing.
FIGURE 3. Bus Timing.
t1
t5
R/C
t6
t9
CS
t2
t4
BUSY
t8
Hi-Z State
D15 - D0
DataValid
Hi-Z State
t11
t3
MODE
Acquire
Convert
Acquire
t10
FIGURE 2. ADS7811 Timing.
®
7
ADS7811
a conversion, R/C should be taken LOW at least 100ns
before CS is taken LOW. R/C and/or CS should be taken
HIGH during the early part of the conversion, preferably
within 200ns of the start of the conversion. If these times are
not observed, then there is risk that the transition of these
digital signals may affect the conversion result.
to that listed in the Specifications Table. The range for the
external reference is 2.3V to 2.7V. While the ADS7811 will
operate using an external reference, the specifications are
only guaranteed when the internal reference is used.
REF PIN
The REF pin itself should be bypassed with a 0.1µF ceramic
capacitor in parallel with a 2.2µF tantalum capacitor. While
both capacitors should be physically close to the ADS7811,
it is very important that the ceramic capacitor be placed as
close as possible.
The three NAND gates shown in Figure 1 can be used to
generate R/C and CS signals from a single negative going
pulse. The pulse must not be longer than 3.3µs or a second
conversion may be initiated immediately after the first.
BUSY
BUSY goes LOW when a conversion is started and remains
LOW throughout the conversion. Just prior to BUSY going
HIGH, the digital outputs become active with the conversion
result. Time t11, shown in Figure 2, should provide adequate
time for the ADS7811 to drive the digital outputs to a valid
logic state before BUSY rises. As shown in Figure 1 and 2,
the rising edge of BUSY can be used to latch the digital
result into an external component.
The REF voltage should not be used to drive a large load or
any load which is dynamic. A large load will reduce the
reference voltage and the corresponding input range of the
converter. A dynamic load will modulate the reference
voltage and this modulation will be present in the converter’s
output data.
CAP PIN
The voltage on the CAP pin is the output of the reference
buffer. This pin should be bypassed with a 0.1µF ceramic
capacitor in parallel with a 2.2µF tantalum capacitor. While
both capacitors should be physically close to the ADS7811,
it is very important that the ceramic capacitor be placed as
close as possible.
DIGITAL OUTPUT
The ADS7811’s digital output is in Binary Two’s Complement (BTC) format. Table III shows the relationship between the digital output word and analog input voltage under
ideal conditions.
The CAP pin connects to the internal reference buffer and
directly to the binary weighted capacitor array of the converter. Thus, the signal at the CAP pin has high-frequency
glitches which occur at each bit decision. For this reason, the
CAP voltage should not be used to provide a reference
voltage for external circuitry.
DIGITAL OUTPUT
ANALOG
INPUT
DESCRIPTION
BINARY CODE
HEX CODE
2.499924V
0111 1111 1111 1111
7FFF
Full Scale Range
±2.5V
Least Significant
Bit (LSB)
76µV
+Full Scale
(2.5V – 1LSB)
Midscale
BINARY TWO’S COMPLEMENT
LAYOUT
0V
0000 0000 0000 0000
0000
One LSB below
Midscale
–76µV
1111 1111 1111 1111
FFFF
–Full Scale
–2.5V
1000 0000 0000 0000
8000
The layout of the ADS7811 and accompanying components
will be critical for optimum performance. Use of an analog
ground plane is essential. Use of +5V and –5V power planes
is not critical as long as the supplies are well bypassed, and
the traces connecting +5V and –5V to the power connector
are not too long or too thin.
Table III. Ideal Input Voltages and Output Codes.
The two +VS power pins of the ADS7811 must be tied
together. The voltage source for these pins should also
power the input buffer and the 74HC00 shown in Figure 1.
This supply should separate from the positive +5V supply
for the system’s digital logic
REFERENCE
The ADS7811 can be operated with the internal 2.5V reference or an external reference. By applying an external
reference to the REF pin, the internal reference is bypassed.
The reference voltage at REF is buffered internally.
Three ground pins are present on the ADS7811: pin 2, pin 5,
and pin 14. These should all be tied to the analog ground
plane. The analog ground plane should extend underneath
all analog signal conditioning components and up to the
74HC574s (or equivalent components) shown in Figure 1.
The 74HC574s should not be located more than several
inches from the ADS7811.
The voltage at the reference input sets the full-scale range of
the converter. With the internal 2.5V reference, the input
range is ±2.5V. Thus, the input range of the converter’s
analog input is simply ±VREF, where VREF is the voltage at
the reference input. Because of internal gain and offset error,
the input range will not be exactly ±VREF. The full-scale
error of the converter with an external reference will typically be 0.25% or less. The bipolar zero error will be similar
The ground for the 74HC574s should be connected to the
digital ground. The analog ground plane should extend up to
®
ADS7811
8
SIGNAL CONDITIONING
The ADS7811 input essentially consists of a switch and a
capacitor. In the acquisition or sample mode, the switch is
closed and the input signal drives the capacitor directly.
When a conversion is started, the switch is opened capturing
the input signal at that moment. This voltage is held on the
capacitor for the remainder of the conversion.
the 74HC574s but should be kept at least 1/4" (6mm) distant
from the digital ground plane (if present). The analog and
digital grounds planes should not overlap at any point.
INTERMEDIATE LATCHES
The 74HC574s shown in Figure 1 isolate the ADS7811 from
digital signals on a microprocessor, digital signal processor
(DSP), or microcontroller bus. This is necessary because of
the precision needed within the ADS7811. The weight of a
single LSB in the ADS7811 is 76µV, and the comparator
must be able to resolve differences in voltage to this level.
External digital signals which transition during the conversion can easily couple onto the substrate and produce voltages larger than this.
While this provides for a wide bandwidth sample and hold
function and results in excellent AC performance, this architecture requires a high bandwidth, precision op amp to drive
the analog input. The op amp and configuration shown in
Figure 1 is highly recommended. The amplifier should be
placed within 1 to 2 inches (25 to 50mm) of the ADS7811,
and the layout guidelines in the OPA628 data sheet should
be strictly followed.
In place of the 74HC574s, it might be possible to use a FIFO
or similar type of memory device. For many systems, it may
be difficult to go directly from the ADS7811 into a
microcontroller or DSP even if the ADS7811 is not connected to shared bus. The reason for this is that the outputs
are active only during the acquisition period.
®
9
ADS7811