MicroConverter ®, Dual 16-Bit - ADCs with Embedded 62 kB Flash MCU ADuC836 FEATURES High Resolution - ADCs 2 Independent ADCs (16-Bit Resolution) 16-Bit No Missing Codes, Primary ADC 16-Bit rms (16-Bit p-p) Effective Resolution @ 20 Hz Offset Drift 10 nV/C, Gain Drift 0.5 ppm/C Memory 62 Kbytes On-Chip Flash/EE Program Memory 4 Kbytes On-Chip Flash/EE Data Memory Flash/EE, 100 Year Retention, 100 Kcycles Endurance 3 Levels of Flash/EE Program Memory Security In-Circuit Serial Download (No External Hardware) High Speed User Download (5 Seconds) 2304 Bytes On-Chip Data RAM 8051 Based Core 8051 Compatible Instruction Set 32 kHz External Crystal On-Chip Programmable PLL (12.58 MHz Max) 3 16-Bit Timer/Counter 26 Programmable I/O Lines 11 Interrupt Sources, 2 Priority Levels Dual Data Pointer, Extended 11-Bit Stack Pointer On-Chip Peripherals Internal Power on Reset Circuit 12-Bit Voltage Output DAC Dual 16-Bit - DACs/PWMs On-Chip Temperature Sensor Dual Excitation Current Sources Time Interval Counter (Wake-Up/RTC Timer) UART, SPI®, and I2 C® Serial I/O High Speed Baud Rate Generator (Including 115,200) Watchdog Timer (WDT) Power Supply Monitor (PSM) Power Normal: 2.3 mA Max @ 3.6 V (Core CLK = 1.57 MHz) Power-Down: 20 A Max with Wake-Up Timer Running Specified for 3 V and 5 V Operation Package and Temperature Range 52-Lead MQFP (14 mm 14 mm), –40C to +125C 56-Lead LFCSP (8 mm 8 mm), –40C to +85C APPLICATIONS Intelligent Sensors Weigh Scales Portable Instrumentation, Battery-Powered Systems 4–20 mA Transmitters Data Logging Precision System Monitoring FUNCTIONAL BLOCK DIAGRAM ADuC836 AVDD AIN1 AIN2 AIN3 AIN4 BUF MUX PGA PRIMARY 16-BIT - ADC AGND AUXILIARY 16-BIT - ADC MUX AIN5 REFIN– EXTERNAL VREF DETECT INTERNAL BAND GAP VREF RESET DVDD 12-BIT DAC DUAL 16-BIT - DAC BUF IEXC1 IEXC2 DAC PWM0 MUX PWM1 8051-BASED MCU WITH ADDITIONAL PERIPHERALS 62 KBYTES FLASH/EE PROGRAM MEMORY 4 KBYTES FLASH/EE DATA MEMORY 2304 BYTES USER RAM POR DGND CURRENT SOURCE DUAL 16-BIT PWM TEMP SENSOR REFIN+ AVDD PLL AND PROG CLOCK DIV OSC WAKE- UP/ RTC TIMER 3 16 BIT TIMERS BAUD R ATE TIMER POWER SUPPLY MON WATCHDOG TIMER 4 PARALLEL PORTS UART, SPI, AND I2C SERIAL I/O XTAL1 XTAL2 GENERAL DESCRIPTION The ADuC836 is a complete smart transducer front end, integrating two high resolution - ADCs, an 8-bit MCU, and program/data Flash/EE memory on a single chip. The two independent ADCs (primary and auxiliary) include a temperature sensor and a PGA (allowing direct measurement of low level signals). The ADCs with on-chip digital filtering and programmable output data rates are intended for the measurement of wide dynamic range, low frequency signals, such as those in weigh scale, strain gage, pressure transducer, or temperature measurement applications. The device operates from a 32 kHz crystal with an on-chip PLL generating a high frequency clock of 12.58 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an 8052 and therefore 8051 instruction set compatible with 12 core clock periods per machine cycle. 62 Kbytes of nonvolatile Flash/EE program memory, 4 Kbytes of nonvolatile Flash/EE data memory, and 2304 bytes of data RAM are provided on-chip. The program memory can be configured as data memory to give up to 60 Kbytes of NV data memory in data logging applications. REV. A On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as single-pin emulation mode via the EA pin. The ADuC836 is supported by a QuickStart™ development system featuring low cost software and hardware development tools. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADuC836 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 NONVOLATILE FLASH/EE MEMORY Flash/EE Memory Overview . . . . . . . . . . . . . . . . . . . . . . . .29 Flash/EE Memory and the ADuC836 . . . . . . . . . . . . . . . . .29 ADuC836 Flash/EE Memory Reliability . . . . . . . . . . . . . . .29 Flash/EE Program Memory . . . . . . . . . . . . . . . . . . . . . . . .30 Serial Downloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Parallel Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 User Download Mode (ULOAD) . . . . . . . . . . . . . . . . . . . .31 Flash/EE Program Memory Security . . . . . . . . . . . . . . . . . .31 Lock, Secure, and Serial Safe Modes . . . . . . . . . . . . . . . . . .31 Using the Flash/EE Data Memory . . . . . . . . . . . . . . . . . . .32 ECON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Programming the Flash/EE Data Memory . . . . . . . . . . . . .33 Flash/EE Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . .33 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . .1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . .1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . .9 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .9 DETAILED BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . .10 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . .10 OTHER ON-CHIP PERIPHERALS DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 On-Chip PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Time Interval Counter (Wake-Up/RTC Timer) . . . . . . . . .40 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Power Supply Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . .44 I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Dual Data Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . .13 SPECIAL FUNCTION REGISTERS (SFRS) . . . . . . . . . .14 Accumulator SFR (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . .14 B SFR (B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Stack Pointer (SP and SPH) . . . . . . . . . . . . . . . . . . . . . . . .15 Program Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . . . .15 Power Control SFR (PCON) . . . . . . . . . . . . . . . . . . . . . . .15 ADuC836 Configuration SFR (CFG836) . . . . . . . . . . . . . .15 Complete SFR Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 8052 COMPATIBLE ON-CHIP PERIPHERALS Parallel I/O Ports 0–3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 UART Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 UART Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Baud Rate Generation Using Timer 1 and Timer 2 . . . . . . .59 Baud Rate Generation Using Timer 3 . . . . . . . . . . . . . . . . .60 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 ADC SFR INTERFACE ADCSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 ADCMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 ADC0CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 ADC1CON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 ADC0H/ADC0M/ADC1H/ADC1L . . . . . . . . . . . . . . . . . .20 OF0H/OF0M/OF1H/OF1L . . . . . . . . . . . . . . . . . . . . . . . .20 GN0H/GN0M/GN1H/GN1L . . . . . . . . . . . . . . . . . . . . . . .20 SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 ICON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 HARDWARE DESIGN CONSIDERATIONS External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . .63 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Power-On Reset (POR) Operation . . . . . . . . . . . . . . . . . . .64 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Wake-Up from Power-Down Latency . . . . . . . . . . . . . . . . .65 Grounding and Board Layout Recommendations . . . . . . . .66 ADuC836 System Self-Identification . . . . . . . . . . . . . . . . . .66 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Primary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Auxiliary ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Primary and Auxiliary ADC Inputs . . . . . . . . . . . . . . . . . . .25 Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . .25 Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Excitation Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 ADC Chopping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 OTHER HARDWARE CONSIDERATIONS In-Circuit Serial Download Access . . . . . . . . . . . . . . . . . . .67 Embedded Serial Port Debugger . . . . . . . . . . . . . . . . . . . . .67 Single-Pin Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . .67 Typical System Configuration . . . . . . . . . . . . . . . . . . . . . . .68 QUICKSTART DEVELOPMENT SYSTEM . . . . . . . . . . .69 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . .70 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .80 –2– REV. A SPECIFICATIONS1 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, REFIN(+) = 2.5 V; REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 = 32.768 kHz Crystal; all specifications TMIN to TMAX, unless otherwise noted.) Parameter ADC SPECIFICATIONS Conversion Rate Primary ADC No Missing Codes2 Resolution Output Noise Integral Nonlinearity Offset Error3 Offset Error Drift Full-Scale Error4 Gain Error Drift5 ADC Range Matching Power Supply Rejection (PSR) Common-Mode DC Rejection On AIN On REFIN Common-Mode 50 Hz/60 Hz Rejection On AIN ADuC836 Test Conditions/Comments Unit 5.4 105 On Both Channels Programmable in 0.732 ms Increments Hz min Hz max 16 13.5 16 See Tables X and XI in ADuC836 ADC Description ±15 ±3 ±10 ±10 ±0.5 ±0.5 ±2 95 80 20 Hz Update Rate Range = ±20 mV, 20 Hz Update Rate Range = ±2.56 V, 20 Hz Update Rate Output Noise Varies with Selected Update Rate and Gain Range 1 LSB Bits min Bits p-p typ Bits p-p typ 95 113 125 At DC, AIN = 7.8 mV, Range = ±20 mV At DC, AIN = 1 V, Range = ±2.56 V At DC, AIN = 1 V, Range = ±2.56 V 20 Hz Update Rate 50 Hz/60 Hz ±1 Hz, AIN = 7.8 mV, Range = ±20 mV 50 Hz/60 Hz ±1 Hz, AIN = 1 V, Range = ±2.56 V 50 Hz/60 Hz ±1 Hz, AIN = 1 V, Range = ±2.56 V dBs typ dBs typ dBs typ 50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate 50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate dBs typ dBs typ 95 90 On REFIN Normal Mode 50 Hz/60 Hz Rejection On AIN On REFIN Auxiliary ADC No Missing Codes2 Resolution Output Noise Integral Nonlinearity Offset Error3 Offset Error Drift Full-Scale Error6 Gain Error Drift5 Power Supply Rejection (PSR) Normal Mode 50 Hz/60 Hz Rejection On AIN On REFIN DAC PERFORMANCE DC Specifications7 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error8 AC Specifications2, 7 Voltage Output Settling Time Digital-to-Analog Glitch Energy REV. A ADuC836 90 60 60 16 16 See Table XII in ADuC836 ADC Description ±15 –2 1 –2.5 ±0.5 80 60 60 12 ±3 –1 ±50 ±1 ±1 Range = ±20 mV to ±640 mV Range = ±1.28 V to ±2.56 V AIN = 18 mV AIN = 7.8 mV, Range = ±20 mV AIN = 1 V, Range = ±2.56 V Range = ±2.5 V, 20 Hz Update Rate Output Noise Varies with Selected Update Rate –3– dBs typ dBs typ dBs typ Bits min Bits p-p typ AIN = 1 V, 20 Hz Update Rate ppm of FSR max LSB typ V/°C typ LSB typ ppm/°C typ dBs typ 50 Hz/60 Hz ±1 Hz 50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate dBs typ dBs typ AVDD Range VREF Range Bits LSB typ LSB max mV max % max % typ Settling Time to 1 LSB of Final Value 1 LSB Change at Major Carry s typ nVs typ Guaranteed 12-Bit Monotonic 15 10 ppm of FSR max V typ nV/°C typ V typ LSB typ ppm/°C typ V typ dBs typ dBs typ ADuC836 SPECIFICATIONS (continued) Parameter INTERNAL REFERENCE ADC Reference Reference Voltage Power Supply Rejection Reference Tempco DAC Reference Reference Voltage Power Supply Rejection Reference Tempco ADuC836 Test Conditions/Comments Unit 1.25 ± 1% 45 100 Initial Tolerance @ 25°C, VDD = 5 V V min/max dBs typ ppm/°C typ 2.5 ± 1% 50 ±100 Initial Tolerance @ 25°C, VDD = 5 V V min/max dBs typ ppm/°C typ ANALOG INPUTS/REFERENCE INPUTS Primary ADC Differential Input Voltage Ranges9, 10 Bipolar Mode (ADC0CON3 = 0) Analog Input Current2 Analog Input Current Drift Absolute AIN Voltage Limits2 Auxiliary ADC Input Voltage Range9, 10 Average Analog Input Current Average Analog Input Current Drift2 Absolute AIN Voltage Limits2, 11 External Reference Inputs REFIN(+) to REFIN(–) Range2 Average Reference Input Current Average Reference Input Current Drift “NO Ext. REF” Trigger Voltage ADC SYSTEM CALIBRATION Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span ANALOG (DAC) OUTPUT Voltage Range Resistive Load Capacitive Load Output Impedance ISINK TEMPERATURE SENSOR Accuracy Thermal Impedance (JA) External Reference Voltage = 2.5 V RN2, RN1, RN0 of ADC0CON Set to 0 0 0 (Unipolar Mode 0 mV to 20 mV) 0 0 1 (Unipolar Mode 0 mV to 40 mV) 0 1 0 (Unipolar Mode 0 mV to 80 mV) 0 1 1 (Unipolar Mode 0 mV to 160 mV) 1 0 0 (Unipolar Mode 0 mV to 320 mV) 1 0 1 (Unipolar Mode 0 mV to 640 mV) 1 1 0 (Unipolar Mode 0 V to 1.28 V) 1 1 1 (Unipolar Mode 0 V to 2.56 V) TMAX = 85°C TMAX = 125°C TMAX = 85°C TMAX = 125°C ±20 ±40 ±80 ±160 ±320 ±640 ±1.28 ±2.56 ±1 ±5 ±5 ±15 AGND + 100 mV AVDD – 100 mV 0 to VREF Unipolar Mode, for Bipolar Mode See Note 11 Input Current Will Vary with Input Voltage on the Unbuffered Auxiliary ADC 125 ±2 AGND – 30 mV AVDD + 30 mV 1 AVDD 1 ±0.1 0.3 0.65 Both ADCs Enabled NOXREF Bit Active if VREF < 0.3 V NOXREF Bit Inactive if VREF > 0.65 V 1.05 FS –1.05 FS 0.8 FS 2.1 FS mV mV mV mV mV mV V V nA max nA max pA/°C typ pA/°C typ V min V max V nA/V typ pA/V/°C typ V min V max V min V max A/V typ nA/V/°C typ V min V max V max V min V min V max 0 to VREF 0 to AVDD 10 100 0.5 50 DACRN = 0 in DACCON SFR DACRN = 1 in DACCON SFR From DAC Output to AGND From DAC Output to AGND ±2 90 52 MQFP Package CSP Package (Base Floating)12 –4– V typ V typ k typ pF typ typ A typ °C typ °C/W typ °C/W typ REV. A ADuC836 Parameter ADuC836 TRANSDUCER BURNOUT CURRENT SOURCES AIN+ Current –100 AIN– Current +100 Initial Tolerance @ 25°C Drift ±10 0.03 EXCITATION CURRENT SOURCES Output Current Initial Tolerance @ 25°C Drift Initial Current Matching @ 25°C Drift Matching Line Regulation (AVDD) Load Regulation Output Compliance2 LOGIC INPUTS All Inputs Except SCLOCK, RESET, and XTAL12 VINL, Input Low Voltage VINH, Input High Voltage SCLOCK and RESET Only (Schmitt-Triggered Inputs)2 VT+ VT– VT+ – VT– Input Currents Port 0, P1.2–P1.7, EA SCLOCK, MOSI, MISO, SS13 RESET P1.0, P1.1, Ports 2 and 3 Input Capacitance Unit AIN+ Is the Selected Positive Input to the Primary ADC AIN– Is the Selected Negative Input to the Auxiliary ADC nA typ nA typ % typ %/°C typ –200 ±10 200 ±1 20 1 0.1 AVDD – 0.6 AGND Available from Each Current Source 0.8 0.4 2.0 DVDD = 5 V DVDD = 3 V V max V max V min 1.3/3 0.95/2.5 0.8/1.4 0.4/1.1 0.3/0.85 0.3/0.85 DVDD = 5 V DVDD = 3 V DVDD = 5 V DVDD = 3 V DVDD = 5 V DVDD = 3 V V min/V max V min/V max V min/V max V min/V max V min/V max V min/V max ±10 –10 min, –40 max ±10 ±10 35 min, 105 max VIN = 0 V or VDD VIN = 0 V, DVDD = 5 V, Internal Pull-Up VIN = VDD, DVDD = 5 V VIN = 0 V, DVDD = 5 V VIN = VDD, DVDD = 5 V, Internal Pull-Down VIN = VDD, DVDD = 5 V VIN = 2 V, DVDD = 5 V A max A min/A max A max A max A min/A max Matching between Both Current Sources AVDD = 5 V + 5% ±10 –180 –660 –20 –75 5 VIN = 450 mV, DVDD = 5 V All Digital Inputs CRYSTAL OSCILLATOR (XTAL1 AND XTAL2) Logic Inputs, XTAL1 Only2 VINL, Input Low Voltage 0.8 0.4 VINH, Input High Voltage 3.5 2.5 XTAL1 Input Capacitance 18 XTAL2 Output Capacitance 18 REV. A Test Conditions/Comments DVDD = 5 V DVDD = 3 V DVDD = 5 V DVDD = 3 V –5– A typ % typ ppm/°C typ % typ ppm/°C typ A/V typ A/V typ V max V min A max A min A max A min A max pF typ V max V max V min V min pF typ pF typ ADuC836 SPECIFICATIONS (continued) Parameter ADuC836 Test Conditions/Comments Unit VDD = 5 V, ISOURCE = 80 A VDD = 3 V, ISOURCE = 20 A ISINK = 8 mA, SCLOCK, MOSI/SDATA ISINK = 10 mA, P1.0 and P1.1 ISINK = 1.6 mA, All Other Outputs V min V min V max V max V max A max pF typ 2.63 4.63 ±3.0 ±4.0 2.63 4.63 ±3.0 ±4.0 Four Trip Points Selectable in This Range Programmed via TPA1–0 in PSMCON TMAX = 85°C TMAX = 125°C Four Trip Points Selectable in This Range Programmed via TPD1–0 in PSMCON TMAX = 85C TMAX = 125C V min V max % max % max V min V max % max % max 0 2000 Nine Timeout Periods in This Range Programmed via PRE3–0 in WDCON ms min ms max 98.3 Clock Rate Generated via On-Chip PLL Programmable via CD2–0 Bits in PLLCON SFR kHz min 2 LOGIC OUTPUTS (Not Including XTAL2) VOH, Output High Voltage 2.4 2.4 VOL, Output Low Voltage14 0.4 0.4 0.4 Floating State Leakage Current2 ±10 Floating State Output Capacitance 5 POWER SUPPLY MONITOR (PSM) AVDD Trip Point Selection Range AVDD Power Supply Trip Point Accuracy DVDD Trip Point Selection Range DVDD Power Supply Trip Point Accuracy WATCHDOG TIMER (WDT) Timeout Period MCU CORE CLOCK RATE MCU Clock Rate2 START-UP TIME At Power-On After External RESET in Normal Mode After WDT Reset in Normal Mode From Idle Mode From Power-Down Mode Oscillator Running Wake-Up with INT0 Interrupt Wake-Up with SPI Interrupt Wake-Up with TIC Interrupt Wake-Up with External RESET Oscillator Powered Down Wake-Up with INT0 Interrupt Wake-Up with SPI Interrupt Wake-Up with External RESET 12.58 MHz max 300 3 3 10 ms typ ms typ ms typ s typ Controlled via WDCON SFR OSC_PD Bit = 0 in PLLCON SFR 20 20 20 3 s typ s typ s typ ms typ OSC_PD Bit = 1 in PLLCON SFR 20 20 5 s typ s typ ms typ FLASH/EE MEMORY RELIABILITY CHARACTERISTICS15 Endurance16 100,000 Data Retention17 100 Cycles min Years min –6– REV. A ADuC836 Parameter POWER REQUIREMENTS Power Supply Voltages AVDD, 3 V Nominal Operation AVDD, 5 V Nominal Operation DVDD, 3 V Nominal Operation DVDD, 5 V Nominal Operation ADuC836 Test Conditions/Comments 2.7 3.6 4.75 5.25 2.7 3.6 4.75 5.25 V min V max V min V max V min V max V min V max 5 V POWER CONSUMPTION Power Supply Currents Normal Mode18, 19 DVDD Current 4 DVDD Current 13 16 AVDD Current 180 Power Supply Currents Power-Down Mode18, 19 DVDD Current 53 100 DVDD Current 30 80 AVDD Current 1 3 Typical Additional Power Supply Currents (AIDD and DIDD) PSM Peripheral Primary ADC Auxiliary ADC DAC Dual Current Sources DVDD = 4.75 V to 5.25 V, AVDD = 5.25 V Core CLK = 1.57 MHz Core CLK = 12.58 MHz Core CLK = 12.58 MHz Core CLK = 1.57 MHz or 12.58 MHz Core CLK = 1.57 MHz or 12.58 MHz TMAX = 85°C; Osc. On, TIC On TMAX = 125°C; Osc. On, TIC On TMAX = 85°C; Osc. Off TMAX = 125°C; Osc. Off TMAX = 85°C; Osc. On or Osc. Off TMAX = 125°C; Osc. On or Osc. Off mA max mA typ mA max A max A max A max A max A max A max A max Core CLK = 1.57 MHz 50 1 500 150 400 A typ mA typ A typ A typ A typ 3 V POWER CONSUMPTION Power Supply Currents Normal Mode18, 19 DVDD Current 2.3 DVDD Current 8 10 AVDD Current 180 DVDD = 2.7 V to 3.6 V Core CLK = 1.57 MHz Core CLK = 12.58 MHz Core CLK = 12.58 MHz AVDD = 5.25 V, Core CLK = 1.57 MHz or 12.58 MHz Core CLK = 1.57 MHz or 12.58 MHz TMAX = 85°C; Osc. On, TIC On TMAX = 125°C; Osc. On, TIC On Osc. Off AVDD = 5.25 V; TMAX = 85°C; Osc. On or Osc. Off AVDD = 5.25 V; TMAX = 125°C; Osc. On or Osc. Off Power Supply Currents Power-Down Mode18, 19 DVDD Current 20 40 DVDD Current 10 AVDD Current 1 3 REV. A Unit DVDD and AVDD Can Be Set Independently –7– mA max mA typ mA max A max A max A max A typ A max A max ADuC836 NOTES 1 Temperature range for ADuC836BS (MQFP package) is –40°C to +125°C. Temperature range for ADuC836BCP (CSP package) is –40°C to +85°C. 2 These numbers are not production tested but are guaranteed by design and/or characterization data on production release. 3 System Zero-Scale Calibration can remove this error. 4 The primary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of 10 V. If user power supply or temperature conditions are significantly different from these, an Internal Full-Scale Calibration will restore this error to 10 V. A system zero-scale and full-scale calibration will remove this error altogether. 5 Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input. 6 The auxiliary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration will remove this error altogether. 7 DAC linearity and ac specifications are calculated using: reduced code range of 48 to 4095, 0 to VREF; reduced code range of 100 to 3950, 0 to VDD. 8 Gain Error is a measurement of the span error of the DAC. 9 In general terms, the bipolar input voltage range to the primary ADC is given by RangeADC = ±(VREF 2RN)/125, where: VREF = REFIN(+) to REFIN(–) voltage and VREF = 1.25 V when internal ADC VREF is selected. RN = decimal equivalent of RN2, RN1, RN0, e.g., VREF = 2.5 V and RN2, RN1, RN0 = 1, 1, 0 the RangeADC = ±1.28 V. In Unipolar mode, the effective range is 0 V to 1.28 V in our example. 10 1.25 V is used as the reference voltage to the auxiliary ADC when internal VREF is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON, respectively. 11 In Bipolar mode, the auxiliary ADC can only be driven to a minimum of AGND – 30 mV as indicated by the auxiliary ADC absolute AIN voltage limits. The bipolar range is still –VREF to +VREF; however, the negative voltage is limited to –30 mV. 12 The ADuC836BCP (CSP package) has been qualified and tested with the base of the CSP package floating. 13 Pins configured in SPI mode, pins configured as digital inputs during this test. 14 Pins configured in I2C mode only. 15 Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory. 16 Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40°C, +25°C, +85°C, and +125°C. Typical endurance at 25°C is 700 Kcycles. 17 Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV will derate with junction temperature as shown in Figure 16 in the Flash/EE Memory section. 18 Power Supply current consumption is measured in Normal, Idle, and Power-Down modes under the following conditions: Normal mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop. Idle mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode. Power-Down mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 pins = 0.4 V, all other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON, PCON.1 = 1, Core Execution suspended in Power-Down mode, OSC turned on or off via OSC_PD bit (PLLCON.7) in PLLCON SFR. 19 DVDD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle. Specifications subject to change without notice. –8– REV. A ADuC836 ABSOLUTE MAXIMUM RATINGS1 PIN CONFIGURATIONS 52-Lead MQFP (TA= 25°C, unless otherwise noted.) AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND2 . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +5 V Analog Input Voltage to AGND3 . . . . . . –0.3 V to AVDD + 0.3 V Reference Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V AIN/REFIN Current (Indefinite) . . . . . . . . . . . . . . . . . . 30 mA Digital Input Voltage to DGND . . . . . . –0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V Operating Temperature Range . . . . . . . . . . . . –40°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C JA Thermal Impedance (MQFP) . . . . . . . . . . . . . . . . . 90°C/W JA Thermal Impedance (LFCSP Base Floating) . . . . . . 52°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C �� � �� �� ������ ���������� ������� �������� �������������� �� �� �� �� 56-Lead LFCSP �� ������ ���������� � NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 AGND and DGND are shorted internally on the ADuC836. 3 Applies to P1.2 to P1.7 pins operating in analog or digital input modes. �� �� ������� �������� �������������� �� �� �� �� ORDERING GUIDE Model Temperature Range Package Description Package Option ADuC836BS ADuC836BCP EVAL-ADuC836QS –40°C to +125°C –40°C to +85°C 52-Lead Metric Quad Flat Package 56-Lead Lead Frame Chip Scale Package QuickStart Development System S-52 CP-56 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC836 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges.Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. A –9– ADuC836 AIN1 BUF AIN MUX AIN2 AIN3 AIN5 TEMP SENSOR PGA BAND GAP REFERENCE REFIN ADC CONTROL AND CALIBRATION 19 MCU CORE DUAL 16-BIT PWM DGND RESET SINGLE-PIN EMULATOR 40 42 26 27 14 13 32 33 XTAL1 DVDD 41 XTAL2 AGND 17 SS AVDD 16 DAC 1 PWM0 2 PWM1 22 T0 23 T1 1 T2 2 T2EX 18 INT0 19 INT1 OSC MISO 15 SPI/I2C SERIAL INTERFACE MOSI/SDATA 47 21 35 WAKE-UP/ RTC TIMER SCLOCK 20 34 48 16-BIT COUNTER TIMERS PLL WITH PROG. CLOCK DIVIDER UART TIMER 3 MUX ALE 6 BUF EA 5 TXD UART SERIAL PORT POR 25 PSEN CURRENT SOURCE MUX 24 POWER SUPPLY MONITOR 200A RXD IEXC 1 23 DUAL 16-BIT - DAC DOWNLOADER DEBUGGER IEXC 2 22 12-BIT VOLTAGE OUTPUT DAC WATCHDOG TIMER 8052 P3.6 (WR) 18 2304 BYTES USER RAM 4 KBYTES DATA FLASH/EE 2 DATA POINTERS 11-BIT STACK POINTER 200A 17 PWM CONTROL 62 KBYTES PROGRAM/ FLASH/EE VREF DETECT REFIN ADC CONTROL AND CALIBRATION PRIMARY ADC 16-BIT - ADC AUXILIARY ADC 16-BIT - ADC AIN MUX AIN4 DAC CONTROL 16 P3.7 (RD) 39 P3.4 (T0/PWMCLK) 38 P3.5 (T1) 37 P3.3 (INT1) 36 P3.2 (INT0) 31 P3.0 (RXD) 30 P3.1 (TXD) 29 P2.7 (A15/A23) 28 P2.6 (A14/A22) 12 P2.5 (A13/A21) 11 P2.3 (A11/A19) 10 P2.4 (A12/A20) 9 P2.2 (A10/A18) 4 P2.0 (A8/A16) 3 P2.1 (A9/A17) 2 P1.7 (AIN4/DAC) 1 P1.6 (AIN3) 52 P1.4 (AIN1) 51 P1.5 (AIN2) 50 P1.3 (AIN5/IEXC 2) P0.7 (AD7) 49 P1.2 (DAC/IEXC 1) P0.6 (AD6) 46 P1.0 (T2) P0.5 (AD5) 45 P1.1 (T2EX) P0.4 (AD4) 44 P0.2 (AD2) 43 P0.3 (AD3) P0.0 (AD0) P0.1 (AD1) ADuC836 *PIN NUMBERS REFER TO THE 52-LEAD MQFP PACKAGE SHADED AREAS REPRESENT THE NEW FEATURES OF THE ADuC836 OVER THE ADuC816 Figure 1. Detailed Block Diagram PIN FUNCTION DESCRIPTIONS Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic Type* Description 1, 2 P1.0/P1.1 I/O P1.0/T2/PWM0 I/O 56, 1 P1.1/T2EX/PWM1 I/O 3–4, 9–12 2–3, 11–14 P1.2–P1.7 I P1.2/DAC/IEXC1 I/O P1.3/AIN5/IEXC2 I/O P1.0 and P1.1 can function as digital inputs or digital outputs and have a pull-up configuration as described for Port 3. P1.0 and P1.1 have an increased current drive sink capability of 10 mA. P1.0 and P1.1 also have various secondary functions as described below. P1.0 can be used to provide a clock input to Timer 2. When enabled, Counter 2 is incremented in response to a negative transition on the T2 input pin. If the PWM is enabled, the PWM0 output will appear at this pin. P1.1 can also be used to provide a control input to Timer 2. When enabled, a PWM1 negative transition on the T2EX input pin will cause a Timer 2 capture or reload event. If the PWM is enabled, the PWM1 output will appear at this pin. Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital input for which 0 must be written to the port bit. As a digital input, these pins must be driven high or low externally. These pins also have the following analog functionality: The voltage output from the DAC or one or both current sources (200 µA or 2 200 µA) can be configured to appear at this pin. Auxiliary ADC input or one or both current sources can be configured at this pin. –10– REV. A ADuC836 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic Type* Description P1.4/AIN1 P1.5/AIN2 P1.6/AIN3 P1.7/AIN4/DAC I I I I/O Primary ADC, Positive Analog Input Primary ADC, Negative Analog Input Auxiliary ADC Input or Muxed Primary ADC, Positive Analog Input Auxiliary ADC Input or Muxed Primary ADC, Negative Analog Input. The voltage output from the DAC can also be configured to appear at this pin. 5 4, 5 AVDD S Analog Supply Voltage, 3 V or 5 V 6 6, 7, 8 AGND S Analog Ground. Ground reference pin for the analog circuitry. 7 9 REFIN(–) I Reference Input, Negative Terminal 8 10 REFIN(+) I Reference Input, Positive Terminal 13 15 SS I Slave Select Input for the SPI Interface. A weak pull-up is present on this pin. 14 16 MISO I/O Master Input/Slave Output for the SPI Interface. A weak pull-up is present on this input pin. 15 17 RESET I Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is running resets the device. There is an internal weak pull-down and a Schmitt trigger input stage on this pin. 16–19, 22–25 18–21, 24–27 P3.0–P3.7 I/O P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0/PWMCLK I/O I/O I/O I/O I/O P3.5/T1 P3.6/WR I/O I/O P3.7/RD I/O P3.0–P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-up resistors. When driving a 0-to-1 output transition, a strong pull-up is active for two core clock periods of the instruction cycle. Port 3 pins also have various secondary functions including: Receiver Data for UART Serial Port Transmitter Data for UART Serial Port External Interrupt 0. This pin can also be used as a gate control input to Timer 0. External Interrupt 1. This pin can also be used as a gate control input to Timer 1. Timer/Counter 0 External Input. If the PWM is enabled, an external clock may be input at this pin. Timer/Counter 1 External Input External Data Memory Write Strobe. Latches the data byte from Port 0 into an external data memory. External Data Memory Read Strobe. Enables the data from an external data memory to Port 0. 20, 34, 48 22, 36, 51, DVDD S Digital Supply, 3 V or 5 V 21, 35, 47 23, 37, 38, DGND 50 S Digital Ground. Ground reference point for the digital circuitry. 26 SCLOCK I/O Serial Interface Clock for either the I2C or SPI Interface. As an input, this pin is a Schmitt-triggered input, and a weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly controlled in software as a digital output pin. 27 MOSI/SDATA I/O Serial Data I/O for the I2C Interface or Master Output/Slave Input for the SPI Interface. A weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly controlled in software as a digital output pin. 28–31 36–39 30–33 39–42 P2.0–P2.7 (A8–A15) (A16–A23) I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24-bit external data memory space. 32 34 XTAL1 I Input to the Crystal Oscillator Inverter 33 35 XTAL2 O Output from the Crystal Oscillator Inverter. (See the Hardware Design Considerations section for description.) REV. A –11– ADuC836 PIN FUNCTION DESCRIPTIONS (continued) Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic Type* Description 40 43 EA I/O External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000h to F7FFh. When held low, this input enables the device to fetch all instructions from external program memory. To determine the mode of code execution, i.e., internal or external, the EA pin is sampled at the end of an external RESET assertion or as part of a device power cycle. EA may also be used as an external emulation I/O pin, and therefore the voltage level at this pin must not be changed during normal mode operation as it may cause an emulation interrupt that will halt code execution. 41 44 PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable Serial Download mode when pulled low through a resistor at the end of an external RESET assertion or as part of a device power cycle. 42 45 ALE O Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit data address space accesses) of the address to external memory during external code or data memory access cycles. It is activated every six oscillator periods except during an external data memory access. It can be disabled by setting the PCON.4 bit in the PCON SFR. 43–46 49–52 46–49 52–55 P0.0–P0.7 (AD0–AD3) I/O These pins are part of Port 0, which is an 8-bit, open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and in that state can be used (AD4–AD7)as high impedance inputs. An external pull-up resistor will be required on P0 outputs to force a valid logic high level externally. Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory. In this application, it uses strong internal pull-ups when emitting 1s. *I = Input, O = Output, S = Supply. –12– REV. A ADuC836 MEMORY ORGANIZATION Reset initializes the stack pointer to location 07H. Any call or push pre-increments the SP before loading the stack. Therefore, loading the stack starts from location 08H, which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the stack pointer should be initialized to an area of RAM not used for data storage. The ADuC836 contains four different memory blocks: 62 Kbytes of On-Chip Flash/EE Program Memory 4 Kbytes of On-Chip Flash/EE Data Memory 256 bytes of General-Purpose RAM 2 Kbytes of Internal XRAM 7FH (1) Flash/EE Program Memory GENERAL-PURPOSE AREA The ADuC836 provides 62 Kbytes of Flash/EE program memory to run user code. The user can choose to run code from this internal memory or run code from an external program memory. 30H 2FH BANKS SELECTED VIA BITS IN PSW If the user applies power or resets the device while the EA pin is pulled low externally, the part will execute code from the external program space; otherwise, if EA is pulled high externally, the part defaults to code execution from its internal 62 Kbytes of Flash/EE program memory. BIT-ADDRESSABLE (BIT ADDRESSES) 20H 1FH 11 18H 17H Unlike the ADuC816, where code execution can overflow from the internal code space to external code space once the PC becomes greater than 1FFFH, the ADuC836 does not support the rollover from F7FFH in internal code space to F800H in external code space. Instead, the 2048 bytes between F800H and FFFFH will appear as NOP instructions to user code. 10 10H 0FH 01 FOUR BANKS OF EIGHT REGISTERS R0–R7 08H 07H 00 Permanently embedded firmware allows code to be serially downloaded to the 62 Kbytes of internal code space via the UART serial port while the device is in-circuit. No external hardware is required. RESET VALUE OF STACK POINTER 00H Figure 2. Lower 128 Bytes of Internal Data Memory (4) Internal XRAM 56 Kbytes of the program memory can be reprogrammed during runtime; thus the code space can be upgraded in the field using a user defined protocol or it can be used as a data memory. This is discussed in more detail in the Flash/EE Memory section. (2) Flash/EE Data Memory 4 Kbytes of Flash/EE Data Memory are available to the user and can be accessed indirectly via a group of registers mapped into the Special Function Register (SFR) area. Access to the Flash/EE Data memory is discussed in detail in the Flash/EE Memory section. The ADuC836 contains 2 Kbytes of on-chip extended data memory. This memory, although on-chip, is accessed via the MOVX instruction. The 2 Kbytes of internal XRAM are mapped into the bottom 2 Kbytes of the external address space if the CFG836.0 bit is set. Otherwise, access to the external data memory will occur just like a standard 8051. Even with the CFG836.0 bit set, access to the external XRAM will occur once the 24-bit DPTR is greater than 0007FFH. (3) General-Purpose RAM FFFFFFH FFFFFFH The general-purpose RAM is divided into two separate memories: the upper and lower 128 bytes of RAM. The lower 128 bytes of RAM can be accessed through direct or indirect addressing; the upper 128 bytes of RAM can only be accessed through indirect addressing as it shares the same address space as the SFR space, which can only be accessed through direct addressing. EXTERNAL DATA MEMORY SPACE (24-BIT ADDRESS SPACE) The lower 128 bytes of internal data memory are mapped as shown in Figure 2. The lowest 32 bytes are grouped into four banks of eight registers addressed as R0 through R7. The next 16 bytes (128 bits), locations 20H through 2FH above the register banks, form a block of directly addressable bit locations at bit addresses 00H through 7FH. The stack can be located anywhere in the internal memory address space, and the stack depth can be expanded up to 2048 bytes. EXTERNAL DATA MEMORY SPACE (24-BIT ADDRESS SPACE) 000800H 0007FFH 000000H 000000H CFG836.0 = 0 2 KBYTES ON-CHIP XRAM CFG836.0 = 1 Figure 3. Internal and External XRAM GENERAL NOTES PERTAINING TO THIS DATA SHEET 1. SET implies a Logic 1 state and CLEARED implies a Logic 0 state, unless otherwise stated. 2. SET and CLEARED also imply that the bit is set or automatically cleared by the ADuC836 hardware, unless otherwise stated. 3. User software should not write 1s to reserved or unimplemented bits as they may be used in future products. 4. Any pin numbers used throughout this data sheet refer to the 52-lead MQFP package, unless otherwise stated. REV. A –13– ADuC836 SPECIAL FUNCTION REGISTERS (SFRS) When accessing the internal XRAM, the P0 and P2 port pins, as well as the RD and WR strobes, will not be output as per a standard 8051 MOVX instruction. This allows the user to use these port pins as standard I/O. The upper 1792 bytes of the internal XRAM can be configured to be used as an extended 11-bit stack pointer. By default, the stack will operate exactly like an 8052 in that it will roll over from FFH to 00H in the general-purpose RAM. On the ADuC836 however, it is possible (by setting CFG836.7) to enable the 11-bit extended stack pointer. In this case, the stack will roll over from FFH in RAM to 0100H in XRAM. The 11-bit stack pointer is visible in the SP and SPH SFRs. The SP SFR is located at 81H as with a standard 8052. The SPH SFR is located at B7H. The 3 LSBs of this SFR contain the three extra bits necessary to extend the 8-bit stack pointer into an 11-bit stack pointer. The SFR space is mapped into the upper 128 bytes of internal data memory space and accessed by direct addressing only. It provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADuC836 via the SFR area is shown in Figure 5. 8051 COMPATIBLE CORE 07FFH 256 BYTES RAM 2K XRAM UPPER 1792 BYTES OF ON-CHIP XRAM (DATA + STACK FOR EXSP = 1, DATA ONLY FOR EXSP = 0) CFG836.7 = 0 FFH 00H CFG836.7 = 1 100H 256 BYTES OF ON-CHIP DATA RAM (DATA + STACK) 4 KBYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH/EE DATA MEMORY 62 KBYTE ELECTRICALLY REPROGRAMMABLE NONVOLATILE FLASH/EE PROGRAM MEMORY 128-BYTE SPECIAL FUNCTION REGISTER AREA DUAL - ADCs OTHER ON-CHIP PERIPHERALS TEMP SENSOR CURRENT SOURCES 12-BIT DAC SERIAL I/O WDT, PSM TIC, PLL Figure 5. Programming Model All registers, except the Program Counter (PC) and the four general-purpose register banks, reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip peripherals. Accumulator SFR (ACC) LOWER 256 BYTES OF ON-CHIP XRAM (DATA ONLY) 00H Figure 4. Extended Stack Pointer Operation External Data Memory (External XRAM) Just like a standard 8051 compatible core, the ADuC836 can access external data memory using a MOVX instruction. The MOVX instruction automatically outputs the various control strobes required to access the data memory. The ADuC836, however, can access up to 16 Mbytes of external data memory. This is an enhancement of the 64 Kbytes external data memory space available on a standard 8051 compatible core. The external data memory is discussed in more detail in the ADuC836 Hardware Design Considerations section. ACC is the Accumulator Register, which is used for math operations including addition, subtraction, integer multiplication, and division, and Boolean bit manipulations. The mnemonics for accumulator-specific instructions, refer to the Accumulator as A. B SFR (B) The B Register is used with the ACC for multiplication and division operations. For other instructions, it can be treated as a general-purpose scratch pad register. Data Pointer (DPTR) The Data Pointer is made up of three 8-bit registers, named DPP (page byte), DPH (high byte), and DPL (low byte). These are used to provide memory addresses for internal and external code access and external data access. It may be manipulated as a 16-bit register (DPTR = DPH, DPL), although INC DPTR instructions will automatically carry over to DPP, or as three independent 8-bit registers (DPP, DPH, DPL). The ADuC836 supports dual data pointers. For more information, refer to the Dual Data Pointer section. –14– REV. A ADuC836 Stack Pointer (SP and SPH) Table II. PCON SFR Bit Designations The SP SFR is the stack pointer and is used to hold an internal RAM address that is called the “top of the stack.” The SP Register is incremented before data is stored, during PUSH and CALL executions. While the Stack may reside anywhere in on-chip RAM, the SP Register is initialized to 07H after a reset. This causes the stack to begin at location 08H. As mentioned earlier, the ADuC836 offers an extended 11-bit stack pointer. The three extra bits that make up the 11-bit stack pointer are the 3 LSBs of the SPH byte located at B7H. Bit Name Description 7 6 5 4 3 2 1 0 SMOD SERIPD INT0PD ALEOFF GF1 GF0 PD IDL Double UART Baud Rate SPI Power-Down Interrupt Enable INT0 Power-Down Interrupt Enable Disable ALE Output General-Purpose Flag Bit General-Purpose Flag Bit Power-Down Mode Enable Idle Mode Enable Program Status Word (PSW) The PSW SFR contains several bits reflecting the current status of the CPU as detailed in Table I. SFR Address Power-On Default Value Bit Addressable D0H 00H Yes Table I. PSW SFR Bit Designations Bit Name Description 7 6 5 4 3 CY AC F0 RS1 RS0 2 1 0 OV F1 P Carry Flag Auxiliary Carry Flag General-Purpose Flag Register Bank Select Bits RS1 RS0 Selected Bank 0 0 0 0 1 1 1 0 2 1 1 3 Overflow Flag General-Purpose Flag Parity Bit Power Control SFR (PCON) The PCON SFR contains bits for power saving options and general-purpose status flags, as shown in Table II. ADuC836 CONFIGURATION SFR (CFG836) The CFG836 SFR contains the necessary bits to configure the internal XRAM and the extended SP. By default it configures the user into 8051 mode, i.e., extended SP is disabled, internal XRAM is disabled. SFR Address Power-On Default Value Bit Addressable Table III. CFG836 SFR Bit Designations Bit Name 7 EXSP 6 5 4 3 2 1 0 The TIC (Wake-Up/RTC timer) can be used to accurately wake up the ADuC836 from power-down at regular intervals. To use the TIC to wake up the ADuC836 from power-down, the OSC_PD bit in the PLLCON SFR must be clear and the TIC must be enabled. SFR Address Power-On Default Value Bit Addressable REV. A AFH 00H No 87H 00H No –15– Description Extended SP Enable. If this bit is set, the stack will roll over from SPH/SP = 00FFH to 0100H. If this bit is clear, the SPH SFR will be disabled and the stack will roll over from SP = FFH to SP = 00H. ––– Reserved for Future Use ––– Reserved for Future Use ––– Reserved for Future Use ––– Reserved for Future Use ––– Reserved for Future Use ––– Reserved for Future Use XRAMEN XRAM Enable Bit. If this bit is set, the internal XRAM will be mapped into the lower 2 Kbytes of the external address space. If this bit is clear, the internal XRAM will not be accessible and the external data memory will be mapped into the lower 2 Kbytes of external data memory (see Figure 3). ADuC836 COMPLETE SFR MAP not implemented, i.e., no register exists at this location. If an unoccupied location is read, an unspecified value is returned. SFR locations that are reserved for future use are shaded (RESERVED) and should not be accessed by user software. Figure 6 shows a full SFR memory map and the SFR contents after RESET. NOT USED indicates unoccupied SFR locations. Unoccupied locations in the SFR address space are ISPI WCOL SPE SPIM CPOL CPHA SPR1 SPR0 FFH 0 FEH 0 FDH 0 FCH 0 FBH 0 FAH 1 F9H 0 F8H 0 F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H 0 F1H 0 F0H 0 SPICON F8H MDE MCO I2CM MDI I2CRS I2CTX RESERVED RESERVED BITS F0H EFH 0 EEH 0 EDH 0 ECH 0 EBH 0 EAH 0 E9H 0 E8H 0 E7H 0 0 E5H 0 E4H 0 E3H 0 E2H 0 E1H 0 E0H 0 0 D8H 0 BITS E8H RDY0 DFH CY D7H TF2 CFH PRE3 C7H RDY1 0 DEH AC 0 D6H EXF2 0 CEH PRE2 0 C6H PADC BFH RD B7H EA AFH 0 BEH WR 1 B6H EADC 0 AEH CAL 0 DDH NOXREF 0 DCH F0 0 D5H RSI GN0M RESERVED EAH 00H 0 CDH TCLK 0 CCH PRE1 0 C5H PRE0 PS T1 1 B5H PT1 0 BBH T0 INT1 1 B4H ET2 0 ADH WDIR 1 C3H 0 BCH 1 B3H ES ET1 0 ACH OV 0 ABH FI 0 D2H EXEN2 0 CBH 0 C4H PT2 0 BDH 0 D3H 0 D9H TR2 CNT2 0 CAH 0 C9H WDS 0 C2H PX1 0 BAH INT0 1 B2H EX1 0 AAH 0 D0H 0 0 C8H WDE 0 C1H 0 WDWR 0 C0H PT0 0 PX0 B9H 0 B8H TXD 1 B1H 0 ET0 1 EX0 0 A8H 0 SM0 1 A6H SM1 1 A5H 1 A4H SM2 1 A3H REN TB8 1 A2H 1 A1H RB8 1 A0H T1 9FH 0 9EH 0 9DH 0 9CH 0 9BH 0 9AH 0 99H 97H 1 96H 1 95H 1 94H 1 93H 1 92H 1 91H D0H 00H BITS C8H 0 98H TR1 TF0 TR0 IE1 IT1 T2 1 90H IE0 0 1 IT0 8FH 0 8EH 0 8DH 0 8CH 0 8BH 0 8AH 0 89H 0 88H 0 87H 1 86H 1 85H 1 84H 1 83H 1 82H 1 81H 1 80H 1 EBH 1 53H OF0H 00H ADC0M RESERVED 00H RESERVED RESERVED RESERVED E3H 80H ADC0H 00H DBH 00H ADCMODE ADC0CON ADC1CON D1H D2H D3H 07H RCAP2L RESERVED CAH IP BITS B8H 00H GN1L ECH 1 9AH GN1H EDH OF1L E4H 00H ADC1L 00H RESERVED RESERVED 59H OF1H E5H 80H DCH 00H SF ICON 45H D5H RESERVED TL2 CCH TH2 00H CDH EDATA1 00H PWM0H B2H PWM1L 00H B3H 00H BCH 00H PWM1H B4H 00H RESERVED RESERVED 00H A9H RESERVED RESERVED A0H TIMECON HTHSEC 2 SEC 2 MIN 2 00H EDATA3 BEH 00H RESERVED RESERVED IEIP2 00H HOUR 2 PWMCON AEH 00H INTVAL BITS A0H FFH A1H 00H A2H 00H A3H 00H RESERVED RESERVED BITS 98H 00H P1 BITS 90H 88H 99H NOT USED 00H RESERVED RESERVED 00H TMOD 89H P0 BITS 00H A5H 00H T3FD 9DH 00H A6H 00H T3CON 9EH 00H EADRH C7H 00H EDATA4 BFH 00H SPH B7H 00H CFG836 AFH 00H DPCON A7H 00H RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED FFH TCON BITS A4H SBUF 03H 00H EDATA2 BDH DEH PLLCON D7H 00H EADRL RESERVED RESERVED A8H D4H C6H 00H B1H PSMCON DFH 00H RESERVED RESERVED RESERVED PWM0L FFH RESERVED RESERVED ADC1H DDH 2H RESERVED RESERVED B9H 00H 1 CHIPID C2H IE BITS CBH ECON 00H B0H 00H RCAP2H RESERVED 10H C0H BITS 00H WDCON BITS SPIDAT RESERVED DAH 00H SCON R1 T2EX TF1 1 FDH BITS P2 A7H GN0H OF0M 00H P3 RXD 1 B0H 0 A9H D8H T2CON CAP2 1 55H E2H 00H PSW P 0 D1H BITS 00H RESERVED E0H ADCSTAT ERR1 0 DAH RS0 0 D4H RCLK ERR0 0 DBH BITS NOT USED FCH F7H ACC E6H 00H 00H I2CCON I2CI DACCON RESERVED RESERVED FBH 04H B MDO DACH DACL RESERVED RESERVED BITS 00H TL0 8AH SP TL1 00H DPL 8BH TH0 00H DPH 8CH 00H TH1 8DH RESERVED RESERVED 00H DPP PCON RESERVED RESERVED 80H FFH 81H 07H 82H 00H 83H 00H 84H 00H 87H 00H NOTES 1CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER-UP TO FACTORY CALIBRATED VALUES. 2THESE SFRs MAINTAIN THEIR PRERESET VALUES AFTER A RESET IF TIMECON.0 = 1. SFR MAP KEY: THESE BITS ARE CONTAINED IN THIS BYTE. BIT MNEMONIC BIT BIT ADDRESS RESET DEFAULT BIT VALUE IE0 89H TCON IT0 0 88H 0 88H 00H MNEMONIC RESET DEFAULT VALUE SFR ADDRESS SFR NOTE: SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT ADDRESSABLE. Figure 6. Special Function Register Locations and Their Reset Default Values –16– REV. A ADuC836 ADC SFR INTERFACE Both ADCs are controlled and configured via a number of SFRs that are summarized here and described in more detail in the following sections. ADCSTAT ADC Status Register. Holds general status of the primary and auxiliary ADCs. ADC0M/H Primary ADC 16-bit conversion result is held in these two 8-bit registers. ADCMODE ADC Mode Register. Controls general modes of operation for primary and auxiliary ADCs ADC1L/H Auxiliary ADC 16-bit conversion result is held in these two 8-bit registers. ADC0CON Primary ADC Control Register. Controls specific configuration of primary ADC. OF0M/H Primary ADC 16-bit Offset Calibration Coefficient is held in these two 8-bit registers. ADC1CON Auxiliary ADC Control Register. Controls specific configuration of auxiliary ADC. OF1L/H Auxiliary ADC 16-bit Offset Calibration Coefficient is held in these two 8-bit registers. SF Sinc Filter Register. Configures the decimation factor for the Sinc3 filter and thus the primary and auxiliary ADC update rates. GN0M/H Primary ADC 16-bit Gain Calibration Coefficient is held in these two 8-bit registers. ICON Current Source Control Register. Allows the user to control of the various on-chip current source options. GN1L/H Auxiliary ADC 16-bit Gain Calibration Coefficient is held in these two 8-bit registers. ADCSTAT (ADC Status Register) This SFR reflects the status of both ADCs including data ready, calibration, and various (ADC related) error and warning conditions such as reference detect and conversion overflow/underflow flags. SFR Address D8H Power-On Default Value 00H Bit Addressable Yes Table IV. ADCSTAT SFR Bit Designations Bit Name Description 7 RDY0 Ready Bit for Primary ADC. Set by hardware on completion of ADC conversion or calibration cycle. Cleared directly by the user or indirectly by writing to the mode bits to start another primary ADC conversion or calibration. The primary ADC is inhibited from writing further results to its data or calibration registers until the RDY0 bit is cleared. 6 RDY1 Ready Bit for Auxiliary ADC. Same definition as RDY0 referred to the auxiliary ADC. 5 CAL Calibration Status Bit. Set by hardware on completion of calibration. Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration. 4 NOXREF No External Reference Bit (only active if primary or auxiliary ADC is active). Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a specified threshold. When set, conversion results are clamped to all ones, if using external reference. Cleared to indicate valid VREF. 3 ERR0 Primary ADC Error Bit. Set by hardware to indicate that the result written to the primary ADC data registers has been clamped to all zeros or all ones. After a calibration, this bit also flags error conditions that caused the calibration registers not to be written. Cleared by a write to the mode bits to initiate a conversion or calibration. 2 ERR1 Auxiliary ADC Error Bit. Same definition as ERR0 referred to the auxiliary ADC. 1 ––– Reserved for Future Use 0 ––– Reserved for Future Use REV. A –17– ADuC836 ADCMODE (ADC Mode Register) Used to control the operational mode of both ADCs. SFR Address D1H Power-On Default Value 00H Bit Addressable No Table V. ADCMODE SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 ––– Reserved for Future Use 5 ADC0EN Primary ADC Enable. Set by the user to enable the primary ADC and place it in the mode selected in MD2–MD0, below. Cleared by the user to place the primary ADC in power-down mode. 4 ADC1EN Auxiliary ADC Enable. Set by the user to enable the auxiliary ADC and place it in the mode selected in MD2–MD0, below. Cleared by the user to place the auxiliary ADC in power-down mode. 3 ––– Reserved for Future Use 2 MD2 Primary and Auxiliary ADC Mode bits. 1 MD1 These bits select the operational mode of the enabled ADC as follows: 0 MD0 MD2 0 0 MD1 0 0 MD0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 ADC Power-Down Mode (Power-On Default) Idle Mode. The ADC filter and modulator are held in a reset state although the modulator clocks are still provided. Single Conversion Mode. A single conversion is performed on the enabled ADC. On completion of the conversion, the ADC data registers (ADC0H/M and/or ADC1H/L) are updated, the relevant flags in the ADCSTAT SFR are written, and power-down is re-entered with the MD2–MD0 accordingly being written to 000. Continuous Conversion. The ADC data registers are regularly updated at the selected update rate (see SF Register). Internal Zero-Scale Calibration. Internal short automatically connected to the enabled ADC input(s). Internal Full-Scale Calibration. Internal or external VREF (as determined by XREF0 and XREF1 bits in ADC0/1CON) is automatically connected to the enabled ADC input(s) for this calibration. System Zero-Scale Calibration. User should connect system zero-scale input to the enabled ADC input(s) as selected by CH1/CH0 and ACH1/ACH0 bits in the ADC0/1CON Register. System Full-Scale Calibration. User should connect system full-scale input to the enabled ADC input(s) as selected by the CH1/CH0 and ACH1/ACH0 bits in the ADC0/1CON Register. NOTES 1. Any change to the MD bits will immediately reset both ADCs. A write to the MD2–0 bits with no change is also treated as a reset. (See exception to this in Note 3.) 2. If ADC0CON is written when ADC0EN = 1, or if ADC0EN is changed from 0 to 1, then both ADCs are also immediately reset. In other words, the primary ADC is given priority over the auxiliary ADC, and any change requested on the primary ADC is immediately responded to. 3. On the other hand, if ADC1CON is written or if ADC1EN is changed from 0 to 1, only the auxiliary ADC is reset. For example, if the primary ADC is continuously converting when the auxiliary ADC change or enable occurs, the primary ADC continues undisturbed. Rather than allow the auxiliary ADC to operate with a phase difference from the primary ADC, the auxiliary ADC will fall into step with the outputs of the primary ADC. The result is that the first conversion time for the auxiliary ADC will be delayed up to three outputs while the auxiliary ADC update rate is synchronized to the primary ADC. 4. Once ADCMODE has been written with a calibration mode, the RDY0/1 bits (ADCSTAT) are immediately reset and the calibration commences. On completion, the appropriate calibration registers are written, the relevant bits in ADCSTAT are written, and the MD2–0 bits are reset to 000 to indicate the ADC is back in Power-Down mode. 5. Any calibration request of the auxiliary ADC while the temperature sensor is selected will fail to complete. Although the RDY1 bit will be set at the end of the calibration cycle, no update of the calibration SFRs will take place and the ERR1 bit will be set. 6. Calibrations are performed at maximum SF (see SF SFR) value, guaranteeing optimum calibration operation. –18– REV. A ADuC836 ADC0CON (Primary ADC Control Register) and ADC1CON (Auxiliary ADC Control Register) The ADC0CON and ADC1CON SFRs are used to configure the primary and auxiliary ADC for reference and channel selection, unipolar or bipolar coding and, in the case of the primary ADC, range (the auxiliary ADC operates on a fixed input range of ±VREF). ADC0CON Primary ADC Control SFR ADC1CON Auxiliary ADC Control SFR SFR Address D2H SFR Address D3H Power-On Default Value 07H Power-On Default Value 00H Bit Addressable No Bit Addressable No Table VI. ADC0CON SFR Bit Designations Bit Name Description 7 6 ––– XREF0 5 4 CH1 CH0 3 UNI0 2 1 0 RN2 RN1 RN0 Reserved for Future Use Primary ADC External Reference Select Bit. Set by user to enable the primary ADC to use the external reference via REFIN(+)/REFIN(–). Cleared by user to enable the primary ADC to use the internal band gap reference (VREF = 1.25 V). Primary ADC Channel Selection Bits. Written by the user to select the differential input pairs used by the primary ADC as follows: CH1 CH0 Positive Input Negative Input 0 0 AIN1 AIN2 0 1 AIN3 AIN4 1 0 AIN2 AIN2 (Internal Short) 1 1 AIN3 AIN2 Primary ADC Unipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in 000000H output. Cleared by user to enable bipolar coding, i.e., zero differential input will result in 800000H output. Primary ADC Range Bits. Written by the user to select the primary ADC input range as follows: RN2 RN1 RN0 Selected Primary ADC Input Range (VREF = 2.5 V) 0 0 0 ±20 mV (0 mV–20 mV in Unipolar Mode) 0 0 1 ±40 mV (0 mV–40 mV in Unipolar Mode) 0 1 0 ±80 mV (0 mV–80 mV in Unipolar Mode) 0 1 1 ±160 mV (0 mV–160 mV in Unipolar Mode) 1 0 0 ±320 mV (0 mV–320 mV in Unipolar Mode) 1 0 1 ±640 mV (0 mV–640 mV in Unipolar Mode) 1 1 0 ±1.28 V (0 V–1.28 V in Unipolar Mode) 1 1 1 ±2.56 V (0 V–2.56 V in Unipolar Mode) Table VII. ADC1CON SFR Bit Designations Bit Name Description 7 6 ––– XREF1 5 4 ACH1 ACH0 3 UNI1 2 1 0 ––– ––– ––– Reserved for Future Use Auxiliary ADC External Reference Bit. Set by user to enable the auxiliary ADC to use the external reference via REFIN(+)/REFIN(–). Cleared by user to enable the auxiliary ADC to use the internal band gap reference. Auxiliary ADC Channel Selection Bits. Written by the user to select the single-ended input pins used to drive the auxiliary ADC as follows: ACH1 ACH0 Positive Input Negative Input 0 0 AIN3 AGND 0 1 AIN4 AGND 1 0 Temp Sensor AGND (Temp Sensor routed to the ADC input) 1 1 AIN5 AGND Auxiliary ADC Unipolar Bit. Set by user to enable unipolar coding, i.e., zero input will result in 0000H output. Cleared by user to enable bipolar coding, i.e., zero input will result in 8000H output. Reserved for Future Use Reserved for Future Use Reserved for Future Use NOTES 1. When the temperature sensor is selected, user code must select internal reference via XREF1 bit above and clear the UNI1 bit (ADC1CON.3) to select bipolar coding. 2. The temperature sensor is factory calibrated to yield conversion results 8000H at 0°C. 3. A +1°C change in temperature will result in a +1 LSB change in the ADC1H Register ADC conversion result. REV. A –19– ADuC836 ADC0H/ADC0M (Primary ADC Conversion Result Registers) These two 8-bit registers hold the 16-bit conversion result from the primary ADC. SFR Address Power-On Default Value Bit Addressable ADC0H ADC0M 00H No High Data Byte Middle Data Byte ADC0H, ADC0M ADC0H, ADC0M DBH DAH ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers) These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC. SFR Address Power-On Default Value Bit Addressable ADC1H ADC1L 00H No High Data Byte Low Data Byte ADC1H, ADC1L ADC1H, ADC1L DDH DCH OF0H/OF0M (Primary ADC Offset Calibration Registers*) These two 8-bit registers hold the 16-bit offset calibration coefficient for the primary ADC. These registers are configured at power-on with a factory default value of 800000H. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register. SFR Address Power-On Default Value Bit Addressable OF0H OF0M 80000H No Primary ADC Offset Coefficient High Byte Primary ADC Offset Coefficient Middle Byte OF0H, OF0M respectively OF0H, OF0M E3H E2H OF1H/OF1L (Auxiliary ADC Offset Calibration Registers*) These two 8-bit registers hold the 16-bit offset calibration coefficient for the auxiliary ADC. These registers are configured at power-on with a factory default value of 8000H. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration of the auxiliary ADC is initiated by the user via the MD2–0 bits in the ADCMODE Register. SFR Address Power-On Default Value Bit Addressable OF1H OF1L 8000H No Auxiliary ADC Offset Coefficient High Byte Auxiliary ADC Offset Coefficient Low Byte OF1H and OF1L, respectively OF1H, OF1L E5H E4H GN0H/GN0M (Primary ADC Gain Calibration Registers*) These two 8-bit registers hold the 16-bit gain calibration coefficient for the primary ADC. These registers are configured at power-on with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these bytes will be automatically overwritten if an internal or system full-scale calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register. SFR Address Power-On Default Value Bit Addressable GN0H GN0M No Primary ADC Gain Coefficient High Byte Primary ADC Gain Coefficient Middle Byte Configured at Factory Final Test; See Notes above. GN0H, GN0M EBH EAH GN1H/GN1L (Auxiliary ADC Gain Calibration Registers*) These two 8-bit registers hold the 16-bit gain calibration coefficient for the auxiliary ADC. These registers are configured at power-on with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these bytes will be automatically overwritten if an internal or system full-scale calibration of the auxiliary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register. SFR Address Power-On Default Value Bit Addressable GN1H GN1L No Auxiliary ADC Gain Coefficient High Byte Auxiliary ADC Gain Coefficient Low Byte Configured at Factory Final Test; see notes above. GN1H, GN1L EDH ECH *These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero. –20– REV. A ADuC836 SF (Sinc Filter Register) The number in this register sets the decimation factor and thus the output update rate for the primary and auxiliary ADCs. This SFR cannot be written by user software while either ADC is active. The update rate applies to both primary and auxiliary ADCs and is calculated as follows: f ADC = where: 1 1 × × f MOD 3 8 × SF value for the SF Register is 45H, resulting in a default ADC update rate of just under 20 Hz. Both ADC inputs are chopped to minimize offset errors, which means that the settling time for a single conversion, or the time to a first conversion result in Continuous Conversion mode, is 2 tADC. As mentioned earlier, all calibration cycles will be carried out automatically with a maximum, i.e., FFH, SF value to ensure optimum calibration performance. Once a calibration cycle has completed, the value in the SF Register will be that programmed by user software. fADC = ADC Output Update Rate fMOD = Modulator Clock Frequency = 32.768 kHz SF = Decimal Value of SF Register The allowable range for SF is 0DH to FFH. Examples of SF values and corresponding conversion update rates (fADC) and conversion times (tADC) are shown in Table VIII. The power-on default Table VIII. SF SFR Bit Designations SF(dec) SF(hex) fADC(Hz) tADC(ms) 13 69 255 0D 45 FF 105.3 19.79 5.35 9.52 50.34 186.77 ICON (Current Sources Control Register) The icon SFR is used to control and configure the various excitation and burnout current source options available on-chip. SFR Address Power-On Default Value Bit Addressable D5H 00H No Table IX. ICON SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 BO Burnout Current Enable Bit. Set by user to enable both transducer burnout current sources in the primary ADC signal paths. Cleared by the user to disable both transducer burnout current sources. 5 ADC1IC Auxiliary ADC Current Correction Bit. Set by user to allow scaling of the auxiliary ADC by an internal current source calibration word. 4 ADC0IC Primary ADC Current Correction Bit. Set by user to allow scaling of the primary ADC by an internal current source calibration word. 3 I2PIN* Current Source-2 Pin Select Bit. Set by user to enable current source-2 (200 A) to external Pin 3 (P1.2/DAC/IEXC1). Cleared by user to enable current source-2 (200 A) to external Pin 4 (P1.3/AIN5/IEXC2). 2 I1PIN* Current Source-1 Pin Select Bit. Set by user to enable current source-1 (200 A) to external Pin 4 (P1.3/AIN5/IEXC2). Cleared by user to enable current source-1 (200 A) to external Pin 3 (P1.2/DAC/IEXC1). 1 I2EN Current Source-2 Enable Bit. Set by user to turn on excitation current source-2 (200 A). Cleared by user to turn off excitation current source-2 (200 A). 0 I1EN Current Source-1 Enable Bit. Set by user to turn on excitation current source-1 (200 A). Cleared by user to turn off excitation current source-1 (200 A). *Both current sources can be enabled to the same external pin, yielding a 400 A current source. REV. A –21– ADuC836 PRIMARY AND AUXILIARY ADC NOISE PERFORMANCE via the Sinc Filter (SF) SFR. It is important to note that the peak-to-peak resolution figures represent the resolution for which there will be no code flicker within a six-sigma limit. Tables X, XI, and XII show the output rms noise in mV and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for some typical output update rates on both the primary and auxiliary ADCs. The numbers are typical and are generated at a differential input voltage of 0 V. The output update rate is selected The QuickStart Development system PC software comes complete with an ADC noise evaluation tool. This tool can be easily used with the evaluation board to see these figures from silicon. Table X. Primary ADC, Typical Output RMS Noise (V) Typical Output RMS Noise vs. Input Range and Update Rate; Output RMS Noise in V SF Word Data Update Rate (Hz) 20 mV 40 mV 80 mV Input Range 160 mV 320 mV 640 mV 1.28 V 2.56 V 13 69 255 105.3 19.79 5.35 1.50 0.60 0.35 1.50 0.65 0.35 1.60 0.65 0.37 1.75 0.65 0.37 3.50 0.65 0.37 4.50 0.95 0.51 6.70 1.40 0.82 11.75 2.30 1.25 Table XI. Primary ADC, Peak-to-Peak Resolution (Bits) Peak-to-Peak Resolution vs. Input Range and Update Rate; Peak-to-Peak Resolution in Bits SF Word Data Update Rate (Hz) 20 mV 40 mV 80 mV Input Range 160 mV 320 mV 640 mV 1.28 V 2.56 V 13 69 255 105.3 19.79 5.35 12 13.5 14 13 14 15 14 15 16 15 16 16 15 16 16 15.5 16 16 16 16 16 16 16 16 Typical RMS Resolution vs. Input Range and Update Rate: RMS Resolution in Bits* SF Word Data Update Rate (Hz) 20 mV 40 mV 80 mV Input Range 160 mV 320 mV 640 mV 1.28 V 2.56 V 13 69 255 105.3 19.79 5.35 14.7 16 16 15.7 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 *Based on a six-sigma limit, the rms resolution is 2.7 bits greater than the peak-to-peak resolution. Table XII. Auxiliary ADC Peak-to-Peak Resolution vs. Update Rate1 Peak-to-Peak Resolution in Bits Typical Output RMS Noise vs. Update Rate* Output RMS Noise in V SF Data Update Rate (Hz) Input Range Word 2.5 V SF Word Data Update Rate (Hz) Input Range 2.5 V 13 69 255 105.3 19.79 5.35 10.75 2.00 1.15 13 69 255 105.3 19.79 5.35 162 16 16 *ADC converting in Bipolar mode NOTES 1 ADC converting in Bipolar mode 2 In Unipolar mode, peak-to-peak resolution at 105 Hz is 15 bits. –22– REV. A ADuC836 PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION Overview The ADuC836 incorporates two independent - ADCs (primary and auxiliary) with on-chip digital filtering intended for the measurement of wide dynamic range, low frequency signals such as those in weigh-scale, strain gage, pressure transducer, or temperature measurement applications. Primary ADC This ADC is intended to convert the primary sensor input. The input is buffered and can be programmed for one of eight input ranges from ±20 mV to ±2.56 V being driven from one of three differential input channel options AIN1/2, AIN3/4, or AIN3/2. The input channel is internally buffered, allowing the part to handle significant source impedances on the analog input and PROGRAMMABLE GAIN AMPLIFIER ANALOG INPUT CHOPPING BURNOUT CURRENTS TWO 100nA BURNOUT CURRENTS ALLOW THE USER TO EASILY DETECT IF A TRANSDUCER HAS BURNED OUT OR GONE OPEN-CIRCUIT. THE PROGRAMMABLE GAIN AMPLIFIER ALLOWS EIGHT UNIPOLAR AND EIGHT BIPOLAR INPUT RANGES FROM 20mV TO 2.56V (EXT V REF = 2.5V). THE INPUTS ARE ALTERNATELY REVERSED THROUGH THE CONVERSION CYCLE. CHOPPING YIELDS EXCELLENT ADC OFFSET AND OFFSET DRIFT PERFORMANCE. allowing R/C filtering (for noise rejection or RFI reduction) to be placed on the analog inputs if required. On-chip burnout currents can also be turned on. These currents can be used to check that a transducer on the selected channel is still operational before attempting to take measurements. The ADC employs a - conversion technique to realize up to 16 bits of no missing codes performance. The - modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital information. A Sinc3 programmable low-pass filter is then employed to decimate the modulator output data stream to give a valid data conversion result at programmable output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms). A chopping scheme is also employed to minimize ADC offset errors. A block diagram of the primary ADC is shown in Figure 7. DIFFERENTIAL REFERENCE THE EXTERNAL REFERENCE INPUT TO THE ADuC836 IS DIFFERENTIAL AND FACILITATES RATIOMETRIC OPERATION. THE EXTERNAL REFERENCE VOLTAGE IS SELECTED VIA THE XREF0 BIT IN ADC0CON. REFERENCE DETECT CIRCUITRY TESTS FOR OPEN OR SHORTED REFERENCE INPUTS. - ADC OUTPUT AVERAGE THE - ARCHITECTURE ENSURES 24 BITS NO MISSING CODES. THE ENTIRE - ADC IS CHOPPED TO REMOVE DRIFT ERROR. AS PART OF THE CHOPPING IMPLEMENTATION, EACH DATA-WORD OUTPUT FROM THE FILTER IS SUMMED AND AVERAGED WITH ITS PREDECESSOR TO NULL ADC CHANNEL OFFSET ERRORS. REFIN(–) REFIN(+) AVDD - ADC AIN1 AIN2 BUFFER MUX PGA - MODULATOR PROGRAMMABLE DIGITAL FILTER OUTPUT AVERAGE OUTPUT SCALING DIGTAL OUTPUT RESULT WRITTEN TO ADC0H/M/L SFRS AIN3 CHOP AIN4 AGND CHOP OUTPUT SCALING ANALOG MULTIPLEXER A DIFFERENTIAL MULTIPLEXER ALLOWS SELECTION OF THREE FULLY DIFFERENTIAL PAIR OPTIONS AND ADDITIONAL INTERNAL SHORT OPTION (AIN2–AIN2). THE MULTIPLEXER IS CONTROLLED VIA THE CHANNEL SELECTION BITS IN ADC0CON. BUFFER AMPLIFIER THE BUFFER AMPLIFIER PRESENTS A HIGH IMPEDANCE INPUT STAGE FOR THE ANALOG INPUTS, ALLOWING SIGNIFICANT EXTERNAL SOURCE IMPEDANCES. PROGRAMMABLE DIGITAL FILTER - MODULATOR THE MODULATOR PROVIDES A HIGH FREQUENCY 1-BIT DATA STREAM (THE OUTPUT OF WHICH IS ALSO CHOPPED) TO THE DIGITAL FILTER, THE DUTY CYCLE OF WHICH REPRESENTS THE SAMPLED ANALOG INPUT VOLTAGE. THE SINC3 FILTER REMOVES QUANTIZATION NOISE INTRODUCED BY THE MODULATOR. THE UPDATE RATE AND BANDWIDTH OF THIS FILTER ARE PROGRAMMABLE VIA THE SF SFR. Figure 7. Primary ADC Block Diagram REV. A –23– THE OUPUT WORD FROM THE DIGITAL FILTER IS SCALED BY THE CALIBRATION COEFFICIENTS BEFORE BEING PROVIDED AS THE CONVERSION RESULT. ADuC836 Auxiliary ADC The auxiliary ADC is intended to convert supplementary inputs such as those from a cold junction diode or thermistor. This ADC is not buffered and has a fixed input range of 0 V to 2.5 V (assuming an external 2.5 V reference). The single-ended inputs can be driven from AIN3, AIN4, or AIN5 pins, or directly from the on-chip temperature sensor voltage. A block diagram of the auxiliary ADC is shown in Figure 8. Analog Input Channels The primary ADC has four associated analog input pins (labeled AIN1 to AIN4) that can be configured as two fully differential input channels. Channel selection bits in the ADC0CON SFR detailed in Table VI allow three combinations of differential pair selection as well as an additional shorted input option (AIN2–AIN2). The auxiliary ADC has three external input pins (labeled AIN3 to AIN5) as well as an internal connection to the on-chip temperature sensor. All inputs to the auxiliary ADC are single-ended inputs referenced to the AGND on the part. Channel selection bits in the ADC1CON SFR detailed in Table VII allow selection of one of four inputs. Two input multiplexers switch the selected input channel to the on-chip buffer amplifier in the case of the primary ADC and directly to the - modulator input in the case of the auxiliary ADC. When the analog input channel is switched, the settling time of the part must elapse before a new valid word is available from the ADC. DIFFERENTIAL REFERENCE ANALOG INPUT CHOPPING THE INPUTS ARE ALTERNATELY REVERSED THROUGH THE CONVERSION CYCLE. CHOPPING YIELDS EXCELLENT ADC OFFSET AND OFFSET DRIFT PERFORMANCE. THE EXTERNAL REFERENCE INPUT TO THE ADuC836 IS DIFFERENTIAL AND FACILITATES RATIOMETRIC OPERATION. THE EXTERNAL REFERENCE VOLTAGE IS SELECTED VIA THE XREF1 BIT IN ADC1CON. REFERENCE DETECT CIRCUITRY TESTS FOR OPEN OR SHORTED REFERENCE INPUTS. OUTPUT AVERAGE - ADC AS PART OF THE CHOPPING IMPLEMENTATION, EACH DATA-WORD OUTPUT FROM THE FILTER IS SUMMED AND AVERAGED WITH ITS PREDECESSOR TO NULL ADC CHANNEL OFFSET ERRORS. THE - ARCHITECTURE ENSURES 16 BITS NO MISSING CODES. THE ENTIRE - ADC IS CHOPPED TO REMOVE DRIFT ERRORS. REFIN(–) REFIN(+) - ADC AIN3 AIN4 AIN5 ON-CHIP TEMPERATURE SENSOR - MODULATOR MU PROGRAMMABLE DIGITAL FILTER OUTPUT AVERAGE OUTPUT SCALING DIGTAL OUTPUT RESULT WRITTEN TO ADC1H/L SFRs MUX X CHOP CHOP OUTPUT SCALING ANALOG MULTIPLEXER A DIFFERENTIAL MULTIPLEXER ALLOWS SELECTION OF THREE EXTERNAL SINGLE ENDED INPUTS OR THE ON-CHIP TEMP. SENSOR. THE MULTIPLEXER IS CONTROLLED VIA THE CHANNEL SELECTION BITS IN ADC1CON. PROGRAMMABLE DIGITAL FILTER - MODULATOR THE SINC3 FILTER REMOVES QUANTIZATION NOISE INTRODUCED BY THE MODULATOR. THE UPDATE RATE AND BANDWIDTH OF THIS FILTER ARE PROGRAMMABLE VIA THE SF SFR. THE MODULATOR PROVIDES A HIGH FREQUENCY 1-BIT DATA STREAM (THE OUTPUT OF WHICH IS ALSO CHOPPED) TO THE DIGITAL FILTER, THE DUTY CYCLE OF WHICH REPRESENTS THE SAMPLED ANALOG INPUT VOLTAGE. THE OUPUT WORD FROM THE DIGITAL FILTER IS SCALED BY THE CALIBRATION COEFFICIENTS BEFORE BEING PROVIDED AS THE CONVERSION RESULT. Figure 8. Auxiliary ADC Block Diagram –24– REV. A ADuC836 Primary and Auxiliary ADC Inputs 19.372 The output of the Primary ADC multiplexer feeds into a high impedance input stage of the buffer amplifier. As a result, the primary ADC inputs can handle significant source impedances and are tailored for direct connection to external resistive-type sensors like strain gages or Resistance Temperature Detectors (RTDs). ADC INPUT VOLTAGE – mV 19.371 The auxiliary ADC, however, is unbuffered, resulting in higher analog input current on the auxiliary ADC. It should be noted that this unbuffered input path provides a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input pins can cause dc gain errors depending on the output impedance of the source that is driving the ADC inputs. 19.367 19.366 800 2.56V 700 1.28V 600 640mV 500 320mV 400 160mV 300 80mV 200 40mV 100 20mV ADC RANGE Figure 9. Primary ADC Range Matching The absolute input voltage range on the auxiliary ADC is restricted to between AGND – 30 mV to AVDD + 30 mV. The slightly negative absolute input voltage limit does allow the possibility of monitoring small signal bipolar signals using the single-ended auxiliary ADC front end. Programmable Gain Amplifier The output from the buffer on the primary ADC is applied to the input of the on-chip programmable gain amplifier (PGA). The PGA can be programmed through eight different unipolar input ranges and bipolar ranges. The PGA gain range is programmed via the range bits in the ADC0CON SFR. With the external reference select bit set in the ADC0CON SFR and an external 2.5 V reference, the unipolar ranges are 0 mV to 20 mV, 0 mV to 40 mV, 0 mV to 80 mV, 0 mV to 160 mV, 0 mV to 320 mV, 0 mV to 640 mV, 0 V to 1.28 V, and 0 to 2.56 V; the bipolar ranges are ±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV, ±1.28 V, and ±2.56 V. These are the nominal ranges that should appear at the input to the on-chip PGA. An ADC range matching specification of 2 µV (typ) across all ranges means that calibration need only be carried out at a single gain range and does not have to be repeated when the PGA gain range is changed. REV. A 19.368 19.364 SAMPLE COUNT 0 The absolute input voltage range on the primary ADC is restricted to between AGND + 100 mV to AVDD – 100 mV. Care must be taken in setting up the common-mode voltage and input voltage range so that these limits are not exceeded; otherwise there will be a degradation in linearity performance. The auxiliary ADC does not incorporate a PGA and is configured for a fixed single input range of 0 to VREF. 19.369 19.365 Analog Input Ranges Typical matching across ranges is shown in Figure 9. Here, the primary ADC is configured in bipolar mode with an external 2.5 V reference, while just greater than 19 mV is forced on its inputs. The ADC continuously converts the dc input voltage at an update rate of 5.35 Hz, i.e., SF = FFH. In total, 800 conversion results are gathered. The first 100 results are gathered with the primary ADC operating in the ±20 mV range. The ADC range is then switched to ±40 mV, 100 more conversion results are gathered, and so on, until the last group of 100 samples is gathered with the ADC configured in the ±2.56 V range. From Figure 9, the variation in the sample mean through each range, i.e., the range matching, is seen to be of the order of 2 V. 19.370 Bipolar/Unipolar Inputs The analog inputs on the ADuC836 can accept either unipolar or bipolar input voltage ranges. Bipolar input ranges do not imply that the part can handle negative voltages with respect to system AGND. Unipolar and bipolar signals on the AIN(+) input on the primary ADC are referenced to the voltage on the respective AIN(–) input. For example, if AIN(–) is 2.5 V and the primary ADC is configured for an analog input range of 0 mV to 20 mV, the input voltage range on the AIN(+) input is 2.5 V to 2.52 V. If AIN(–) is 2.5 V and the ADuC836 is configured for an analog input range of 1.28 V, the analog input range on the AIN(+) input is 1.22 V to 3.78 V (i.e., 2.5 V ± 1.28 V). As mentioned earlier, the auxiliary ADC input is a single-ended input with respect to the system AGND. In this context, a bipolar signal on the auxiliary ADC can only span 30 mV negative with respect to AGND before violating the voltage input limits for this ADC. Bipolar or unipolar options are chosen by programming the primary and auxiliary Unipolar enable bits in the ADC0CON and ADC1CON SFRs, respectively. This programs the relevant ADC for either unipolar or bipolar operation. Programming for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding and the points on the transfer function where calibrations occur. When an ADC is configured for unipolar operation, the output coding is natural (straight) binary with a zero differential input voltage resulting in a code of 000 . . . 000, a midscale voltage resulting in a code of 100 . . . 000, and a full-scale input voltage resulting in a code of 111 . . . 111. When an ADC is configured for bipolar operation, the coding is offset binary with a negative full-scale voltage resulting in a code of 000 . . . 000, a zero differential voltage resulting in a code of 100 . . . 000, and a positive full-scale voltage resulting in a code of 111 . . . 111. –25– ADuC836 Reference Input Excitation Currents The ADuC836’s reference inputs, REFIN(+) and REFIN(–), provide a differential reference input capability. The commonmode range for these differential inputs is from AGND to AVDD. The nominal reference voltage, VREF (REFIN(+) – REFIN(–)), for specified operation is 2.5 V with the primary and auxiliary reference enable bits set in the respective ADC0CON and/or ADC1CON SFRs. The ADuC836 also contains two identical, 200 µA constant current sources. Both source current from AVDD to Pin 3 (IEXC1) or Pin 4 (IEXC2). These current sources are controlled via bits in the ICON SFR shown in Table IX. They can be configured to source 200 µA individually to both pins or a combination of both currents, i.e., 400 µA, to either of the selected pins. These current sources can be used to excite external resistive bridge or RTD sensors. The part is also functional (although not specified for performance) when the XREF0 or XREF1 bits are 0, which enables the on-chip internal band gap reference. In this mode, the ADCs will see the internal reference of 1.25 V, therefore halving all input ranges. As a result of using the internal reference voltage, a noticeable degradation in peak-to-peak resolution will result. Therefore, for best performance, operation with an external reference is strongly recommended. Reference Detect In applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source will be removed as the application is ratiometric. If the ADuC836 is not used in a ratiometric application, a low noise reference should be used. Recommended reference voltage sources for the ADuC836 include the AD780, REF43, and REF192. It should also be noted that the reference inputs provide a high impedance, dynamic load. Because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors depending on the output impedance of the source that is driving the reference inputs. Reference voltage sources, like those recommended above (e.g., AD780), will typically have low output impedances and therefore decoupling capacitors on the REFIN(+) input would be recommended. Deriving the reference input voltage across an external resistor, as shown in Figure 66, will mean that the reference input sees a significant external source impedance. External decoupling on the REFIN(+) and REFIN(–) pins would not be recommended in this type of circuit configuration. The ADuC836 includes on-chip circuitry to detect if the part has a valid reference for conversions or calibrations. If the voltage between the external REFIN(+) and REFIN(–) pins goes below 0.3 V or either the REFIN(+) or REFIN(–) inputs is open circuit, the ADuC836 detects that it no longer has a valid reference. In this case, the NOXREF bit of the ADCSTAT SFR is set to a 1. If the ADuC836 is performing normal conversions and the NOXREF bit becomes active, the conversion results revert to all 1s. It is not necessary to continuously monitor the status of the NOXREF bit when performing conversions. It is only necessary to verify its status if the conversion result read from the ADC Data Register is all 1s. If the ADuC836 is performing either an offset or gain calibration and the NOXREF bit becomes active, the updating of the respective calibration registers is inhibited to avoid loading incorrect coefficients to these registers, and the appropriate ERR0 or ERR1 bits in the ADCSTAT SFR are set. If the user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the ERR0 or ERR1 bit should be checked at the end of the calibration cycle. - Modulator A - ADC generally consists of two main blocks, an analog modulator and a digital filter. In the case of the ADuC836 ADCs, the analog modulators consist of a difference amplifier, an integrator block, a comparator, and a feedback DAC, as illustrated in Figure 10. ANALOG INPUT COMPARATOR INTEGRATOR Burnout Currents The primary ADC on the ADuC836 contains two 100 nA constant current generators: one sourcing current from AVDD to AIN(+) and one sinking from AIN(–) to AGND. The currents are switched to the selected analog input pair. Both currents are either on or off, depending on the Burnout Current Enable (BO) bit in the ICON SFR (see Table IX). These currents can be used to verify that an external transducer is still operational before attempting to take measurements on that channel. Once the burnout currents are turned on, they will flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. If the resultant voltage measured is full-scale, it indicates that the transducer has gone open-circuit. If the voltage measured is 0 V, it indicates that the transducer has short circuited. For normal operation, these burnout currents are turned off by writing a 0 to the BO bit in the ICON SFR. The current sources work over the normal absolute input voltage range specifications. DIFFERENCE AMP HIGH FREQUENCY BIT STREAM TO DIGITAL FILTER DAC Figure 10. - Modulator Simplified Block Diagram In operation, the analog signal sample is fed to the difference amplifier along with the output of the feedback DAC. The difference between these two signals is integrated and fed to the comparator. The output of the comparator provides the input to the feedback DAC so the system functions as a negative feedback loop that tries to minimize the difference signal. The digital data that represents the analog input voltage is contained in the duty cycle of the pulse train appearing at the output of the comparator. This duty cycle data can be recovered as a data-word using a subsequent digital filter stage. The sampling frequency of the modulator loop is many times higher than the bandwidth of the input signal. The integrator in the modulator shapes the quantization noise (which results from the analog-to-digital conversion) so that the noise is pushed toward one-half of the modulator frequency. –26– REV. A ADuC836 Digital Filter 0 The output of the - modulator feeds directly into the digital filter. The digital filter then band-limits the response to a frequency significantly lower than one-half of the modulator frequency. In this manner, the 1-bit output of the comparator is translated into a band-limited, low noise output from the ADuC836 ADCs. –10 –20 –30 GAIN – dB –40 The ADuC836 filter is a low-pass, SIN3 or (SINx/x)3 filter whose primary function is to remove the quantization noise introduced at the modulator. The cutoff frequency and decimated output data rate of the filter are programmable via the SF (Sinc Filter) SFR, as described in Table VIII. –70 –90 –100 –110 –120 0 10 20 30 70 80 90 110 Figures 13 and 14 show the NMR for 50 Hz and 60 Hz across the full range of SF word, i.e., SF = 13 dec to SF = 255 dec. 0 –10 –20 –30 GAIN – dB –40 0 –10 –20 –50 –60 –70 –80 –30 –90 –40 –100 –50 –110 –60 –120 10 –70 30 50 70 90 –80 –90 110 130 150 170 190 210 230 250 SF – Decimal Figure 13. 50 Hz Normal Mode Rejection vs. SF –100 0 –110 –120 40 50 60 FREQUENCY – Hz Figure 12. Filter Response, SF = 255 dec It should also be noted that rejection of mains related frequency components, i.e., 50 Hz and 60 Hz, is seen to be at a level of >65 dB at 50 Hz and >100 dB at 60 Hz. This confirms the data sheet specifications for 50 Hz/60 Hz Normal Mode Rejection (NMR) at a 20 Hz update rate. GAIN – dB –60 –80 Figure 11 shows the frequency response of the ADC channel at the default SF word of 69 dec or 45H, yielding an overall output update rate of just under 20 Hz. It should be noted that this frequency response allows frequency components higher than the ADC Nyquist frequency to pass through the ADC, in some cases without significant attenuation. These components may, therefore, be aliased and appear in-band after the sampling process. –50 –10 0 10 20 30 40 50 60 70 FREQUENCY – Hz 80 90 100 110 –20 –30 Figure 11. Filter Response, SF = 69 dec GAIN – dB –40 The response of the filter, however, will change with SF word, as can be seen in Figure 12, which shows >90 dB NMR at 50 Hz and >70 dB NMR at 60 Hz when SF = 255 dec. –50 –60 –70 –80 –90 –100 –110 –120 10 30 50 70 90 110 130 150 170 190 210 230 250 SF – Decimal Figure 14. 60 Hz Normal Mode Rejection vs. SF REV. A –27– ADuC836 ADC Chopping Both ADCs on the ADuC836 implement a chopping scheme whereby the ADC repeatedly reverses its inputs. The decimated digital output words from the Sinc3 filters therefore have a positive offset and negative offset term included. As a result, a final summing stage is included in each ADC so that each output word from the filter is summed and averaged with the previous filter output to produce a new valid output result to be written to the ADC data SFRs. In this way, while the ADC throughput or update rate is as discussed earlier and illustrated in Table VIII, the full settling time through the ADC (or the time to a first conversion result) will actually be given by 2 tADC. The chopping scheme incorporated in the ADuC836 ADC results in excellent dc offset and offset drift specifications and is extremely beneficial in applications where drift, noise rejection, and optimum EMI rejection are important factors. Calibration The ADuC836 provides four calibration modes that can be programmed via the mode bits in the ADCMODE SFR detailed in Table V. In fact, every ADuC836 has already been factory calibrated. The resultant Offset and Gain calibration coefficients for both the primary and auxiliary ADCs are stored on-chip in manufacturing-specific Flash/EE memory locations. At power-on or after reset, these factory calibration coefficients are automatically downloaded to the calibration registers in the ADuC836 SFR space. Each ADC (primary and auxiliary) has dedicated calibration SFRs, which have been described earlier as part of the general ADC SFR description. However, the factory calibration values in the ADC calibration SFRs will be overwritten if any one of the four calibration options are initiated and that ADC is enabled via the ADC enable bits in ADCMODE. Even though an internal offset calibration mode is described below, it should be recognized that both ADCs are chopped. This chopping scheme inherently minimizes offset and means that an internal offset calibration should never be required. Also, because factory 5 V/25°C gain calibration coefficients are automatically present at power-on an internal full-scale calibration will only be required if the part is being operated at 3 V or at temperatures significantly different from 25°C. The ADuC836 offers internal or system calibration facilities. For full calibration to occur on the selected ADC, the calibration logic must record the modulator output for two different input conditions: zero-scale and full-scale points. These points are derived by performing a conversion on the different input voltages provided to the input of the modulator during calibration. The result of the zero-scale calibration conversion is stored in the Offset Calibration Registers for the appropriate ADC. The result of the full-scale calibration conversion is stored in the Gain Calibration Registers for the appropriate ADC. With these readings, the calibration logic can calculate the offset and the gain slope for the input-to-output transfer function of the converter. During an internal zero-scale or full-scale calibration, the respective zero-scale input and full-scale inputs are automatically connected to the ADC input pins internally to the device. A system calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the external ADC pins before the calibration mode is initiated. In this way, external ADC errors are taken into account and minimized as a result of system calibration. It should also be noted that to optimize calibration accuracy, all ADuC836 ADC calibrations are carried out automatically at the slowest update rate. Internally in the ADuC836, the coefficients are normalized before being used to scale the words coming out of the digital filter. The offset calibration coefficient is subtracted from the result prior to the multiplication by the gain coefficient. From an operational point of view, a calibration should be treated like another ADC conversion. A zero-scale calibration (if required) should always be carried out before a full-scale calibration. System software should monitor the relevant ADC RDY0/1 bit in the ADCSTAT SFR to determine end of calibration via a polling sequence or interrupt driven routine. –28– REV. A ADuC836 ADuC836 Flash/EE Memory Reliability NONVOLATILE FLASH/EE MEMORY Flash/EE Memory Overview The Flash/EE program and data memory arrays on the ADuC836 are fully qualified for two key Flash/EE memory characteristics: Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention. The ADuC836 incorporates Flash/EE memory technology on-chip to provide the user with nonvolatile, in-circuit, reprogrammable code and data memory space. Flash/EE memory is a relatively recent type of nonvolatile memory technology and is based on a single transistor cell architecture. This technology is basically an outgrowth of EPROM technology and was developed through the late 1980s. Flash/EE memory takes the flexible in-circuit reprogrammable features of EEPROM and combines them with the space efficient/density features of EPROM (see Figure 15). Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events, which are defined as: a. Initial page erase sequence b. Read/verify sequence Because Flash/EE technology is based on a single transistor cell architecture, a Flash memory array, like EPROM, can be implemented to achieve the space efficiencies or memory densities required by a given design. c. Byte program sequence d. Second read/verify sequence In reliability qualification, every byte in both the program and data Flash/EE memory is cycled from 00H to FFH until a first fail is recorded, signifying the endurance limit of the on-chip Flash/EE memory. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased; the erase being performed in page blocks. Thus, flash memory is often and more correctly referred to as Flash/EE memory. As indicated in the Specification tables, the ADuC836 Flash/EE Memory Endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of –40°C, +25°C, +85°C, and +125°C. The results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25°C. EEPROM TECHNOLOGY SPACE EFFICIENT/ DENSITY IN-CIRCUIT REPROGRAMMABLE FLASH/EE MEMORY TECHNOLOGY Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the ADuC836 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 55°C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit described above, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash/EE memory is reprogrammed. It should also be noted that retention lifetime, based on an activation energy of 0.6 eV, will derate with TJ, as shown in Figure 16. Figure 15. Flash/EE Memory Development Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programmability, high density, and low cost. Incorporated into the ADuC836, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one-time programmable (OTP) devices at remote operating nodes. Flash/EE Memory and the ADuC836 The ADuC836 provides two arrays of Flash/EE memory for user applications. 62 Kbytes of Flash/EE program space are provided on-chip to facilitate code execution without any external discrete ROM device requirements. The program memory can be programmed in-circuit, using the serial download mode provided, using conventional third party memory programmers, or via any user defined protocol in User Download (ULOAD) mode. A 4 Kbyte Flash/EE data memory space is also provided on-chip. This may be used as a general-purpose, nonvolatile scratch pad area. User access to this area is via a group of seven SFRs. This space can be programmed at a byte level, although it must first be erased in 4-byte pages. 300 250 RETENTION – Years EPROM TECHNOLOGY A Single Flash/EE Memory Endurance Cycle 200 ADI SPECIFICATION 100 YEARS MIN. AT TJ = 55C 150 100 50 0 40 50 60 70 80 90 TJ JUNCTION TEMPERATURE – C 100 110 Figure 16. Flash/EE Memory Data Retention REV. A –29– ADuC836 Flash/EE Program Memory (2) Parallel Programming The ADuC836 contains a 64 Kbyte array of Flash/EE program memory. The lower 62 Kbytes of this program memory are available to the user, and can be used for program storage or indeed as additional NV data memory. The Parallel Programming mode is fully compatible with conventional third party Flash or EEPROM device programmers. A block diagram of the external pin configuration required to support parallel programming is shown in Figure 18. In this mode, Ports 0 and 2 operate as the external address bus interface, P3 operates as the external data bus interface, and P1.0 operates as the Write Enable strobe. Port 1.1, P1.2, P1.3, and P1.4 are used as a general configuration port that configures the device for various program and erase operations during parallel programming. The upper 2 Kbytes of this Flash/EE program memory array contain permanently embedded firmware, allowing in-circuit serial download, serial debug, and nonintrusive single pin emulation. These 2 Kbytes of embedded firmware also contain a power-on configuration routine that downloads factory calibrated coefficients to the various calibrated peripherals (ADC, temperature sensor, current sources, band gap references, and so on). This 2 Kbyte embedded firmware is hidden from user code. Attempts to read this space will read 0s, i.e., the embedded firmware appears as NOP instructions to user code. In normal operating mode (power-up default), the 62 Kbytes of user Flash/EE program memory appear as a single block. This block is used to store the user code, as shown in Figure 17. EMBEDDED DOWNLOAD/DEBUG KERNEL PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO BE DOWNLOADED TO ANY OF THE 62 KBYTES OF ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM APPEARS AS ‘NOP’ INSTRUCTIONS TO USER CODE. FFFFH 2 KBYTE F800H USER PROGRAM MEMORY 62 KBYTES OF FLASH/EE PROGRAM MEMORY IS AVAILABLE TO THE USER. ALL OF THIS SPACE CAN BE PROGRAMMED FROM THE PERMANENTLY EMBEDDED DOWNLOAD/DEBUG KERNEL OR IN PARALLEL PROGRAMMING MODE. 62 KBYTE F7FFH Table XIII. Flash/EE Memory Parallel Programming Modes P1.4 Port 1 Pins P1.3 P1.2 P1.1 Programming Mode 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 0 1 1 1 0 1 1 0 All other codes 1 0 0 1 1 0 1 Erase Flash/EE Program, Data, and Security Modes Read Device Signature/ID Program Code Byte Program Data Byte Read Code Byte Read Data Byte Program Security Modes Read/Verify Security Modes Redundant 5V VDD ADuC836 P3 GND PROGRAM MODE (SEE TABLE XIII) 0000H COMMAND ENABLE Figure 17. Flash/EE Program Memory Map in Normal Mode In Normal mode, the 62 Kbytes of Flash/EE program memory can be programmed by serial downloading or parallel processing: ENTRY SEQUENCE P1.1 -> P1.4 P1.0 GND EA GND PSEN VDD P0 P2 P1.5 -> P1.7 PROGRAM DATA (D0–D7) PROGRAM ADDRESS (A0–A13) (P2.0 = A0) (P1.7 = A13) TIMING RESET (1) Serial Downloading (In-Circuit Programming) The ADuC836 facilitates code download via the standard UART serial port. The ADuC836 will enter Serial Download mode after a reset or power cycle if the PSEN pin is pulled low through an external 1 k resistor. Once in serial download mode, the hidden embedded download kernel will execute. This allows the user to download code to the full 62 Kbytes of Flash/EE program memory while the device is in circuit in its target application hardware. Figure 18. Flash/EE Memory Parallel Programming A PC serial download executable is provided as part of the ADuC836 QuickStart development system. Application Note uC004 fully describes the serial download protocol that is used by the embedded download kernel. This Application Note is available at www.analog.com/microconverter. –30– REV. A ADuC836 Flash/EE Program Memory Security User Download Mode (ULOAD) In Figure 17 we can see that it was possible to use the 62 Kbytes of Flash/EE program memory available to the user as one single block of memory. In this mode, all of the Flash/EE memory is read only to user code. However, the Flash/EE program memory can also be written to during runtime simply by entering ULOAD mode. In ULOAD mode, the lower 56 Kbytes of program memory can be erased and reprogrammed by user software, as shown in Figure 19. ULOAD mode can be used to upgrade your code in the field via any user defined download protocol. Configuring the SPI port on the ADuC836 as a slave, it is possible to completely reprogram the 56 Kbytes of Flash/EE program memory in only 5 seconds (see Application Note uC007). Alternatively, ULOAD mode can be used to save data to the 56 Kbytes of Flash/EE memory. This can be extremely useful in data logging applications where the ADuC836 can provide up to 60 Kbytes of NV data memory on-chip (4 Kbytes of dedicated Flash/EE data memory also exist). The upper 6 Kbytes of the 62 Kbytes of Flash/EE program memory are only programmable via serial download or parallel programming. This means that this space appears as read-only to user code. Therefore, it cannot be accidently erased or reprogrammed by erroneous code execution. This makes it very suitable to use the 6 Kbytes as a bootloader. A Bootload Enable option exists in the serial downloader to “Always RUN from E000h after Reset.” If using a bootloader, this option is recommended to ensure that the bootloader always executes correct code after reset. Programming the Flash/EE program memory via ULOAD mode is described in more detail in the description of ECON and also in Application Note uC007. EMBEDDED DOWNLOAD/DEBUG KERNEL PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO BE DOWNLOADED TO ANY OF THE 62 KBYTES OF ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM APPEARS AS ‘NOP’ INSTRUCTIONS TO USER CODE. 62 KBYTES OF USER CODE MEMORY USER BOOTLOADER SPACE THE USER BOOTLOADER SPACE CAN BE PROGRAMMED IN DOWNLOAD/DEBUG MODE VIA THE KERNEL BUT IS READ ONLY WHEN EXECUTING USER CODE USER DOWNLOAD SPACE EITHER THE DOWNLOAD/DEBUG KERNEL OR USER CODE (IN ULOAD MODE) CAN PROGRAM THIS SPACE. The ADuC836 facilitates three modes of Flash/EE program memory security. These modes can be independently activated, restricting access to the internal code space. These security modes can be enabled as part of serial download protocol, as described in Application Note uC004, or via parallel programming. The ADuC836 offers the following security modes: Lock Mode This mode locks the code memory, disabling parallel programming of the program memory. However, reading the memory in Parallel mode and reading the memory via a MOVC command from external memory is still allowed. This mode is deactivated by initiating an “erase code and data” command in Serial Download or Parallel Programming modes. Secure Mode This mode locks the code memory, disabling parallel programming of the program memory. Reading/verifying the memory in Parallel mode and reading the internal memory via a MOVC command from external memory is also disabled. This mode is deactivated by initiating an “erase code and data” command in Serial Download or Parallel Programming modes. Serial Safe Mode This mode disables serial download capability on the device. If Serial Safe mode is activated and an attempt is made to reset the part into Serial Download mode, i.e., RESET asserted and deasserted with PSEN low, the part will interpret the serial download reset as a normal reset only. It will therefore not enter Serial Download mode, but only execute a normal reset sequence. Serial Safe mode can only be disabled by initiating an “erase code and data” command in parallel programming mode. FFFFH 2 KBYTE F800H F7FFH 6 KBYTE E000H DFFFH 56 KBYTE 0000H Figure 19. Flash/EE Program Memory Map in ULOAD Mode REV. A –31– ADuC836 BYTE 2 (0FFDH) BYTE 3 (0FFEH) BYTE 4 (0FFFH) 3FEH BYTE 1 (0FF8H) BYTE 2 (0FF9H) BYTE 3 (0FFAH) BYTE 4 (0FFBH) 03H BYTE 1 (000CH) BYTE 2 (000DH) BYTE 3 (000EH) BYTE 4 (000FH) 02H BYTE 1 (0008H) BYTE 2 (0009H) BYTE 3 (000AH) BYTE 4 (000BH) 01H BYTE 1 (0004H) BYTE 2 (0005H) BYTE 3 (0006H) BYTE 4 (0007H) BYTE 1 (0000H) BYTE 2 (0001H) BYTE 3 (0002H) BYTE 4 (0003H) 00H A block diagram of the SFR interface to the Flash/EE data memory array is shown in Figure 20. ECON—Flash/EE Memory Control SFR BYTE ADDRESSES ARE GIVEN IN BRACKETS Programming of either the Flash/EE data memory or the Flash/EE program memory is done through the Flash/EE Memory Control SFR (ECON). This SFR allows the user to read, write, erase, or verify the 4 Kbytes of Flash/EE data memory or the 56 Kbytes of Flash/EE program memory. EDATA4 SFR BYTE 1 (0FFCH) EDATA3 SFR 3FFH EDATA2 SFR PAGE ADDRESS (EADRH/L) The 4 Kbytes of Flash/EE data memory are configured as 1024 pages, each of four bytes. As with the other ADuC836 peripherals, the interface to this memory space is via a group of registers mapped in the SFR space. A group of four data registers (EDATA1–A4) is used to hold the four bytes of data at each page. The page is addressed via the two registers EADRH and EADRL. Finally, ECON is an 8-bit control register that may be written with one of nine Flash/EE memory access commands to trigger various read, write, erase, and verify functions. EDATA1 SFR Using the Flash/EE Data Memory Figure 20. Flash/EE Data Memory Control and Configuration Table XIV. ECON—Flash/EE Memory Commands Command Description (Normal Mode) (Power-On Default) Command Description (ULOAD Mode) 01H READ Results in four bytes in the Flash/EE data memory, addressed by the page address EADRH/L, being read into EDATA 1 to 4. Not Implemented. Use the MOVC instruction. 02H WRITE Results in four bytes in EDATA1–A4 being written to the Flash/EE data memory, at the page address given by EADRH/L (0 EADRH/L < 0400H) Note: The four bytes in the page being addressed must be pre-erased. Results in bytes 0–255 of internal XRAM being written to the 256 bytes of Flash/EE program memory at the page address given by EADRH. (0 EADRH < E0H) Note: The 256 bytes in the page being addressed must be pre-erased. 03H Reserved Command Reserved Command 04H VERIFY Verifies if the data in EDATA1–4 is contained in the page address given by EADRH/L. A subsequent read of the ECON SFR will result in a 0 being read if the verification is valid, or a nonzero value being read to indicate an invalid verification. Not Implemented. Use the MOVC and MOVX instructions to verify the WRITE in software. 05H ERASE PAGE Results in the erase of the 4-bytes page of Flash/EE data memory addressed by the page address EADRH/L Results in the 64-byte page of Flash/EE program memory, addressed by the byte address EADRH/L being erased. EADRL can equal any of 64 locations within the page. A new page starts whenever EADRL is equal to 00H, 40H, 80H, or C0H. 06H ERASE ALL Results in the erase of entire four Kbytes of Flash/EE data memory. Results in the erase of the entire 56 Kbytes of ULOAD Flash/EE program memory. 81H READBYTE Results in the byte in the Flash/EE data memory, addressed by the byte address EADRH/L, being read into EDATA1. (0 EADRH/L 0FFFH). Not Implemented. Use the MOVC command. 82H WRITEBYTE Results in the byte in EDATA1 being written into Flash/EE data memory, at the byte address EADRH/L. Results in the byte in EDATA1 being written into Flash/EE program memory at the byte address EADRH/L (0 EADRH/L DFFFH). 0FH EXULOAD Leaves the ECON instructions to operate on the Flash/EE data memory. Enters Normal mode, directing subsequent ECON instructions to operate on the Flash/EE data memory. F0H ULOAD Enters ULOAD mode, directing subsequent ECON instructions to operate on the Flash/EE program memory. Leaves the ECON instructions to operate on the Flash/EE program memory. ECON Value –32– REV. A ADuC836 Programming the Flash/EE Data Memory A user wishes to program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other three bytes already in this page. A typical program of the Flash/EE Data array will involve: 1. Setting EADRH/L with the page address 2. Writing the data to be programmed to the EDATA1–4 3. Writing the ECON SFR with the appropriate command Step 1: Set Up the Page Address The two address registers, EADRH and EADRL, hold the high byte address and the low byte address of the page to be addressed. The assembly language to set up the address may appear as: MOV EADRH,#0 ; Set Page Address Pointer MOV EADRL,#03H set to FFH, it is nonetheless good programming practice to include an erase-all routine as part of any configuration/setup code running on the ADuC836. An ERASE-ALL command consists of writing 06H to the ECON SFR, which initiates an erase of the 4-Kbyte Flash/EE array. This command coded in 8051 assembly would appear as: MOV ECON,#06H ; Erase all Command ; 2 ms Duration Flash/EE Memory Timing Typical program and erase times for the ADuC836 are as follows: Normal Mode (operating on Flash/EE data memory) READPAGE (4 bytes) WRITEPAGE (4 bytes) VERIFYPAGE (4 bytes) ERASEPAGE (4 bytes) ERASEALL (4 Kbytes) READBYTE (1 byte) WRITEBYTE (1 byte) Step 2: Set Up the EDATA Registers The four values to be written into the page into the four SFRs EDATA1–4. Since we do not know three of them, it is necessary to read the current page and overwrite the second byte. MOV ECON,#1 ; Read Page into EDATA1-4 MOV EDATA2,#0F3H ; Overwrite byte 2 ULOAD Mode (operating on Flash/EE program memory) WRITEPAGE (256 bytes) ERASEPAGE (64 bytes) ERASEALL (56 Kbytes) WRITEBYTE (1 byte) Step 3: Program Page A byte in the Flash/EE array can be programmed only if it has previously been erased. To be more specific, a byte can only be programmed if it already holds the value FFH. Because of the Flash/EE architecture, this erase must happen at a page level. Therefore, a minimum of four bytes (1 page) will be erased when an erase command is initiated. Once the page is erased, we can program the four bytes in-page and then perform a verification of the data. MOV ECON,#5 ; ERASE Page MOV ECON,#2 ; WRITE Page MOV ECON,#4 ; VERIFY Page MOV A,ECON ; Check if ECON=0 (OK!) JNZ ERROR Note that although the four Kbytes of Flash/EE data memory is shipped from the factory pre-erased, i.e., Byte locations REV. A – 5 machine cycles – 380 s – 5 machine cycles – 2 ms – 2 ms – 3 machine cycles – 200 s – 15 ms – 2 ms – 2 ms – 200 s It should be noted that a given mode of operation is initiated as soon as the command word is written to the ECON SFR. The core microcontroller operation on the ADuC836 is idled until the requested Program/Read or Erase mode is completed. In practice, this means that even though the Flash/EE memory mode of operation is typically initiated with a two-machine cycle MOV instruction (to write to the ECON SFR), the next instruction will not be executed until the Flash/EE operation is complete. This means that the core will not respond to interrupt requests until the Flash/EE operation is complete, although the core peripheral functions like counter/timers will continue to count and time as configured throughout this period. –33– ADuC836 DAC The ADuC836 incorporates a 12-bit voltage output DAC on-chip. It has a rail-to-rail voltage output buffer capable of driving 10 k/100 pF. It has two selectable ranges, 0 V to VREF (the internal band gap 2.5 V reference) and 0 V to AVDD. It can operate in 12-bit or 8-bit mode. The DAC has a control register, DACCON, and two data registers, DACH/L. The DAC output can be programmed to appear at Pin 3 or Pin 12. It should be noted that in 12-bit mode, the DAC voltage output will be updated as soon as the DACL data SFR has been written; therefore, the DAC data registers should be updated as DACH first, followed by DACL. The 12-bit DAC data should be written into DACH/L right-justified such that DACL contains the lower eight bits, and the lower nibble of DACH contains the upper four bits. Table XV. DACCON SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 ––– Reserved for Future Use 5 ––– Reserved for Future Use 4 DACPIN DAC Output Pin Select. Set by user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC). Cleared by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1). 3 DAC8 DAC 8-bit Mode Bit. Set by user to enable 8-bit DAC operation. In this mode, the 8 bits in DACL SFR are routed to the 8 MSBs of the DAC, and the 4 LSBs of the DAC are set to zero. Cleared by user to operate the DAC in its normal 12-bit mode of operation. 2 DACRN DAC Output Range Bit. Set by user to configure DAC range of 0 to AVDD. Cleared by user to configure DAC range of 0 V to 2.5 V (VREF). 1 DACCLR DAC Clear Bit. Set to 1 by user to enable normal DAC operation. Cleared to 0 by user to reset DAC data registers DACL/H to zero. 0 DACEN DAC Enable Bit. Set to 1 by user to enable normal DAC operation. Cleared to 0 by user to power down the DAC. DACH/L DAC Data Registers Function SFR Address DAC Data Registers, written by user to update the DAC output. DACL (DAC Data Low Byte) FBH DACH (DAC Data High Byte) FCH 00H Both Registers No Both Registers Power-On Default Value Bit Addressable Using the D/A Converter The on-chip D/A converter architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is illustrated in Figure 21. AVDD VREF ADuC836 R OUTPUT BUFFER R 12 DAC R HIGH-Z DISABLE (FROM MCU) R R Figure 21. Resistor String DAC Functional Equivalent Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity. As illustrated in Figure 21, the reference source for the DAC is user selectable in software. It can be either AVDD or VREF. In 0-to-AVDD mode, the DAC output transfer function spans from 0 V to the voltage at the AVDD pin. In 0-to-VREF mode, the DAC output transfer function spans from 0 V to the internal VREF (2.5 V). The DAC output buffer amplifier features a true rail-to-rail output stage implementation. This means that, unloaded, each output is capable of swinging to within less than 100 mV of both AVDD and ground. Moreover, the DAC’s linearity specification (when driving a 10 k resistive load to ground) is guaranteed through the full transfer function except codes 0 to 48 in 0-to-VREF mode and 0 to 100 and 3950 to 4095 in 0-toVDD mode. Linearity degradation near ground and VDD is caused by saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 22. The dotted line in Figure 22 indicates the ideal transfer function, and the solid line represents what the transfer function might look like with endpoint nonlinearities due to saturation of the output amplifier. –34– REV. A ADuC836 4 VDD VDD–50mV DAC LOADED WITH 0FFFH OUTPUT VOLTAGE – V VDD–100mV 3 1 100mV DAC LOADED WITH 0000H 50mV 0mV 0 FFFH 000H Figure 22. Endpoint Nonlinearities Due to Amplifier Saturation Note that Figure 22 represents a transfer function in 0-to-VDD mode only. In 0-to-VREF mode (with VREF < VDD), the lower nonlinearity would be similar, but the upper portion of the transfer function would follow the “ideal” line right to the end, showing no signs of endpoint linearity errors. The endpoint nonlinearities conceptually illustrated in Figure 22 get worse as a function of output loading. Most of the ADuC836 data sheet specifications assume a 10 k resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 22 become larger. With larger current demands, this can significantly limit output voltage swing. Figures 23 and 24 illustrate this behavior. It should be noted that the upper trace in each of these figures is valid only for an output range selection of 0-to-AVDD. In 0-to-VREF mode, DAC loading will not cause high side voltage drops as long as the reference voltage remains below the upper trace in the corresponding figure. For example, if AVDD = 3 V and VREF = 2.5 V, the high side voltage will not be affected by loads less than 5 mA. But somewhere around 7 mA, the upper curve in Figure 24 drops below 2.5 V (VREF), indicating that at these higher currents, the output will not be capable of reaching VREF. 5 OUTPUT VOLTAGE – V For larger loads, the current drive capability may not be sufficient To increase the source and sink current capability of the DAC, an external buffer should be added, as shown in Figure 25. ADuC836 12 Figure 25. Buffering the DAC Output The DAC output buffer also features a high impedance disable function. In the chip’s default power-on state, the DAC is disabled and its output is in a high impedance state (or “three-state”) where they remain inactive until enabled in software. This means that if a zero output is desired during power-up or power-down transient conditions, a pull-down resistor must be added to each DAC output. Assuming this resistor is in place, the DAC output will remain at ground potential whenever the DAC is disabled. 3 2 1 DAC LOADED WITH 0000H 0 0 10 5 SOURCE/SINK CURRENT – mA 15 Figure 23. Source and Sink Current Capability with VREF = AVDD = 5 V REV. A 15 Figure 24. Source and Sink Current Capability with VREF = VDD = 3 V DAC LOADED WITH 0FFFH 4 10 5 SOURCE/SINK CURRENT – mA 0 –35– ADuC836 PULSEWIDTH MODULATOR (PWM) The PWM on the ADuC836 is a highly flexible PWM offering programmable resolution and input clock, and can be configured for any one of six different modes of operation. Two of these modes allow the PWM to be configured as a - DAC with up to 16 bits of resolution. A block diagram of the PWM is shown in Figure 26. 12.583MHz PWMCLK CLOCK SELECT 32.768kHz 32.768kHz/15 16-BIT PWM COUNTER Figure 26. MODE PWM PWMCON (as described in Table XVI) controls the different modes of operation of the PWM as well as the PWM clock frequency. PWM0H/L and PWM1H/L are the data registers that determine the duty cycles of the PWM outputs at P1.0 and P1.1. To use the PWM user software, first write to PWMCON to select the PWM mode of operation and the PWM input clock. Writing to PWMCON also resets the PWM counter. In any of the 16-bit modes of operation (modes 1, 3, 4, 6), user software should write to the PWM0L or PWM1L SFRs first. This value is written to a hidden SFR. Writing to the PWM0H or PWM1H SFRs updates both the PWMxH and the PWMxL SFRs but does not change the outputs until the end of the PWM cycle in progress. The values written to these 16-bit registers are then used in the next PWM cycle. PROGRAMMABLE DIVIDER P1.0 COMPARE The PWM uses five SFRs: the control SFR, PWMCON, and four data SFRs: PWM0H, PWM0L, PWM1H, and PWM1L. P1.1 PWM1H/L PWM0H/L Block Diagram PWMCON PWM Control SFR SFR Address Power-On Default Value Bit Addressable AEH 00H No Table XVI. PWMCON SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 MD2 PWM Mode Bits 5 MD1 The MD2/1/0 bits choose the PWM mode as follows: 4 MD0 MD2 0 0 0 0 1 1 1 1 3 CDIV1 PWM Clock Divider. 2 CDIV0 Scale the clock source for the PWM counter as follows: CDIV1 0 0 1 1 MD1 0 0 1 1 0 0 1 1 CDIV0 0 1 0 1 MD0 0 1 0 1 0 1 0 1 Mode Mode 0: PWM Disabled Mode 1: Single Variable Resolution PWM Mode 2: Twin 8-bit PWM Mode 3: Twin 16-bit PWM Mode 4: Dual NRZ 16-bit - DAC Mode 5: Dual 8-bit PWM Mode 6: Dual RZ 16-bit - DAC Reserved for Future Use Description PWM Counter = Selected Clock/1 PWM Counter = Selected Clock 4 PWM Counter = Selected Clock/16 PWM Counter = Selected Clock/64 1 CSEL1 PWM Clock Divider. 0 CSEL0 Select the clock source for the PWM as follows: CSEL1 0 0 1 1 CSEL0 0 1 0 1 Description PWM Clock = fXTAL/15 PWM Clock = fXTAL PWM Clock = External Input at P3.4/T0/PWMCLK PWM Clock = fVCO (12.58 MHz) –36– REV. A ADuC836 PWM MODES OF OPERATION Mode 0: PWM Disabled PWM1L PWM COUNTER The PWM is disabled, allowing P1.0 and P1.1 to be used as normal. PWM0H Mode 1: Single Variable Resolution PWM PWM0L In Mode 1, both the pulse length and the cycle time (period) are programmable in user code, allowing the resolution of the PWM to be variable. PWM1H 0 P1.0 PWM1H/L sets the period of the output waveform. Reducing PWM1H/L reduces the resolution of the PWM output but increases the maximum output rate of the PWM (e.g., setting PWM1H/L to 65536 gives a 16-bit PWM with a maximum output rate of 192 Hz (12.583 MHz/65536). Setting PWM1H/L to 4096 gives a 12-bit PWM with a maximum output rate of 3072 Hz (12.583 MHz/4096)). P1.1 Figure 28. PWM Mode 2 Mode 3: Twin 16-Bit PWM In Mode 3, the PWM counter is fixed to count from 0 to 65536, giving a fixed 16-bit PWM. Operating from the 12.58 MHz core clock results in a PWM output rate of 192 Hz. The duty cycle of the PWM outputs at P1.0 and P1.1 is independently programmable. PWM0H/L sets the duty cycle of the PWM output waveform, as shown in Figure 27. PWM1H/L PWM COUNTER As in Figure 29, while the PWM counter is less than PWM0H/L, the output of PWM0 (P1.0) is high. Once the PWM counter equals PWM0H/L, PWM0 (P1.0) goes low and remains low until the PWM counter rolls over. PWM0H/L Similarly, while the PWM counter is less than PWM1H/L, the output of PWM1 (P1.1) is high. Once the PWM counter equals PWM1H/L, PWM1 (P1.1) goes low and remains low until the PWM counter rolls over. 0 P1.0 In this mode, both PWM outputs are synchronized (i.e., once the PWM counter rolls over to 0, both PWM0 (P1.0) and PWM1 (P1.1) will go high). Figure 27. PWM in Mode 1 Mode 2: Twin 8-Bit PWM In Mode 2, the duty cycle of the PWM outputs and the resolution of the PWM outputs are both programmable. The maximum resolution of the PWM output is eight bits. 65536 PWM COUNTER PWM1H/L PWM1L sets the period for both PWM outputs. Typically this will be set to 255 (FFH) to give an 8-bit PWM, although it is possible to reduce this as necessary. A value of 100 could be loaded here to give a percentage PWM (i.e., the PWM is accurate to 1%). The outputs of the PWM at P1.0 and P1.1 are shown in Figure 28. As can be seen, the output of PWM0 (P1.0) goes low when the PWM counter equals PWM0L. The output of PWM1 (P1.1) goes high when the PWM counter equals PWM1H and goes low again when the PWM counter equals PWM0H. Setting PWM1H to 0 ensures that both PWM outputs start simultaneously. REV. A PWM0H/L 0 P1.0 P1.1 Figure 29. PWM Mode 3 –37– ADuC836 Mode 4: Dual NRZ 16-Bit - DAC PWM1L PWM COUNTERS Mode 4 provides a high speed PWM output similar to that of a - DAC. Typically, this mode will be used with the PWM clock equal to 12.58 MHz. PWM1H PWM0L In this mode, P1.0 and P1.1 are updated every PWM clock (80 ns in the case of 12.58 MHz). Over any 65536 cycles (16-bit PWM), PWM0 (P1.0) is high for PWM0H/L cycles and low for (65536 – PWM0H/L) cycles. Similarly, PWM1 (P1.1) is high for PWM1H/L cycles and low for (65536 – PWM1H/L) cycles. If PWM1H is set to 4010H (slightly above one quarter of FS), then typically P1.1 will be low for three clocks and high for one clock (each clock is approximately 80 ns). Over every 65536 clocks, the PWM will compromise for the fact that the output should be slightly above one quarter of full scale by having a high cycle followed by only two low cycles. PWM0H/L = C000H CARRY OUT AT P1.0 16-BIT 16-BIT 16-BIT 12.583MHz 0 1 1 1 0 1 1 80s LATCH 16-BIT 16-BIT 0 0 CARRY OUT AT P1.1 0 1 0 0 0 16-BIT 80s PWM1H/L = 4000H Figure 30. PWM Mode 4 For faster DAC outputs (at lower resolution), write 0s to the LSBs that are not required with a 1 in the LSB position. If, for example, only 12-bit performance is required, write 0001 to the 4 LSBs. This means that a 12-bit accurate - DAC output can occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives an 8-bit accurate - DAC output at 49 kHz. PWM0H 0 P1.0 P1.1 Figure 31. PWM Mode 5 Mode 6: Dual RZ 16-Bit - DAC Mode 6 provides a high speed PWM output similar to that of a - DAC. Mode 6 operates very similarly to Mode 4. However, the key difference is that Mode 6 provides return to zero (RZ) - DAC output. Mode 4 provides non-return-to-zero - DAC outputs. The RZ mode ensures that any difference in the rise and fall times will not affect the - DAC INL. However, the RZ Mode halves the dynamic range of the - DAC outputs from 0AVDD to 0AVDD/2. For best results, this mode should be used with a PWM clock divider of 4. If PWM1H is set to 4010H (slightly above one quarter of FS) then P1.1 will typically be low for three full clocks (3 80 ns), high for half a clock (40 ns) and then low again for half a clock (40 ns) before repeating itself. Over every 65536 clocks, the PWM will compromise for the fact that the output should be slightly above one quarter of full scale by leaving the output high for two half clocks in four every so often. For faster DAC outputs (at lower resolution), write 0s to the LSBs that are not required with a 1 in the LSB position. If, for example, only 12-bit performance is required, write 0001 to the 4 LSBs. This means that a 12-bit accurate - DAC output can occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives an 8-bit accurate - DAC output at 49 kHz. PWM0H/L = C000H CARRY OUT AT P1.0 16-BIT Mode 5: Dual 8-Bit PWM 16-BIT 16-BIT In Mode 5, the duty cycle of the PWM outputs and the resolution of the PWM outputs are individually programmable. The maximum resolution of the PWM output is 8 bits. 3.146MHz The output resolution is set by the PWM1L and PWM1H SFRs for the P1.0 and P1.1 outputs, respectively. PWM0L and PWM0H set the duty cycles of the PWM outputs at P1.0 and P1.1, respectively. Both PWMs have the same clock source and clock divider. 16-BIT 0 1 1 1 0 1 1 318s LATCH 16-BIT CARRY OUT AT P1.1 0 0 0 1 0 0 0 16-BIT 318s PWM1H/L = 4000H Figure 32. PWM Mode 6 –38– REV. A ADuC836 ON-CHIP PLL The ADuC836 is intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (384) of this to provide a stable 12.582912 MHz clock for the system. The core can operate at this frequency, or at binary submultiples of it, to allow power saving in cases where maximum core performance is not PLLCON PLL Control Register SFR Address Power-On Default Value Bit Addressable D7H 03H No required. The default core clock is the PLL clock divided by 8 or 1.572864 MHz. The ADC clocks are also derived from the PLL clock, with the modulator rate being the same as the crystal oscillator frequency. This choice of frequencies ensures that the modulators and the core will be synchronous, regardless of the core clock rate. The PLL control register is PLLCON. Table XVII. PLLCON SFR Bit Designations Bit Name Description 7 OSC_PD Oscillator Power-Down Bit. Set by user to halt the 32 kHz oscillator in Power-Down mode. Cleared by user to enable the 32 kHz oscillator in Power-Down mode. This feature allows the TIC to continue counting even in Power-Down mode. 6 LOCK PLL Lock Bit. This is a read-only bit. Set automatically at power-on to indicate the PLL loop is correctly tracking the crystal clock. After power-down, this bit can be polled to wait for the PLL to lock. Cleared automatically at power-on to indicate the PLL is not correctly tracking the crystal clock. This may be due to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output can be 12.58 MHz ± 20%. After the ADuC836 wakes up from power-down, user code may poll this bit to wait for the PLL to lock. If LOCK = 0, then the PLL is not locked. 5 ––– Reserved for Future Use. Should be written with 0. 4 LTEA Reading this bit returns the state of the external EA pin latched at reset or power-on. 3 FINT Fast Interrupt Response Bit. Set by user enabling the response to any interrupt to be executed at the fastest core clock frequency, regardless of the configuration of the CD2–0 bits (see below). After user code has returned from an interrupt, the core resumes code execution at the core clock selected by the CD2–0 bits. Cleared by user to disable the fast interrupt response feature. 2 CD2 CPU (Core Clock) Divider Bits. 1 CD1 This number determines the frequency at which the microcontroller core will operate. 0 CD0 CD2 0 0 0 0 1 1 1 1 REV. A CD1 0 0 1 1 0 0 1 1 CD0 0 1 0 1 0 1 0 1 Core Clock Frequency (MHz) 12.582912 6.291456 3.145728 1.572864 (Default Core Clock Frequency) 0.786432 0.393216 0.196608 0.098304 –39– ADuC836 TIME INTERVAL COUNTER (WAKE-UP/RTC TIMER) If the ADuC836 is in Power-Down mode, again with TIC interrupt enabled, the TII bit will wake up the device and resume code execution by vectoring directly to the TIC interrupt service vector address at 0053H. The TIC-related SFRs are described in Table XVIII with a block diagram of the TIC shown in Figure 33. A time interval counter (TIC) is provided on-chip for: Periodically waking up the part from power-down Implementing a real-time clock Counting longer intervals than the standard 8051 compatible timers are capable of TCEN The TIC is capable of timeout intervals ranging from 1/128th second to 255 hours. Furthermore, this counter is clocked by the crystal oscillator rather than the by PLL, and thus has the ability to remain active in Power-Down mode and time long power-down intervals. This has obvious applications for remote battery-powered sensors where regular widely, spaced readings are required. 32.768kHz EXTERNAL CRYSTAL ITS0, 1 8-BIT PRESCALER HUNDREDTHS COUNTER HTHSEC The TIC counter can easily be used to generate a real-time clock. The hardware will count in seconds, minutes, and hours; however, user software will have to count in days, months, and years. The current time can be written to the timebase SFRs (HTHSEC, SEC, MIN, and HOUR) while TCEN is low. When the RTC timer is enabled (TCEN is set), the TCEN bit itself and the HTHSEC, SEC, MIN, and HOUR Registers are not reset to 00H after a hardware or watchdog timer reset. This is to prevent the need to recalibrate the real-time clock after a reset. However, these registers will be reset to 00H after a power cycle (independent of TCEN) or after any reset if TCEN is clear. SECOND COUNTER SEC INTERVAL TIMEBASE SELECTION MUX TIEN MINUTE COUNTER MIN HOUR COUNTER HOUR Six SFRs are associated with the time interval counter, TIMECON being its control register. Depending on the configuration of the IT0 and IT1 bits in TIMECON, the selected time counter register overflow will clock the interval counter. When this counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled. (See IEIP2 SFR description under the Interrupt System section.) INTERVAL TIMEOUT TIME INTERVAL COUNTER INTERRUPT 8-BIT INTERVAL COUNTER EQUAL? INTVAL SFR Figure 33. TIC, Simplified Block Diagram Table XVIII. TIMECON SFR Bit Designations Bit Name Description 7 6 5 4 ––– ––– ITS1 ITS0 3 STI 2 TII 1 TIEN 0 TCEN Reserved for Future Use Reserved for Future Use. For future product code compatibility, this bit should be written as a 1. Interval Timebase Selection Bits. Written by user to determine the interval counter update rate. ITS1 ITS0 Interval Timebase 0 0 1/128 Second 0 1 Seconds 1 0 Minutes 1 1 Hours Single Time Interval Bit. Set by user to generate a single interval timeout. If set, a timeout will clear the TIEN bit. Cleared by user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout. TIC Interrupt Bit. Set when the 8-bit interval counter matches the value in the INTVAL SFR. Cleared by user software. Time Interval Enable Bit. Set by user to enable the 8-bit time interval counter. Cleared by user to disable and clear the contents of the 8-bit interval counter. To ensure that the 8-bit interval counter is cleared, TIEN must be held low for at least 30.5 s (32 kHz). Time Clock Enable Bit. Set by user to enable the time clock to the time interval counters. Cleared by user to disable the 32 kHz clock to the TIC and clear the 8-bit prescaler and the HTHSEC, SEC, MIN, and HOURS SFRs. To ensure that these registers are cleared, TCEN must be held low for at least 30.5 s (32 kHz). The time registers (HTHSEC, SEC, MIN, and HOUR) can be written only while TCEN is low. –40– REV. A ADuC836 INTVAL User Time Interval Select Register Function SFR Address Power-On Default Value Reset Default Value Bit Addressable Valid Value User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled. (See IEIP2 SFR description under the Interrupt System section.) A6H 00H 00H No 0 to 255 decimal HTHSEC Hundredths Seconds Time Register Function SFR Address Power-On Default Value Reset Default Value Bit Addressable Valid Value This register is incremented in 1/128 second intervals once TCEN in TIMECON is active. The HTHSEC SFR counts from 0 to 127 before rolling over to increment the SEC time register. A2H 00H 00H if TCEN = 0, previous value before reset if TCEN = 1 No 0 to 127 decimal SEC Seconds Time Register Function SFR Address Power-On Default Value Reset Default Value Bit Addressable Valid Value This register is incremented in 1-second intervals once TCEN in TIMECON is active. The SEC SFR counts from 0 to 59 before rolling over to increment the MIN time register. A3H 00H 00H if TCEN = 0, previous value before reset if TCEN = 1 No 0 to 59 decimal MIN Minutes Time Register Function SFR Address Power-On Default Value Reset Default Value Bit Addressable Valid Value This register is incremented in 1-minute intervals once TCEN in TIMECON is active. The MIN counts from 0 to 59 before rolling over to increment the HOUR time register. A4H 00H 00H if TCEN = 0, previous value before reset if TCEN = 1 No 0 to 59 decimal HOUR Hours Time Register Function This register is incremented in 1-hour intervals once TCEN in TIMECON is active. The HOUR SFR counts from 0 to 23 before rolling over to 0. A5H 00H 00H if TCEN = 0, previous value before reset if TCEN = 1 No 0 to 23 decimal SFR Address Power-On Default Value Reset Default Value Bit Addressable Valid Value REV. A –41– ADuC836 WATCHDOG TIMER amount of time (see PRE3–0 bits in WDCON). The watchdog timer itself is a 16-bit counter that is clocked at 32.768 kHz. The watchdog timeout interval can be adjusted via the PRE3–0 bits in WDCON. Full control and status of the watchdog timer function can be controlled via the Watchdog Timer Control SFR (WDCON). The WDCON SFR can only be written by user software if the double write sequence described in WDWR below is initiated on every write access to the WDCON SFR. The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC836 enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. The watchdog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR. When enabled, the watchdog circuit will generate a system reset or interrupt (WDS) if the user program fails to set the watchdog (WDE) bit within a predetermined WDCON SFR Address Power-On Default Value Bit Addressable Watchdog Timer Control Register C0H 10H Yes Table XIX. WDCON SFR Bit Designations Bit Name Description 7 PRE3 Watchdog Timer Prescale Bits. 6 PRE2 The Watchdog timeout period is given by the equation tWD = (2PRE (29/fPLL)) 5 PRE1 (0 PRE 7; fPLL = 32.768 kHz) 4 PRE0 3 WDIR Watchdog Interrupt Response Enable Bit. If this bit is set by the user, the watchdog will generate an interrupt response instead of a system reset when the watchdog timeout period has expired. This interrupt is not disabled by the CLR EA instruction, and it is also a fixed, high priority interrupt. If the watchdog is not being used to monitor the system, it can alternatively be used as a timer. The prescaler is used to set the timeout period in which an interrupt will be generated. (See also Note 1, Table XXXIX in the Interrupt System section.) 2 WDS Watchdog Status Bit. Set by the watchdog controller to indicate that a watchdog timeout has occurred. Cleared by writing a 0 or by an external hardware reset. It is not cleared by a watchdog reset. 1 WDE Watchdog Enable Bit. Set by user to enable the watchdog and clear its counters. If a 1 is not written to this bit within the watchdog timeout period, the watchdog will generate a reset or interrupt, depending on WDIR. Cleared under the following conditions: User writes 0, watchdog reset (WDIR = 0); hardware reset; PSM interrupt. 0 WDWR Watchdog Write Enable Bit. To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the very next instruction must be a write instruction to the WDCON SFR. For example: CLR EA ; disable interrupts while writing ; to WDT SETB WDWR ; allow write to WDCON MOV WDCON, #72h ; enable WDT for 2.0s timeout SETB EA ; enable interrupts again (if rqd) PRE3 PRE2 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 PRE3–0 > 1001 PRE1 0 0 1 1 0 0 1 1 0 PRE0 0 1 0 1 0 1 0 1 0 Timeout Period (ms) 15.6 31.2 62.5 125 250 500 1000 2000 0.0 –42– Action Reset or Interrupt Reset or Interrupt Reset or Interrupt Reset or Interrupt Reset or Interrupt Reset or Interrupt Reset or Interrupt Reset or Interrupt Immediate Reset Reserved REV. A ADuC836 POWER SUPPLY MONITOR As its name suggests, the Power Supply Monitor, once enabled, monitors both supplies (AVDD or DVDD) on the ADuC836. It will indicate when any of the supply pins drops below one of four user-selectable voltage trip points from 2.63 V to 4.63 V. For correct operation of the Power Supply Monitor function, AVDD must be equal to or greater than 2.7 V. Monitor function is controlled via the PSMCON SFR. If enabled via the IEIP2 SFR, the monitor PSMCON Power Supply Monitor Control Register SFR Address Power-On Default Value Bit Addressable DFH DEH No will interrupt the core using the PSMI bit in the PSMCON SFR. This bit will not be cleared until the failing power supply has returned above the trip point for at least 250 ms. This monitor function allows the user to save working registers to avoid possible data loss due to the low supply condition, and also ensures that normal code execution will not resume until a safe supply level has been well established. The supply monitor is also protected against spurious glitches triggering the interrupt circuit. Table XX. PSMCON SFR Bit Designations Bit Name Description 7 CMPD DVDD Comparator Bit. This is a read-only bit and directly reflects the state of the DVDD comparator. Read 1 indicates the DVDD supply is above its selected trip point. Read 0 indicates the DVDD supply is below its selected trip point. 6 CMPA AVDD Comparator Bit. This is a read-only bit and directly reflects the state of the AVDD comparator. Read 1 indicates the AVDD supply is above its selected trip point. Read 0 indicates the AVDD supply is below its selected trip point. 5 PSMI Power Supply Monitor Interrupt Bit. This bit will be set high by the MicroConverter if either CMPA or CMPD are low, indicating low analog or digital supply. The PSMI Bit can be used to interrupt the processor. Once CMPD and/or CMPA return (and remain) high, a 250 ms counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be written by the user. However, if either comparator output is low, it is not possible for the user to clear PSMI. 4 TPD1 DVDD Trip Point Selection Bits. 3 TPD0 These bits select the DVDD trip point voltage as follows: TPD1 TPD0 Selected DVDD Trip Point (V) 0 0 4.63 0 1 3.08 1 0 2.93 1 1 2.63 2 TPA1 AVDD Trip Point Selection Bits. 1 TPA0 These bits select the AVDD trip point voltage as follows: TPA1 TPA0 Selected AVDD Trip Point (V) 0 0 4.63 0 1 3.08 1 0 2.93 1 1 2.63 0 PSMEN Power Supply Monitor Enable Bit. Set to 1 by the user to enable the Power Supply Monitor Circuit. Cleared to 0 by the user to disable the Power Supply Monitor Circuit. REV. A –43– ADuC836 SERIAL PERIPHERAL INTERFACE MISO (Master In, Slave Out Data I/O Pin), Pin 14 The ADuC836 integrates a complete hardware Serial Peripheral Interface (SPI) interface on-chip. SPI is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., fullduplex. It should be noted that the SPI pins SCLOCK and MOSI are multiplexed with the I2C pins SCLOCK and SDATA. The pins are controlled via the I2CCON SFR only if SPE is clear. SPI can be configured for master or slave operation and typically consists of four pins: The MISO (master in slave out) pin is configured as an input line in Master mode and an output line in Slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as bytewide (8-bit) serial data, MSB first. SCLOCK (Serial Clock I/O Pin), Pin 26 The master clock (SCLOCK) is used to synchronize the data being transmitted and received through the MOSI and MISO data lines. A single data bit is transmitted and received in each SCLOCK period. Therefore, a byte is transmitted/received after eight SCLOCK periods. The SCLOCK pin is configured as an output in master mode and as an input in Slave mode. In Master mode, the bit rate, polarity, and phase of the clock are controlled by the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR (see Table XXI). In Slave mode, the SPICON register will have to be configured with the phase and polarity (CPHA and CPOL) as the master, as for both Master and Slave modes the data is transmitted on one edge of the SCLOCK signal and sampled on the other. MOSI (Master Out, Slave In Pin), Pin 27 The MOSI (master out slave in) pin is configured as an output line in Master mode and an input line in Slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as bytewide (8-bit) serial data, MSB first. SS (Slave Select Input Pin), Pin 13 The Slave Select (SS) input pin is only used when the ADuC836 is configured in SPI Slave mode. This line is active low. Data is only received or transmitted in Slave mode when the SS pin is low, allowing the ADuC836 to be used in single master, multislave SPI configurations. If CPHA = 1, the SS input may be permanently pulled low. With CPHA = 0, the SS input must be driven low before the first bit in a byte wide transmission or reception and return high again after the last bit in that byte-wide transmission or reception. In SPI Slave mode, the logic level on the external SS pin (Pin 13) can be read via the SPR0 bit in the SPICON SFR. The following SFR registers are used to control the SPI interface. Table XXI. SPICON SFR Bit Designations Bit Name Description 7 ISPI SPI Interrupt Bit. Set by MicroConverter at the end of each SPI transfer. Cleared directly by user code or indirectly by reading the SPIDAT SFR. 6 WCOL Write Collision Error Bit. Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress. Cleared by user code. 5 SPE SPI Interface Enable Bit. Set by user to enable the SPI interface. Cleared by user to enable the I2C interface. 4 SPIM SPI Master/Slave Mode Select Bit. Set by user to enable Master mode operation (SCLOCK is an output). Cleared by user to enable Slave mode operation (SCLOCK is an input). 3 CPOL* Clock Polarity Select Bit. Set by user if SCLOCK idles high. Cleared by user if SCLOCK idles low. 2 CPHA* Clock Phase Select Bit. Set by user if leading SCLOCK edge is to transmit data. Cleared by user if trailing SCLOCK edge is to transmit data. 1 SPR1 SPI Bit Rate Select Bits. 0 SPR0 These bits select the SCLOCK rate (bitrate) in Master mode as follows: SPR1 SPR0 Selected Bit Rate 0 0 fCORE/2 0 1 fCORE/4 1 0 fCORE/8 1 1 fCORE/16 In SPI Slave mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin 13), can be read via the SPR0 bit. *The CPOL and CPHA bits should both contain the same values for master and slave devices. –44– REV. A ADuC836 SPIDAT SPI Data Register Function The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface. F7H 00H No SFR Address Power-On Default Value Bit Addressable Depending on the configuration of the bits in the SPICON SFR shown in Table XXI, the ADuC836 SPI interface will transmit or receive data in a number of possible modes. Figure 34 shows all possible ADuC836 SPI configurations and the timing relationships and synchronization between the signals involved. Also shown in this figure is the SPI Interrupt bit (ISPI) and how it is triggered at the end of each byte-wide communication. SCLOCK (CPOL = 1) SCLOCK (CPOL = 0) SS SAMPLE INPUT (CPHA = 1) DATA OUTPUT ? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB SPI Interface—Master Mode In Master mode, the SCLOCK pin is always an output and generates a burst of eight clocks whenever user code writes to the SPIDAT Register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the SS pin is not used in Master mode. If the ADuC836 needs to assert the SS pin on an external slave device, a port digital output pin should be used. In Master mode, a byte transmission or reception is initiated by a write to SPIDAT. Eight clock periods are generated via the SCLOCK pin and the SPIDAT byte being transmitted via MOSI. With each SCLOCK period, a data bit is also sampled via MISO. After eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. The ISPI flag will be set automatically and an interrupt will occur if enabled. The value in the shift register will be latched into SPIDAT. SPI Interface—Slave Mode ISPI FLAG SAMPLE INPUT (CPHA = 0) DATA OUTPUT MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB ? ISPI FLAG Figure 34. SPI Timing, All Modes REV. A In Slave mode, the SCLOCK is an input. The SS pin must also be driven low externally during the byte communication. Transmission is also initiated by a write to SPIDAT. In Slave mode, a data bit is transmitted via MISO and a data bit is received via MOSI through each input SCLOCK period. After eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. The ISPI flag will be set automatically and an interrupt will occur if enabled. The value in the shift register will be latched into SPIDAT only when the transmission/reception of a byte has been completed. The end of transmission occurs after the eighth clock has been received, if CPHA = 1 or when SS returns high if CPHA = 0. –45– ADuC836 I2C SERIAL INTERFACE The ADuC836 supports a fully licensed* I2C serial interface. The I2C interface is implemented as a full hardware slave and software master. SDATA (Pin 27) is the data I/O pin and SCLOCK (Pin 26) is the serial clock. These two pins are shared with the MOSI and SCLOCK pins of the on-chip SPI interface. Therefore I2CCON SFR Address Power-On Default Value Bit Addressable the user can enable only one interface or the other at any given time (see SPE in Table XXI). Application Note uC001 describes the operation of this interface as implemented and is available from the MicroConverter website at: www.analog.com/microconverter. Three SFRs are used to control the I2C interface. These are described below. I2C Control Register E8H 00H Yes Table XXII. I2CCON SFR Bit Designations Bit Name Description 7 MDO I2C Software Master Data Output Bit (Master Mode Only). This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit will be output on the SDATA pin if the data output enable (MDE) bit is set. 6 MDE I2C Software Master Data Output Enable Bit (Master Mode Only). Set by user to enable the SDATA pin as an output (Tx). Cleared by user to enable SDATA pin as an input (Rx). 5 MCO I2C Software Master Clock Output Bit (Master Mode Only). This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit will be output on the SCLOCK pin. 4 MDI I2C Software Master Data Input Bit (Master Mode Only). This data bit is used to implement a master I2C receiver interface in software. Data on the SDATA pin is latched into this bit on SCLOCK if the data output enable (MDE) bit is 0. 3 I2CM I2C Master/Slave Mode Bit. Set by user to enable I2C software Master mode. Cleared by user to enable I2C hardware Slave mode. 2 I2CRS I2C Reset Bit (Slave Mode Only). Set by user to reset the I2C interface. Cleared by user code for normal I2C operation. 1 I2CTX I2C Direction Transfer Bit (Slave Mode Only). Set by MicroConverter if the interface is transmitting. Cleared by the MicroConverter if the interface is receiving. 0 I2CI I2C Interrupt Bit (Slave Mode Only). Set by the MicroConverter after a byte has been transmitted or received. Cleared automatically when the user code reads the I2CDAT SFR (see I2CDAT below). I2CADD I2C Address Register SFR Address Power-On Default Value Bit Addressable Holds the I2C peripheral address for the part. It may be overwritten by the user code. Application Note uC001 at www.analog.com/microconverter describes the format of the I2C standard 7-bit address in detail. 9BH 55H No I2CDAT I2C Data Register Function Function SFR Address Power-On Default Value Bit Addressable The I2CDAT SFR is written by the user to transmit data over the I2C interface or read by user code to read data just received by the I2C interface. Accessing I2CDAT automatically clears any pending I2C interrupt and the I2CI bit in the I2CCON SFR. User software should access I2CDAT only once per interrupt cycle. 9AH 00H No *Purchase of licensed I2C components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. –46– REV. A ADuC836 The main features of the MicroConverter I2C interface are: Once enabled in I2C Slave mode, the slave controller waits for a START condition. If the ADuC836 detects a valid start condition followed by a valid address, and by the R/W bit, the I2CI interrupt bit will be automatically set by hardware. Only two bus lines are required: a serial data line (SDATA) and a serial clock line (SCLOCK). An I2C master can communicate with multiple slave devices. Because each slave device has a unique 7-bit address, single master/slave relationships can exist at all times even in a multislave environment (Figure 35). On-chip filtering rejects <50 ns spikes on the SDATA and SCLOCK lines to preserve data integrity. The I2C peripheral will only generate a core interrupt if the user has preconfigured the I2C interrupt enable bit in the IEIP2 SFR as well as the global interrupt Bit EA in the IE SFR, i.e., ; Enabling I2C Interrupts for the ADuC836 MOV IEIP2,#01h ; enable I2C interrupt SETB EA DVDD I2C MASTER On the ADuC836, an auto clear of the I2CI bit is implemented so this bit is cleared automatically on a read or write access to the I2CDAT SFR. I2C SLAVE #1 MOV I2CDAT, A ; I2CI auto-cleared MOV A, I2CDAT ; I2CI auto-cleared If for any reason the user tries to clear the interrupt more than once, i.e., access the data SFR more than once per interrupt, then the I2C controller will halt. The interface will then have to be reset using the I2CRS bit. I2C SLAVE #2 Figure 35. Typical I 2C System Software Master Mode The ADuC836 can be used as an I2C master device by configuring the I2C peripheral in Master mode and writing software to output the data bit by bit, which is referred to as a software master. Master mode is enabled by setting the I2CM bit in the I2CCON register. The user can choose to poll the I2CI bit or enable the interrupt. In the case of the interrupt, the PC counter will vector to 003BH at the end of each complete byte. For the first byte when the user gets to the I2CI ISR, the 7-bit address and the R/W bit will appear in the I2CDAT SFR. To transmit data on the SDATA line, MDE must be set to enable the output driver on the SDATA pin. If MDE is set, the SDATA pin will be pulled high or low depending on whether the MDO bit is set or cleared. MCO controls the SCLOCK pin and is always configured as an output in Master mode. In Master mode, the SCLOCK pin will be pulled high or low depending on the whether MCO is set or cleared. The I2CTX bit contains the R/W bit sent from the master. If I2CTX is set, the master would like to receive a byte. Therefore, the slave will transmit data by writing to the I2CDAT register. If I2CTX is cleared, the master would like to transmit a byte. Therefore, the slave will receive a serial byte. The software can interrogate the state of I2CTX to determine whether it should write to or read from I2CDAT. To receive data, MDE must be cleared to disable the output driver on SDATA. Software must provide the clocks by toggling the MCO bit and reading the SDATA pin via the MDI bit. If MDE is cleared, MDI can be used to read the SDATA pin. The value of the SDATA pin is latched into MDI on a rising edge of SCLOCK. MDI is set if the SDATA pin was high on the last rising edge of SCLOCK. MDI is clear if the SDATA pin was low on the last rising edge of SCLOCK. Once the ADuC836 has received a valid address, hardware will hold SCLOCK low until the I2CI bit is cleared by the software. This allows the master to wait for the slave to be ready before transmitting the clocks for the next byte. Software must control MDO, MCO, and MDE appropriately to generate the START condition, slave address, acknowledge bits, data bytes, and STOP conditions. These functions are provided in Application Note uC001. Hardware Slave Mode After reset, the ADuC836 defaults to hardware Slave mode. The I2C interface is enabled by clearing the SPE bit in SPICON. Slave mode is enabled by clearing the I2CM bit in I2CCON. The ADuC836 has a full hardware slave. In Slave mode, the I2C address is stored in the I2CADD register. Data received or to be transmitted is stored in the I2CDAT register. REV. A The I2CI interrupt bit will be set every time a complete data byte is received or transmitted provided it is followed by a valid ACK. If the byte is followed by a NACK, an interrupt is generated. The ADuC836 will continue to issue interrupts for each complete data byte transferred until a STOP condition is received or the interface is reset. When a STOP condition is received, the interface will reset to a state where it is waiting to be addressed (idle). Similarly, if the interface receives a NACK at the end of a sequence, it also returns to the default idle state. The I2CRS bit can be used to reset the I2C interface. This bit can be used to force the interface back to the default idle state. It should be noted that there is no way (in hardware) to distinguish between an interrupt generated by a received START + valid address and an interrupt generated by a received data byte. User software must be used to distinguish between these interrupts. –47– ADuC836 DUAL DATA POINTER DPCON Data Pointer Control SFR The ADuC836 incorporates both main and shadow data pointers. The shadow data pointer is selected via the data pointer control SFR (DPCON). DPCON also includes features such as automatic hardware post-increment and post-decrement, as well as automatic data pointer toggle. DPCON is described in Table XXIII. SFR Address Power-On Default Value Bit Addressable A7H 00H No Table XXIII. DPCON SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 DPT Data Pointer Automatic Toggle Enable. Cleared by user to disable auto swapping of the DPTR. Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction. 5 DP1m1 Shadow Data Pointer Mode. 4 DP1m0 These two bits enable extra modes of the shadow data pointer operation, allowing for more compact and more efficient code size and execution. m1 m0 Behavior of the Shadow Data Pointer 0 0 8052 Behavior 0 1 DPTR is post-incremented after a MOVX or MOVC instruction. 1 0 DPTR is post-decremented after a MOVX or MOVC instruction. 1 1 DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction can be useful for moving 8-bit blocks to/from 16-bit devices.) 3 DP0m1 Main Data Pointer Mode. 2 DP0m0 These two bits enable extra modes of the main data pointer operation, allowing for more compact and more efficient code size and execution. m1 m0 Behavior of the Main Data Pointer 0 0 8052 Behavior 0 1 DPTR is post-incremented after a MOVX or MOVC instruction. 1 0 DPTR is post-decremented after a MOVX or MOVC instruction. 1 1 DPTR LSB is toggled aftera MOVX or MOVC instruction. (This instruction can be useful for moving 8-bit blocks to/from 16-bit devices.) 1 ––– This bit is not implemented to allow the INC DPCON instruction to toggle the data pointer without incrementing the rest of the SFR. 0 DPSEL Data Pointer Select. Cleared by user to select the main data pointer. This means that the contents of the main 24-bit DPTR appears in the three SFRs: DPL, DPH, and DPP. Set by user to select the shadow data pointer. This means that the contents of the shadow 24-bit DPTR appears in the three SFRs: DPL, DPH, and DPP. NOTES 1. This is the only place where the main and shadow data pointers are distinguished. Everywhere else in this data sheet, wherever the DPTR is mentioned, operation on the active DPTR is implied. 2. Only MOVC/MOVX @DPTR instructions are relevant above. MOVC/MOVX PC/@Ri instructions will not cause the DPTR to automatically post increment/decrement, and so on. To illustrate the operation of DPCON, the following code will copy 256 bytes of code memory at address D000H into XRAM starting from address 0000H. the code uses 16 bytes and 2054 cycles. To perform this on a standard 8051 requires approximately 33 bytes and 7172 cycles (depending on how it is implemented). MOV MOV DPTR,#0 DPCON,#55h MOV DPTR,#0D000h MOVELOOP: CLR A ; ; ; ; ; ; Main DPTR = 0 Select shadow DPTR DPTR1 increment mode, DPTR0 increment mode DPTR auto toggling ON Shadow DPTR = D000h MOVC A,@A+DPTR MOVX @DPTR,A MOV JNZ –48– ; ; ; ; ; ; Get data Post Inc DPTR Swap to Main DPTR (Data) Put ACC in XRAM Increment main DPTR Swap to Shad DPTR (Code) A, DPL MOVELOOP REV. A ADuC836 8052 COMPATIBLE ON-CHIP PERIPHERALS Port 1 This section gives a brief overview of the various secondary peripheral circuits, which are also available to the user on-chip. These remaining functions are mostly 8052 compatible (with a few additional features) and are controlled via standard 8052 SFR bit definitions. Port 1 is also an 8-bit port directly controlled via the P1 SFR. The Port 1 pins are divided into two distinct pin groupings: P1.0 to P1.1 and P1.2 to P1.7. P1.0 and P1.1 P1.0 and P1.1 are bidirectional digital I/O pins with internal pull-ups. Parallel I/O The ADuC836 uses four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations while others are multiplexed with alternate functions for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general-purpose I/O pin. If P1.0 and P1.1 have 1s written to them via the P1 SFR, they are pulled high by the internal pull-up resistors. In this state, they can also be used as inputs. As input pins being externally pulled low, they will source current because of the internal pull-ups. With 0s written to them, both of these pins will drive a logic low output voltage (VOL) and will be capable of sinking 10 mA compared to the standard 1.6 mA sink capability on the other port pins. Port 0 Port 0 is an 8-bit open-drain bidirectional I/O port that is directly controlled via the Port 0 SFR. Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory. Figure 36 shows a typical bit latch and I/O buffer for a Port 0 port pin. The bit latch (one bit in the port’s SFR) is represented as a Type D flip-flop, which will clock in a value from the internal bus in response to a “write to latch” signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a “read latch” signal from the CPU. The level of the port pin itself is placed on the internal bus in response to a “read pin” signal from the CPU. Some instructions that read a port activate the “read latch” signal, and others activate the “read pin” signal. See the Read-Modify-Write Instructions section for more details. ADDR/DATA READ LATCH INTERNAL BUS WRITE TO LATCH DVDD CONTROL D Q These pins also have various secondary functions described in Table XXIV. The Timer 2 alternate functions of P1.0 and P1.1 can only be activated if the corresponding bit latch in the P1 SFR contains a 1. Otherwise, the port pin is stuck at 0. In the case of the PWM outputs at P1.0 and P1.1, the PWM outputs will overwrite anything written to P1.0 or P1.1. Table XXIV. P1.0 and P1.1 Alternate Pin Functions Pin Alternate Function P1.0 T2 (Timer/Counter 2 External Input) PWM0 (PWM0 output at this pin) T2EX (Timer/Counter 2 Capture/Reload Trigger) PWM1 (PWM1 output at this pin) P1.1 Figure 37 shows a typical bit latch and I/O buffer for a P1.0 or P1.1 port pin. No external memory access is required from either of these pins, although internal pull-ups are present. DVDD P0.x PIN READ LATCH CL Q LATCH INTERNAL BUS Figure 36. Port 0 Bit Latch and I/O Buffer In general-purpose I/O port mode, Port 0 pins that have 1s written to them via the Port 0 SFR will be configured as open-drain and therefore will float. In this state, Port 0 pins can be used as high impedance inputs. This is represented in Figure 36 by the NAND gate whose output remains high as long as the CONTROL signal is low, thereby disabling the top FET. External pull-up resistors are therefore required when Port 0 pins are used as general-purpose outputs. Port 0 pins with 0s written to them will drive a logic low output voltage (VOL) and will be capable of sinking 1.6 mA. REV. A D WRITE TO LATCH READ PIN As shown in Figure 36, the output drivers of Port 0 pins are switchable to an internal ADDR and ADDR/DATA bus by an internal CONTROL signal for use in external memory accesses. During external memory accesses, the P0 SFR is written with 1s (i.e., all of its bit latches become 1s). When accessing external memory, the CONTROL signal in Figure 36 goes high, enabling push-pull operation of the output pin from the internal address or data bus (ADDR/DATA line). Therefore, no external pull-ups are required on Port 0 for it to access external memory. ALTERNATE OUTPUT FUNCTION INTERNAL PULL-UP* P1.x PIN Q CL Q LATCH READ PIN ALTERNATE INPUT FUNCTION *SEE FIGURE 38 FOR DETAILS OF INTERNAL PULL-UP Figure 37. P1.0 and P1.1 Bit Latch and I/O Buffer The internal pull-up consists of active circuitry, as shown in Figure 38. Whenever a P1.0 or P1.1 bit latch transitions from low to high, Q1 in Figure 38 turns on for two oscillator periods to quickly pull the pin to a logic high state. Once there, the weaker Q3 turns on, thereby latching the pin to a logic high. If the pin is momentarily pulled low externally, Q3 will turn off, but the very weak Q2 will continue to source some current into the pin, attempting to restore it to a logic high. DVDD 2 CLK DELAY Q FROM PORT LATCH Q1 DVDD Q2 DVDD Q3 Q4 Figure 38. Internal Pull-Up Configuration –49– Px.x PIN ADuC836 P1.2 to P1.7 Port 3 pins also have various secondary functions described in Table XXV. The alternate functions of Port 3 pins can be activated only if the corresponding bit latch in the P3 SFR contains a 1. Otherwise, the port pin is stuck at 0. The remaining Port 1 pins (P1.2 to P1.7) can only be configured as analog input (ADC) or digital input pins. By (power-on) default, these pins are configured as analog inputs, i.e., 1 written in the corresponding Port 1 register bit. To configure any of these pins as digital inputs, the user should write a 0 to these port bits to configure the corresponding pin as a high impedance digital input. Figure 39 illustrates this function. Note that there are no output drivers for Port 1 pins, and they therefore cannot be used as outputs. Table XXV. Port 3, Alternate Pin Functions WRITE TO LATCH D Q CL Q LATCH READ PIN TO ADC Alternate Function P3.0 RxD (UART Input Pin) (or Serial Data I/O in Mode 0) TxD (UART Output Pin) (or Serial Clock Output in Mode 0) INT0 (External Interrupt 0) INT1 (External Interrupt 1) T0 (Timer/Counter 0 External Input) PWMCLK (PWM External Clock) T1 (Timer/Counter 1 External Input) WR (External Data Memory Write Strobe) RD (External Data Memory Read Strobe) P3.1 READ LATCH INTERNAL BUS Pin P3.2 P3.3 P3.4 P1.x PIN P3.5 P3.6 P3.7 Figure 39. P1.2 to P1.7 Bit Latch and I/O Buffer Port 2 Port 3 pins have the same bit latch and I/O buffer configurations as the P1.0 and P1.1, as shown in Figure 41. The internal pull-up configuration is also defined by the one in Figure 38. Port 2 is a bidirectional port with internal pull-up resistors directly controlled via the P2 SFR. Port 2 also emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24-bit external data memory space. DVDD READ LATCH As shown in Figure 40, the output drivers of Port 2 are switchable to an internal ADDR bus by an internal CONTROL signal for use in external memory accesses (as for Port 0). In external memory addressing mode (CONTROL = 1), the port pins feature push/ pull operation controlled by the internal address bus (ADDR line). However, unlike the P0 SFR during external memory accesses, the P2 SFR remains unchanged. INTERNAL BUS WRITE TO LATCH In general-purpose I/O port mode, Port 2 pins that have 1s written to them are pulled high by the internal pull-ups (Figure 38), and in that state can be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 pins with 0s written to them will drive a logic low output voltage (VOL) and will be capable of sinking 1.6 mA. ADDR CONTROL READ LATCH INTERNAL PULL-UP* INTERNAL BUS D Q WRITE TO LATCH CL Q READ PIN DVDD DVDD P2.x PIN LATCH *SEE FIGURE 38 FOR DETAILS OF INTERNAL PULL-UP ALTERNATE OUTPUT FUNCTION D Q CL Q INTERNAL PULL-UP* P3.x PIN LATCH READ PIN ALTERNATE INPUT FUNCTION *SEE FIGURE 38 FOR DETAILS OF INTERNAL PULL-UP Figure 41. Port 3 Bit Latch and I/O Buffer Additional Digital I/O In addition to the port pins, the dedicated SPI/I2C pins (SCLOCK and SDATA/MOSI) also feature both input and output functions. Their equivalent I/O architectures are illustrated in Figure 42 and Figure 44, respectively, for SPI operation, and in Figure 43 and Figure 45 for I2C operation. Notice that in I2C mode (SPE = 0), the strong pull-up FET (Q1) is disabled leaving only a weak pull-up (Q2) present. By contrast, in SPI mode (SPE = 1), the strong pull-up FET (Q1) is controlled directly by SPI hardware, giving the pin push/pull capability. Port 3 is a bidirectional port with internal pull-ups directly controlled via the P3 SFR. In I2C mode (SPE = 0), two pull-down FETs (Q3 and Q4) operate in parallel in order to provide an extra 60% or 70% of current sinking capability. In SPI mode, however, (SPE = 1), only one of the pull-down FETs (Q3) operates on each pin resulting in sink capabilities identical to that of Port 0 and Port 2 pins. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-ups. Port 3 pins with 0s written to them will drive a logic low output voltage (VOL) and will be capable of sinking 1.6 mA. On the input path of SCLOCK, notice that a Schmitt trigger conditions the signal going to the SPI hardware to prevent false triggers (double triggers) on slow incoming edges. For incoming signals from the SCLOCK and SDATA pins going to I2C hardware, a filter conditions the signals to reject glitches of up to 50 ns in duration. Figure 40. Port 2 Bit Latch and I/O Buffer Port 3 –50– REV. A ADuC836 Notice also that direct access to the SCLOCK and SDATA/MOSI pins is afforded through the SFR interface in I2C master mode. Therefore, if you are not using the SPI or I2C functions, you can use these two pins to provide additional high current digital outputs. DVDD SPE = 1 (SPI ENABLE) Q1 As shown in Figure 46, the MISO pin in SPI master/slave operation offers the exact same pull-up and pull-down configuration as the MOSI pin in SPI slave/master operation. The SS pin has a weak internal pull-up permanently enabled to prevent the SS input from floating. This pull-up can be easily overdriven by an external device to drive the SS pin low. DVDD Q2 (OFF) HARDWARE SPI (MASTER/SLAVE) SCLOCK PIN SCHMITT TRIGGER Q4 (OFF) HARDWARE SPI (MASTER/SLAVE) Q3 Figure 42. SCLOCK Pin I/O Functional Equivalent in SPI Mode DVDD HARDWARE I2C (SLAVE ONLY) SFR BITS Figure 46. MISO Pin I/O Functional Equivalent DVDD SPE = 0 (I2C ENABLE) Q1 (OFF) Q2 50ns GLITCH REJECTION FILTER HARDWARE SPI (MASTER/SLAVE) SCLOCK PIN MCO I2CM Read-Modify-Write Instructions Figure 43. SCLOCK Pin I/O Functional Equivalent in I2C Mode DVDD SPE = 1 (SPI ENABLE) Q1 Q2 (OFF) SDATA/ MOSI PIN HARDWARE SPI (MASTER/SLAVE) Q4 (OFF) Q3 Figure 44. SDATA/MOSI Pin I/O Functional Equivalent in SPI Mode DVDD SPE = 0 (I2C ENABLE) SFR BITS Q1 (OFF) Q2 SDATA/ MOSI PIN Q4 MDO Some 8051 instructions that read a port, read the latch and others read the pin. The instructions that read the latch rather than the pins are the ones that read a value, possibly change it, and then rewrite it to the latch. These are called “read-modifywrite” instructions. which are listed below. When the destination operand is a port or a port bit, these instructions read the latch rather than the pin. ANL ORL XRL JBC (Logical AND, e.g., ANL P1, A) (Logical OR, e.g., ORL P2, A) (Logical EX-OR, e.g., XRL P3, A) (Jump If Bit = 1 and Clear Bit, e.g., JBC P1.1, LABEL CPL (Complement Bit, e.g., CPL P3.0) INC (Increment, e.g., INC P2) DEC (Decrement, e.g., DEC P2) DJNZ (Decrement and Jump IFf Not Zero, e.g.,DJNZ P3, LABEL) MOV PX.Y, C* (Move Carry to Bit Y of Port X) CLR PX.Y* (Clear Bit Y of Port X) SETB PX.Y* (Set Bit Y of Port X) *These instructions read the port byte (all eight bytes), modify the addressed bit and then write the new byte back to the latch. 50ns GLITCH REJECTION FILTER MDI MDE Q3 I2CM The reason that read-modify-write instructions are directed to the latch rather than to the pin is to avoid a possible misinterpretation of the voltage level of a pin. For example, a port pin might be used to drive the base of a transistor. When a 1 is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor and interpret it as a Logic 0. Reading the latch rather than the pin will return the correct value of 1. Figure 45. SDATA/MOSI Pin I/O Functional Equivalent in I2C Mode REV. A SS PIN Figure 47. SS Pin I/O Functional Equivalent Q4 Q3 HARDWARE I2C (SLAVE ONLY) MISO PIN –51– ADuC836 TIMERS/COUNTERS The ADuC836 has three 16-bit Timer/Counters: Timer 0, Timer 1, and Timer 2. The Timer/Counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each Timer/Counter consists of two 8-bit registers: THx and TLx (x = 0, 1, and 2). All three can be configured to operate either as timers or event counters. In Timer function, the TLx Register is incremented every machine cycle. Thus it can be viewed as counting machine cycles. Since a machine cycle consists of 12 core clock periods, the maximum count rate is 1/12 of the core clock frequency. every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since it takes two machine cycles (16 core clock periods) to recognize a 1-to-0 transition, the maximum count rate is 1/16 of the core clock frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for a minimum of one full machine cycle. Remember that the core clock frequency is programmed via the CD0–2 selection bits in the PLLCON SFR. User configuration and control of the timers is achieved via three main SFRs: TMOD and TCON control the configuration of Timers 0 and 1, while T2CON configures Timer 2. In Counter function, the TLx Register is incremented by a 1-to-0 transition at its corresponding external input pin, T0, T1, or T2. In this function, the external input is sampled during S5P2 of TMOD Timer/Counter 0 and 1 Mode Register SFR Address Power-On Default Value Bit Addressable 89H 00H No Table XXVI. TMOD SFR Bit Designations Bit Name Description 7 Gate Timer 1 Gating Control. Set by software to enable Timer/Counter 1 only while INT1 pin is high and TR1 control bit is set. Cleared by software to enable Timer 1 whenever TR1 control bit is set. 6 C/T Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from T1 pin). Cleared by software to select timer operation (input from internal system clock). 5 M1 Timer 1 Mode Select Bit 1 (used with M0 Bit) 4 M0 Timer 1 Mode Select Bit 0. M1 M0 0 0 TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler. 1 0 8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each time it overflows. 1 1 Timer/Counter 1 stopped. 3 Gate Timer 0 Gating Control. Set by software to enable Timer/Counter 0 only while INT0 pin is high and TR0 control bit is set. Cleared by software to enable Timer 0 whenever TR0 control bit is set. 2 C/T Timer 0 Timer or Counter Select Bit. Set by software to select counter operation (input from T0 pin). Cleared by software to select timer operation (input from internal system clock). 1 M1 Timer 0 Mode Select Bit 1 0 M0 Timer 0 Mode Select Bit 0. M1 M0 0 0 TH0 operates as an 8-bit timer/counter. TL0 serves as 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler. 1 0 8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each time it overflows. 1 1 TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits. –52– REV. A ADuC836 TCON Timer/Counter 0 and 1 Control Register SFR Address Power-On Default Value Bit Addressable 88H 00H Yes Table XXVII. TCON SFR Bit Designations Bit Name Description 7 TF1 Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine. 6 TR1 Timer 1 Run Control Bit. Set by user to turn on Timer/Counter 1. Cleared by user to turn off Timer/Counter 1. 5 TF0 Timer 0 Overflow Flag. Set by hardware on a Timer/Counter 0 overflow. Cleared by hardware when the PC vectors to the interrupt service routine. 4 TR0 Timer 0 Run Control Bit. Set by user to turn on Timer/Counter 0. Cleared by user to turn off Timer/Counter 0. 3 IE1* External Interrupt 1 (INT1) Flag. Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1, depending on bit IT1 state. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transitionactivated. If level-activated, the external requesting source rather than the on-chip hardware, controls the request flag. 2 IT1* External Interrupt 1 (IE1) Trigger Type. Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). Cleared by software to specify level-sensitive detection (i.e., zero level). 1 IE0* External Interrupt 0 (INT0) Flag. Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0, depending on bit IT0 state. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transitionactivated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 0 IT0* External Interrupt 0 (IE0) Trigger Type. Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). Cleared by software to specify level-sensitive detection (i.e., zero level). *These bits are not used in the control of Timer/Counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins. Timer/Counter 0 and 1 Data Registers Both Timer 0 and Timer 1 consist of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit register, depending on the timer mode configuration. TH0 and TL0 Timer 0 high byte and low byte. SFR Address = 8CH, 8AH, respectively. TH1 and TL1 Timer 1 high byte and low byte. SFR Address = 8DH, 8BH, respectively. REV. A –53– ADuC836 TIMER/COUNTER 0 AND 1 OPERATING MODES Mode 2 (8-Bit Timer/Counter with Auto Reload) The following paragraphs describe the operating modes for Timer/ Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for both Timer 0 and 1. Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 50. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which are preset by software. The reload leaves TH0 unchanged. Mode 0 (13-Bit Timer/Counter) Mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler. Figure 48 shows Mode 0 operation. CORE CLK* 12 C/ T = 0 CORE CLK* TL0 (8 BITS) 12 C/ T = 0 TL0 TH0 (5 BITS) (8 BITS) C/ T = 1 TF0 INTERRUPT TF0 C/ T = 1 INTERRUPT P3.4/T0 CONTROL TR0 P3.4/T0 CONTROL TR0 RELOAD TH0 (8 BITS) GATE P3.2/INT0 *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION) GATE P3.2/INT0 Figure 50. Timer/Counter 0, Mode 2 *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION) Mode 3 (Two 8-Bit Timer/Counters) Figure 48. Timer/Counter 0, Mode 0 In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer overflow flag. The overflow flag, TF0, can then be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the timer to be controlled by external input INT0 to facilitate pulsewidth measurements. TR0 is a control bit in the special function register TCON; Gate is in TMOD. The 13-bit register consists of all eight bits of TH0 and the lower five bits of TL0. The upper three bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. Mode 1 (16-Bit Timer/Counter) Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. This configuration is shown in Figure 51. TL0 uses the Timer 0 control bits: C/T, Gate, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the Timer 1 interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or it can still be used by the serial interface as a baud rate generator. In fact, it can be used in any application not requiring an interrupt from Timer 1 itself. Mode 1 is the same as Mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in Figure 49. CORE CLK* CORE CLK/12 12 C/ T = 0 CORE CLK* 12 C/ T = 0 TL0 TH0 (8 BITS) (8 BITS) INTERRUPT TL0 (8 BITS) TF0 TH0 (8 BITS) TF1 C/ T = 1 INTERRUPT P3.4/T0 TF0 CONTROL TR0 C/ T = 1 P3.4/T0 TR0 CONTROL GATE P3.2/INT0 GATE CORE CLK/12 P3.2/INT0 INTERRUPT TR1 *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION) *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION) Figure 49. Timer/Counter 0, Mode 1 Figure 51. Timer/Counter 0, Mode 3 –54– REV. A ADuC836 TIMER/COUNTER 2 OPERATING MODES 16-Bit Capture Mode The following paragraphs describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR, as shown in Table XXIX. Capture Mode has two options, which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter that, upon overflowing, sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt. If EXEN2 = 1, Timer 2 still performs the above, but a l-to-0 transition on external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set; EXF2, like TF2, can generate an interrupt. Capture mode is illustrated in Figure 53. Table XXVIII. Timer 2 Operating Modes RCLK (or) TCLK CAP2 TR2 MODE 0 0 1 X 0 1 X X 1 1 1 0 16-Bit Autoreload 16-Bit Capture Baud Rate OFF The baud rate generator mode is selected by RCLK = 1 and/or TCLK = 1. 16-Bit Autoreload Mode Autoreload mode has two options, which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, when Timer 2 rolls over, it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2L and RCAP2H, which are preset by software. If EXEN2 = 1, Timer 2 still performs the above, but with the added feature that a 1-to-0 transition at external input T2EX will also trigger the 16-bit reload and set EXF2. The Autoreload mode is illustrated in Figure 52. CORE CLK* 12 In either case, if Timer 2 is being used to generate the baud rate, the TF2 interrupt flag will not occur. Therefore Timer 2 interrupts will not occur so they do not have to be disabled. However, in this mode, the EXF2 flag can still cause interrupts and this can be used as a third external interrupt. Baud rate generation will be described as part of the UART serial port operation. C/ T2 = 0 C/ T2 = 1 T2 PIN TL2 (8 BITS) TH2 (8 BITS) RCAP2L RCAP2H CONTROL TR2 RELOAD TRANSITION DETECTOR TF2 TIMER INTERRUPT T2EX PIN EXF2 CONTROL EXEN2 *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION) Figure 52. Timer/Counter 2, 16-Bit Autoreload Mode CORE CLK* 12 C/ T2 = 0 TL2 (8 BITS) C/ T2 = 1 T2 PIN TH2 (8 BITS) TF2 CONTROL TR2 TIMER INTERRUPT CAPTURE TRANSITION DETECTOR RCAP2L T2EX PIN RCAP2H EXF2 CONTROL EXEN2 *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION) Figure 53. Timer/Counter 2, 16-Bit Capture Mode REV. A –55– ADuC836 T2CON Timer/Counter 2 Control Register SFR Address Power-On Default Value Bit Addressable C8H 00H Yes Table XXIX. T2CON SFR Bit Designations Bit Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1. Cleared by user software. 6 EXF2 Timer 2 External Flag. Set by hardware when either a capture or a reload is caused by a negative transition in T2EX and EXEN2 = 1. Cleared by user software. 5 RCLK Receive Clock Enable Bit. Set by user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. Cleared by user to enable Timer 1 overflow to be used for the receive clock. 4 TCLK Transmit Clock Enable Bit. Set by user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. Cleared by user to enable Timer 1 overflow to be used for the transmit clock. 3 EXEN2 Timer 2 External Enable Flag. Set by user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. Cleared by user for Timer 2 to ignore events at T2EX. 2 TR2 Timer 2 Start/Stop Control Bit. Set by user to start Timer 2. Cleared by user to stop Timer 2. 1 CNT2 Timer 2 Timer or Counter Function Select Bit. Set by user to select counter function (input from external T2 pin). Cleared by user to select timer function (input from on-chip core clock). 0 CAP2 Timer 2 Capture/Reload Select Bit. Set by user to enable captures on negative transitions in T2EX when EXEN2 = 1. Cleared by user to enable auto reloads with Timer 2 overflows or negative transitions in T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow. Timer/Counter 2 Data Registers Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and timer capture/reload registers. TH2 and TL2 Timer 2, data high byte and low byte. SFR Address = CDH, CCH, respectively. RCAP2H and RCAP2L Timer 2, Capture/Reload byte and low byte. SFR Address = CBH, CAH, respectively. –56– REV. A ADuC836 SBUF UART SERIAL INTERFACE The serial port is full-duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, the first byte will be lost. The physical interface to the serial data network is via pins RxD(P3.0) and TxD(P3.1), while the SFR interface to the UART comprises the following registers: SCON UART Serial Port Control Registers SFR Address Power-On Default Value Bit Addressable 98H 00H Yes The serial port receive and transmit registers are both accessed through the SBUF SFR (SFR address = 99H). Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. Table XXX. SCON SFR Bit Designations Bit Name Description 7 SM0 UART Serial Mode Select Bits. 6 SM1 These bits select the Serial Port operating mode as follows: SM0 SM1 Selected Operating Mode 0 0 Mode 0: Shift Register, fixed baud rate (fCORE/12) 0 1 Mode 1: 8-bit UART, variable baud rate 1 0 Mode 2: 9-bit UART, fixed baud rate (fCORE/64) or (fCORE/32) 1 1 Mode 3: 9-bit UART, variable baud rate 5 SM2 Multiprocessor Communication Enable Bit. Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared. In Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is cleared, RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is set, RI will not be activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will be set as soon as the byte of data has been received. 4 REN Serial Port Receive Enable Bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. 3 TB8 Serial Port Transmit (Bit 9). The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3. 2 RB8 Serial Port Receiver Bit 9. The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8. 1 TI Serial Port Transmit Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3. TI must be cleared by user software. 0 RI Serial Port Receive Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3. RI must be cleared by software. UART OPERATING MODES Mode 0: 8-Bit Shift Register Mode Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. The data is shifted out of the RxD line. The 8 bits are transmitted with the least significant bit (LSB) first, as shown in Figure 54. Reception is initiated when the Receive Enable bit (REN) is 1 and the Receive Interrupt bit (RI) is 0. When RI is cleared, the data is clocked into the RxD line and the clock pulses are output from the TxD line. REV. A MACHINE CYCLE 1 MACHINE CYCLE 2 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 MACHINE CYCLE 7 MACHINE CYCLE 8 S4 S5 S6 S1 S2 S3 S4 S5 S6 CORE CLK ALE RxD (DATA OUT) DATA BIT 0 DATA BIT 1 DATA BIT 6 DATA BIT 7 TxD (SHIFT CLOCK) Figure 54. UART Serial Port Transmission, Mode 0 –57– ADuC836 Mode 1: 8-Bit UART, Variable Baud Rate To transmit, the eight data bits must be written into SBUF. The ninth bit must be written to TB8 in SCON. When transmission is initiated, the eight data bits (from SBUF) are loaded onto the transmit shift register (LSB first). The contents of TB8 are loaded into the ninth bit position of the transmit shift register. Mode 1 is selected by clearing SM0 and setting SM1. Each data byte (LSB first) is preceded by a start bit (0) and followed by a stop bit (1). Therefore 10 bits are transmitted on TxD or received on RxD. The baud rate can be set by Timer 1 or Timer 2 (or both). Alternatively, a dedicated baud rate generator, Timer 3, is provided on-chip to generate high speed, very accurate baud rates. The transmission will start at the next valid baud rate clock. The TI flag is set as soon as the stop bit appears on TxD. Transmission is initiated by writing to SBUF. The “write to SBUF” signal also loads a 1 (stop bit) into the ninth bit position of the Transmit Shift Register. The data is output bit by bit until the stop bit appears on TxD and the transmit interrupt flag (TI) is automatically set, as shown in Figure 55. Reception for Mode 2 is similar to that of Mode 1. The eight data bytes are input at RxD (LSB first) and loaded onto the Receive Shift Register. When all eight bits have been clocked in, the following events occur: TxD START BIT D0 STOP BIT D1 D2 D3 D4 D5 D6 D7 TI (SCON.1) The eight bits in the Receive Shift Register are latched into SBUF. The ninth data bit is latched into RB8 in SCON. The Receiver Interrupt flag (RI) is set. If, and only if, the following conditions are met at the time the final shift pulse is generated: SET INTERRUPT i.e., READY FOR MORE DATA Figure 55. UART Serial Port Transmission, Mode 0 RI = 0, and Reception is initiated when a 1-to-0 transition is detected on RxD. Assuming a valid start bit was detected, character reception continues. The start bit is skipped and the eight data bits are clocked into the serial port shift register. When all eight bits have been clocked in, the following events occur: Either SM2 = 0, or SM2 = 1 and the received stop bit = 1. If either of these conditions is not met, the received frame is irretrievably lost and RI is not set. Mode 3: 9-Bit UART with Variable Baud Rate Mode 3 is selected by setting both SM0 and SM1. In this mode, the 8051 UART serial port operates in 9-bit mode with a variable baud rate determined by either Timer 1 or Timer 2. The operation of the 9-bit UART is the same as for Mode 2, but the baud rate can be varied as for Mode 1. The eight bits in the Receive Shift Register are latched into SBUF. The ninth bit (stop bit) is clocked into RB8 in SCON. The Receiver Interrupt flag (RI) is set. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. If, and only if, the following conditions are met at the time, the final shift pulse is generated: RI = 0, and Either SM2 = 0, or SM2 = 1 and the Received Stop Bit = 1. UART Serial Port Baud Rate Generation Mode 0 Baud Rate Generation If either of these conditions is not met, the received frame is irretrievably lost and RI is not set. The baud rate in Mode 0 is fixed: Mode 0 Baud Rate = Mode 2: 9-Bit UART with Fixed Baud Rate Mode 2 is selected by setting SM0 and clearing SM1. In this mode, the UART operates in 9-bit mode with a fixed baud rate. The baud rate is fixed at Core_Clk/64 by default, although by setting the SMOD bit in PCON, the frequency can be doubled to Core_Clk/32. Eleven bits are transmitted or received, a start bit (0), eight data bits, a programmable ninth bit, and a stop bit (1). The ninth bit is most often used as a parity bit, although it can be used for anything, including a ninth data bit if required. fCORE * 12 Mode 2 Baud Rate Generation The baud rate in Mode 2 depends on the value of the SMOD bit in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the core clock. If SMOD = 1, the baud rate is 1/32 of the core clock: Mode 2 Baud Rate = fCORE * × 2SMOD 64 Mode 1 and 3 Baud Rate Generation Traditionally, the baud rates in Modes 1 and 3 are determined by the overflow rate in Timer 1 or Timer 2, or both (one for transmit and the other for receive). On the ADuC836, however, the baud rate can also be generated via a separate baud rate generator to achieve higher baud rates and allow all three to be used for other functions. *fCORE refers to the output of the PLL as described in the On-Chip PLL section. –58– REV. A ADuC836 BAUD RATE GENERATION USING TIMER 1 AND TIMER 2 Timer 1 Generated Baud Rates Timer 2 Generated Baud Rates Baud rates can also be generated using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted/received. Because Timer 2 has a 16-bit Autoreload mode, a wider range of baud rates is possible. When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: ( ) Modes 1 and 3 Baud Rate = 2SMOD ⁄ 32 × (Timer 1 Overflow Rate) Mode 1 and Mode 3 Baud Rate = (1 16) × (Timer 2 Overflow Rate) The Timer 1 interrupt should be disabled in this application. The timer itself can be configured for either timer or counter operation, and in any of its three running modes. In the most typical application, it is configured for timer operation, in the Autoreload mode (high nibble of TMOD = 0100 binary). In this case, the baud rate is given by the formula: Therefore when Timer 2 is used to generate baud rates, the timer increments every two clock cycles and not every core machine cycle as before. Thus, it increments six times faster than Timer 1, and therefore baud rates six times faster are possible. Because Timer 2 has a 16-bit autoreload capability, very low baud rates are still possible. Mode 1 and Mode 3 Baud Rate = Timer 2 is selected as the baud rate generator by setting the TCLK and/or RCLK in T2CON. The baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 56. In this case, the baud rate is given by the formula: fCORE Mode 1 and Mode 3 Baud Rate = 32 × (65536 − RCAP2H L) 2SMOD × fCORE 32 × 12 (256 − TH1) A very low baud rate can also be achieved with Timer 1 by leaving the Timer 1 interrupt enabled, configuring the timer to run as a 16-bit timer (high nibble of TMOD = 0100 binary), and using the Timer 1 interrupt to do a 16-bit software reload. Table XXXI shows some commonly used baud rates and how they might be calculated from a core clock frequency of 1.5728 MHz and 12.58 MHz using Timer 1. Generally speaking, a 5% error is tolerable using asynchronous (start/stop) communications. Table XXXII shows some commonly used baud rates and how they might be calculated from a core clock frequency of 1.5728 MHz and 12.5829 MHz using Timer 2. Table XXXI. Commonly Used Baud Rates, Timer 1 Table XXXII. Commonly Used Baud Rates, Timer 2 Ideal Baud Core CLK SMOD Value TH1-Reload Value Actual Baud % Error Ideal Baud Core CLK RCAP2H Value RCAP2L Value Actual Baud % Error 9600 1600 1200 1200 12.58 12.58 12.58 1.57 1 1 1 1 –7 (F9H) –27 (E5H) –55 (C9H) –7 (F9H) 9362 1627 1192 1170 2.5 1.1 0.7 2.5 19200 9600 1600 1200 9600 1600 1200 12.58 12.58 12.58 12.58 1.57 1.57 1.57 –1 (FFH) –1 (FFH) –1 (FFH) –2 (FEH) –1 (FFH) –1 (FFH) –1 (FFH) –20 (ECH) –41 (D7H) –164 (5CH) –72 (B8H) –5 (FBH) –20 (ECH) –41 (D7H) 19661 9591 2398 1199 9830 1658 1199 2.4 0.1 0.1 0.1 2.4 2.4 0.1 TIMER 1 OVERFLOW 2 OSC. FREQ. IS DIVIDED BY 2, NOT 12. 0 CORE CLK* T2 PIN 2 C/ T2 = 0 SMOD TL2 (8 BITS) TH2 (8 BITS) TIMER 2 OVERFLOW 0 RCLK 16 1 NOTE AVAILABILITY OF ADDITIONAL EXTERNAL INTERRUPT RELOAD RCAP2L T2EX PIN EXF 2 RCAP2H TIMER 2 INTERRUPT CONTROL EXEN2 *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION) Figure 56. Timer 2, UART Baud Rates REV. A 1 C/ T2 = 1 TR2 TRANSITION DETECTOR 1 CONTROL –59– RX CLOCK 0 TCLK 16 TX CLOCK ADuC836 BAUD RATE GENERATION USING TIMER 3 The high integer dividers in a UART block means that high speed baud rates are not always possible using some particular crystals, e.g., using a 12 MHz crystal, a baud rate of 115200 is not possible. To address this problem, the ADuC836 has added a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates. Timer 3 can be used instead of Timer 1 or Timer 2 for generating very accurate high speed UART baud rates including 115200 and 230400. Timer 3 also allows a much wider range of baud rates to be obtained. In fact, every desired bit rate from 12 bits to 393216 bits can be generated to within an error of ±0.8%. Timer 3 also frees up the other three timers allowing them to be used for different applications. A block diagram of Timer 3 is shown in Figure 57. CORE CLK* FRACTIONAL DIVIDER TIMER 1/TIMER 2 TX CLOCK (FIG 44) T 3FD = 1 1 2 × fCORE 2 DIV 0 RX CLOCK 0 − 64 DIV = log (12582912/32 × 115200) / log 2 = 1.77 = 1 ( Two SFRs (T3CON and T3FD) are used to control Timer 3. T3CON is the baud rate control SFR, allowing Timer 3 to be used to set up the UART baud rate, and setting up the binary divider (DIV). Table XXXIII. T3CON SFR Bit Designations ) T 3FD = (2 × 12.582912) 21 × 115200 − 64 = 45.22 = 2Dh TX CLOCK *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION) Figure 57. Timer 3, UART Baud Rates 2 × fCORE 2DIV × (T 3FD + 64) For a baud rate of 115200 while operating from the maximum core frequency (CD = 0), we have: T3EN T3 RX/TX CLOCK × Baud Rate Actual Baud Rate = TIMER 1/TIMER 2 RX CLOCK (FIG 44) 2DIV 16 T3FD is the fractional divider ratio required to achieve the required baud rate. We can calculate the appropriate value for T3FD using the following formula. Note that the T3FD should be rounded to the nearest integer. Once the values for DIV and T3FD are calculated, the actual baud rate can be calculated using the following formula: 2 (1 + T3FD/64) The appropriate value to write to the DIV2-1-0 bits can be calculated using the following formula where fCORE is the output of the PLL, as described in the On-Chip PLL section. Note that the DIV value must be rounded down. fCORE log 32 × Baud Rate DIV = log (2) Therefore, the actual baud rate is 115439 bits. Table XXXIV. Commonly Used Baud Rates Using Timer 3 Ideal Baud CD DIV T3CON T3FD % Error 230400 0 0 80H 2DH 0.2 Bit Name Description 115200 115200 0 1 1 0 81H 80H 2DH 2DH 0.2 0.2 7 T3EN Set to enable Timer 3 to generate the baud rate. When set PCON.7, T2CON.4 and T2CON.5 are ignored. Cleared to let the baud rate be generated as per a standard 8052. 57600 57600 57600 0 1 2 2 1 0 82H 81H 80H 2DH 2DH 2DH 0.2 0.2 0.2 6 ––– Reserved for Future Use 5 ––– Reserved for Future Use 4 ––– Reserved for Future Use 3 ––– Reserved for Future Use 38400 38400 38400 38400 0 1 2 3 3 2 1 0 83H 82H 81H 80H 12H 12H 12H 12H 0.1 0.1 0.1 0.1 2 DIV2 Binary Divider Factor 1 DIV1 DIV2 DIV1 DIV0 Bin Divider 0 DIV0 0 0 0 0 1 1 1 1 19200 19200 19200 19200 19200 0 1 2 3 4 4 3 2 1 0 84H 83H 82H 81H 80H 12H 12H 12H 12H 12H 0.1 0.1 0.1 0.1 0.1 9600 9600 9600 9600 9600 9600 38400 0 1 2 3 4 5 0 5 4 3 2 1 0 3 85H 84H 83H 82H 81H 80H 83H 12H 12H 12H 12H 12H 12H 12H 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 4 8 16 32 64 128 –60– REV. A ADuC836 INTERRUPT SYSTEM The ADuC836 provides a total of 11 interrupt sources with two priority levels. The control and configuration of the interrupt system are carried out through three interrupt-related SFRs: the IE (Interrupt Enable) Register, IP (Interrupt Priority Register), and IEIP2 (Secondary Interrupt Enable/Priority SFR) Registers. Their bit definitions are given in the Tables XXXV to XXXVII. IE Interrupt Enable Register SFR Address Power-On Default Value Bit Addressable A8H 00H Yes Table XXXV. IE SFR Bit Designations Bit Name Description 7 6 5 4 3 2 1 0 EA EADC ET2 ES ET1 EX1 ET0 EX0 Written by User to Enable 1 or Disable 0 All Interrupt Sources Written by User to Enable 1 or Disable 0 ADC Interrupt Written by User to Enable 1 or Disable 0 Timer 2 Interrupt Written by User to Enable 1 or Disable 0 UART Serial Port Interrupt Written by User to Enable 1 or Disable 0 Timer 1 Interrupt Written by User to Enable 1 or Disable 0 External Interrupt 1 Written by User to Enable 1 or Disable 0 Timer 0 Interrupt Written by User to Enable 1 or Disable 0 External Interrupt 0 IP Interrupt Priority Register SFR Address Power-On Default Value Bit Addressable B8H 00H Yes Table XXXVI. IP SFR Bit Designations Bit Name Description 7 6 5 4 3 2 1 0 ––– PADC PT2 PS PT1 PX1 PT0 PX0 Reserved for Future Use Written by User to Select ADC Interrupt Priority (1 = High; 0 = Low) Written by User to Select Timer 2 Interrupt Priority (1 = High; 0 = Low) Written by User to Select UART Serial Port Interrupt Priority (1 = High; 0 = Low) Written by User to Select Timer 1 Interrupt Priority (1 = High; 0 = Low) Written by User to Select External Interrupt 1 Priority (1 = High; 0 = Low) Written by User to Select Timer 0 Interrupt Priority (1 = High; 0 = Low) Written by User to Select External Interrupt 0 Priority (1 = High; 0 = Low) IEIP2 Secondary Interrupt Enable and Priority Register SFR Address Power-On Default Value Bit Addressable A9H A0H No Table XXXVII. IEIP2 SFR Bit Designations Bit Name Description 7 6 5 4 3 2 1 0 ––– PTI PPSM PSI ––– ETI EPSM ESI Reserved for Future Use Written by User to Select TIC Interrupt Priority (1 = High; 0 = Low) Written by User to Select Power Supply Monitor Interrupt Priority (1 = High; 0 = Low) Written by User to Select SPI/I2C Serial Port Interrupt Priority (1 = High; 0 = Low) Reserved. This bit must be 0. Written by User to Enable 1 or Disable 0 TIC Interrupt Written by User to Enable 1 or Disable 0 Power Supply Monitor Interrupt Written by User to Enable 1 or Disable 0 SPI/I2C Serial Port Interrupt REV. A –61– ADuC836 Interrupt Priority Interrupt Vectors The Interrupt Enable registers are written by the user to enable individual interrupt sources, while the Interrupt Priority registers allow the user to select one of two priority levels for each interrupt. An interrupt of a high priority may interrupt the service routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt will be serviced first. An interrupt cannot be interrupted by another interrupt of the same priority level. If two interrupts of the same priority level occur simultaneously, a polling sequence is used to determine which interrupt is serviced first. The polling sequence is shown in Table XXXVIII. When an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The interrupt vector addresses are shown in Table XXXIX. Table XXXIX. Interrupt Vector Addresses Table XXXVIII. Priority within an Interrupt Level Source Priority Description PSMI WDS IE0 RDY0/RDY1 TF0 IE1 TF1 ISPI/I2CI RI + TI TF2 + EXF2 TII 1 (Highest) 2 3 4 5 6 7 8 9 10 11 (Lowest) Power Supply Monitor Interrupt Watchdog Interrupt External Interrupt 0 ADC Interrupt Timer/Counter 0 Interrupt External Interrupt 1 Timer/Counter 1 Interrupt SPI Interrupt Serial Interrupt Timer/Counter 2 Interrupt Time Interval Counter Interrupt –62– Source Vector Address IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 RDY0/RDY1 (ADC) ISPI/I2CI PSMI TII WDS (WDIR = 1)* 0003H 000BH 0013H 001BH 0023H 002BH 0033H 003BH 0043H 0053H 005BH *The watchdog can be configured to generate an interrupt instead of a reset when it times out. This is used for logging errors or examining the internal status of the microcontroller core to understand, from a software debug point of view, why a watchdog timeout occurred. The watchdog interrupt is slightly different from the normal interrupts in that its priority level is always set to 1 and it is not possible to disable the interrupt via the global disable bit (EA) in the IE SFR. This is done to ensure that the interrupt will always be responded to if a watchdog timeout occurs. The watchdog will only produce an interrupt if the watchdog timeout is greater than zero. REV. A ADuC836 ADuC836 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC836 into any hardware system. External Memory Interface In addition to its internal program and data memories, the ADuC836 can access up to 64 Kbytes of external program memory (ROM, PROM, and so on) and up to 16 Mbytes of external data memory (SRAM). Though both external program memory and external data memory are accessed using some of the same pins, the two are completely independent of each other from a software point of view. For example, the chip can read/write external data memory while executing from external program memory. Figure 59 shows a hardware configuration for accessing up to 64 Kbytes of external data memory. This interface is standard to any 8051 compatible MCU. ADuC836 To select from which code space (internal or external program memory) to begin executing code, tie the EA (external access) pin high or low, respectively. When EA is high (pulled up to VDD), user program execution will start at Address 0 in the internal 62 Kbytes Flash/EE code space. When EA is low (tied to ground) user program execution will start at Address 0 in the external code space. When executing from internal code space, accesses to the program space above F7FFH (62 Kbytes) will be read as NOP instructions. ADuC836 D0–D7 (DATA) P0 LATCH A0–A7 ALE Note that a second very important function of the EA pin is described in the Single Pin Emulation Mode section. External program memory (if used) must be connected to the ADuC836, as illustrated in Figure 58. Sixteen I/O lines (Ports 0 and 2) are dedicated to bus functions during external program memory fetches. Port 0 (P0) serves as a multiplexed address/data bus. It emits the low byte of the program counter (PCL) as an address, and then goes into a high impedance input state awaiting the arrival of the code byte from the program memory. During the time that the low byte of the program counter is valid on P0, the signal ALE (Address Latch Enable) clocks this byte into an external address latch. Meanwhile, Port 2 (P2) emits the high byte of the program counter (PCH), and PSEN strobes the EPROM and the code byte is read into the ADuC836. SRAM P2 A8–A15 RD OE WR WE Figure 59. External Data Memory Interface (64 Kbytes Address Space) If access to more than 64 Kbytes of RAM is desired, a feature unique to the MicroConverter allows addressing up to 16 Mbytes of external RAM simply by adding an additional latch, as illustrated in Figure 60. SRAM ADuC836 D0–D7 (DATA) P0 LATCH A0–A7 ALE EPROM LATCH A8–A15 P2 D0–D7 (INSTRUCTION) P0 LATCH A0–A7 A16–A23 ALE P2 PSEN RD OE WR WE A8–A15 Figure 60. External Data Memory Interface (16 Mbytes Address Space) OE Figure 58. External Program Memory Interface Note that program memory addresses are always 16 bits wide, even in cases where the actual amount of program memory used is less than 64 Kbytes. External program execution sacrifices two of the 8-bit ports (P0 and P2) to the function of addressing the program memory. While executing from external program memory, Ports 0 and 2 can be used simultaneously for read/write access to external data memory, but not for general-purpose I/O. In either implementation, Port 0 (P0) serves as a multiplexed address/data bus. It emits the low byte of the data pointer (DPL) as an address, which is latched by ALE prior to data being placed on the bus by the ADuC836 (write operation) or by the external data memory (read operation). Port 2 (P2) provides the data pointer page byte (DPP) to be latched by ALE, followed by the data pointer high byte (DPH). If no latch is connected to P2, DPP is ignored by the SRAM, and the 8051 standard of 64 Kbyte external data memory access is maintained. Detailed timing diagrams of external program and data memory read and write access can be found in the Timing Specifications section. REV. A –63– ADuC836 Power Supplies The ADuC836’s operational power supply voltage range is 2.7 V to 5.25 V. Although the guaranteed data sheet specifications are given only for power supplies within 2.7 V to 3.6 V or +5% of the nominal 5 V level, the chip will function equally well at any power supply level between 2.7 V and 5.25 V. Separate analog and digital power supply pins (AVDD and DVDD, respectively) allow AVDD to be kept relatively free of noisy digital signals that are often present on the system DVDD line. In this mode, the part can also operate with split supplies, that is, using different voltage supply levels for each supply. For example, this means that the system can be designed to operate with a DVDD voltage level of 3 V while the AVDD level can be at 5 V, or vice-versa if required. A typical split-supply configuration is shown in Figure 61. ANALOG SUPPLY DIGITAL SUPPLY 10F 10F + – 20 34 + – ADuC836 DVDD AVDD 5 0.1F Notice that in Figures 61 and 62, a large value (10 F) reservoir capacitor sits on DVDD and a separate 10 F capacitor sits on AVDD. Also, local decoupling capacitors (0.1 F) are located at each VDD pin of the chip. As per standard design practice, be sure to include all of these capacitors and ensure the smaller capacitors are closest to each VDD pin with lead lengths as short as possible. Connect the ground terminal of each of these capacitors directly to the underlying ground plane. Finally, it should also be noticed that, at all times, the analog and digital ground pins on the ADuC836 should be referenced to the same system ground reference point. Power-On Reset (POR) Operation An internal POR (Power-On Reset) is implemented on the ADuC836. For DVDD below 2.45 V, the internal POR will hold the ADuC836 in reset. As DVDD rises above 2.45 V, an internal timer will time out for typically 128 ms before the part is released from reset. The user must ensure that the power supply has reached a stable 2.7 V minimum level by this time. Likewise on power-down, the internal POR will hold the ADuC836 in reset until the power supply has dropped below 1 V. Figure 63 illustrates the operation of the internal POR in detail. 48 0.1F DVDD 21 35 DGND AGND 6 2.45V TYP 1.0V TYP 128ms TYP 128ms TYP 1.0V TYP 47 INTERNAL CORE RESET Figure 61. External Dual-Supply Connections As an alternative to providing two separate power supplies, AVDD can be kept quiet by placing a small series resistor and/or ferrite bead between it and DVDD, and then decoupling AVDD separately to ground. An example of this configuration is shown in Figure 62. In this configuration, other analog circuitry (such as op amps, voltage reference, and so on) can be powered from the AVDD supply line as well. DIGITAL SUPPLY + – 10F BEAD 20 34 1.6 10F ADuC836 DVDD AVDD 5 AGND 6 0.1F 48 0.1F 21 35 47 DGND Figure 63. Internal Power-on-Reset Operation Power Consumption The DVDD power supply current consumption is specified in normal, idle, and power-down modes. The AVDD power supply current is specified with the analog peripherals disabled. The normal mode power consumption represents the current drawn from DVDD by the digital core. The other on-chip peripherals (watchdog timer, power supply monitor, and so on) consume negligible current and are therefore lumped in with the normal operating current here. Of course, the user must add any currents sourced by the parallel and serial I/O pins, and those sourced by the DAC in order to determine the total current needed at the ADuC836’s DVDD and AVDD supply pins. Also, current drawn from the DVDD supply will increase by approximately 5 mA during Flash/EE erase and program cycles. Figure 62. External Single-Supply Connections –64– REV. A ADuC836 Power Saving Modes Wake-Up from Power-Down Latency Setting the Idle and Power-Down Mode Bits, PCON.0 and PCON.1, respectively, in the PCON SFR described in Table II allows the chip to be switched from Normal mode into Idle mode, and also into full Power-Down mode. Even with the 32 kHz crystal enabled during power-down, the PLL will take some time to lock after a wake-up from power-down. Typically, the PLL will take about 1 ms to lock. During this time, code will execute, but not at the specified frequency. Some operations require an accurate clock, for example, UART communications, to achieve specified 50 Hz/60 Hz rejection from the ADCs. The following code may be used to wait for the PLL to lock: In Idle mode, the oscillator continues to run, but the core clock generated from the PLL is halted. The on-chip peripherals continue to receive the clock and remain functional. The CPU status is preserved with the stack pointer, program counter, and all other internal registers maintain their data during Idle mode. Port pins and DAC output pins also retain their states, and ALE and PSEN outputs go high in this mode. The chip will recover from Idle mode upon receiving any enabled interrupt, or upon receiving a hardware reset. WAITFORLOCK: MOV A, PLLCON JNB ACC.6, WAITFORLOCK If the crystal has been powered down during power-down, there is an additional delay associated with the startup of the crystal oscillator before the PLL can lock. 32 kHz crystals are inherently slow to oscillate, typically taking about 150 ms. Once again, during this time before lock, code will execute, but the exact frequency of the clock cannot be guaranteed. Again for any timing sensitive operations, it is recommended to wait for lock using the lock bit in PLLCON, as shown in the code above. In Power-Down mode, both the PLL and the clock to the core are stopped. The on-chip oscillator can be halted or can continue to oscillate, depending on the state of the oscillator power-down bit (OSC_PD) in the PLLCON SFR. The TIC, being driven directly from the oscillator, can also be enabled during power-down. All other on-chip peripherals, however, are shut down. Port pins retain their logic levels in this mode, but the DAC output goes to a high impedance state (three-state) while ALE and PSEN outputs are held low. During full Power-Down mode with the oscillator and wake-up timer running, the ADuC836 typically consumes a total of 15 A. There are five ways of terminating Power-Down mode: Grounding and Board Layout Recommendations As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC836 based designs in order to achieve optimum performance from the ADCs and DAC. Although the ADuC836 has separate pins for analog and digital ground (AGND and DGND), the user must not tie these to two separate ground planes unless the two ground planes are connected together very close to the ADuC836, as illustrated in the simplified example of Figure 64a. In systems where digital and analog ground planes are connected together somewhere else (at the system’s power supply, for example), they cannot be connected again near the ADuC836 since a ground loop would result. In these cases, tie the ADuC836’s AGND and DGND pins all to the analog ground plane, as illustrated in Figure 64b. In systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa. The ADuC836 can then be placed between the digital and analog sections, as illustrated in Figure 64c. Asserting the RESET Pin (Pin 15) Returns to Normal mode. All registers are set to their reset default value and program execution starts at the reset vector once the RESET pin is deasserted. Cycling Power All registers are set to their default state and program execution starts at the reset vector approximately 128 ms later. Time Interval Counter (TIC) Interrupt If the OSC_PD bit in the PLLCON SFR is clear, the 32 kHz oscillator will remain powered up even in Power-Down mode. If the Time Interval Counter (Wakeup/RTC timer) is enabled, a TIC interrupt will wake the ADuC836 up from Power-Down mode. The CPU services the TIC interrupt. The RETI at the end of the TIC ISR will return the core to the instruction after the one that enabled power-down. SPI Interrupt If the SERIPD bit in the PCON SFR is set, then an SPI interrupt, if enabled, will wake up the ADuC836 from Power-Down mode. The CPU services the SPI interrupt. The RETI at the end of the ISR will return the core to the instruction after the one that enabled power-down. INT0 Interrupt If the INT0PD bit in the PCON SFR is set, an external interrupt 0, if enabled, will wake up the ADuC836 from power-down. The CPU services the SPI interrupt. The RETI at the end of the ISR will return the core to the instruction after the one that enabled power-down. REV. A In all of these scenarios, and in more complicated real-life applications, keep in mind the flow of current from the supplies and back to ground. Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. For example, do not power components on the analog side of Figure 64b with DVDD since that would force return currents from DVDD to flow through AGND. Also, try to avoid digital currents flowing under analog circuitry, which could happen if the user placed a noisy digital chip on the left half of the board in Figure 64c. Whenever possible, avoid large discontinuities in the ground plane(s) (such as those formed by a long trace on the same layer), since they force return signals to travel a longer path. And of course, make all connections directly to the ground plane with little or no trace separating the pin from its via to ground. –65– ADuC836 a. PLACE DIGITAL COMPONENTS HERE PLACE ANALOG COMPONENTS HERE AGND DGND The CHIPID SFR is a read-only register located at SFR address C2H. The upper nibble of this SFR designates the MicroConverter within the - ADC family. User software can read this SFR to identify the host MicroConverter and thus execute slightly different code if required. The CHIPID SFR reads as follows for the - ADC family of MicroConverter products. ADuC836 ADuC834 ADuC824 ADuC816 b. PLACE ANALOG COMPONENTS HERE PLACE DIGITAL COMPONENTS HERE AGND c. DGND PLACE ANALOG COMPONENTS HERE PLACE DIGITAL COMPONENTS HERE GND Figure 64. System Grounding Schemes If the user plans to connect fast logic signals (rise/fall time < 5 ns) to any of the ADuC836’s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the ADuC836 input pins. A value of 100 or 200 is usually sufficient to prevent high speed signals from coupling capacitively into the ADuC836 and affecting the accuracy of ADC conversions. Clock Oscillator As described earlier, the core clock frequency for the ADuC836 is generated from an on-chip PLL that locks onto a multiple (384 times) of 32.768 kHz. The latter is generated from an internal clock oscillator. To use the internal clock oscillator, connect a 32.768 kHz parallel resonant crystal between the XTAL1 and XTAL2 pins (32 and 33), as shown in Figure 65. As shown in the typical external crystal connection diagram in Figure 65, two internal 12 pF capacitors are provided on-chip. These are connected internally, directly to the XTAL1 and XTAL2 pins, and the total input capacitances at both pins is detailed in the Specifications table. The value of the total load capacitance required for the external crystal should be the value recommended by the crystal manufacturer for use with that specific crystal. In many cases, because of the on-chip capacitors, additional external load capacitors will not be required. ADuC836 XTAL1 32 32.768kHz 12pF 33 ADuC836 System Self-Identification In some hardware designs, it may be an advantage for the software running on the ADuC836 target to identify the host MicroConverter. For example, code running on the ADuC836 may also be used with the ADuC824 or the ADuC816, and is required to operate differently. CHIPID = 3xH CHIPID = 2xH CHIPID = 0xH CHIPID = 1xH XTAL2 12pF TO INTERNAL PLL Figure 65. External Parallel Resonant Crystal Connections Other Hardware Considerations To facilitate in-circuit programming plus in-circuit debug and emulation options, users will want to implement some simple connection points in their hardware that will allow easy access to Download, Debug, and Emulation modes. –66– REV. A ADuC836 OTHER HARDWARE CONSIDERATIONS In-Circuit Serial Download Access Nearly all ADuC836 designs will want to take advantage of the in-circuit reprogrammability of the chip. This is accomplished by a connection to the ADuC836’s UART, which requires an external RS-232 chip for level translation if downloading code from a PC. Basic configuration of an RS-232 connection is illustrated in Figure 66 with a simple ADM3202 based circuit. If users would rather not include an RS-232 chip onto the target board, refer to the application note, uC006–A 4-Wire UART-to-PC Interface available at www.analog.com/microconverter, for a simple (and zero-cost-per-board) method of gaining in-circuit serial download access to the ADuC836. In addition to the basic UART connections, users will also need a way to trigger the chip into Download mode. This is accomplished via a 1 k pull-down resistor that can be jumpered onto the PSEN pin, as shown in Figure 66. To get the ADuC836 into Download mode, simply connect this jumper and power-cycle the device (or manually reset the device, if a manual reset button is available), and it will be ready to receive a new program serially. With the jumper removed, the device will power on in Normal mode (and run the program) whenever power is cycled or RESET is toggled. Note that PSEN is normally an output (as described in the External Memory Interface section) and that it is sampled as an input only on the falling edge of RESET (i.e., at power-up or upon an external manual reset). Note also that if any external circuitry unintentionally pulls PSEN low during power-up or reset events, it could cause the chip to enter Download mode and therefore fail to begin user code execution as it should. To prevent this, ensure REV. A that no external signals are capable of pulling the PSEN pin low, except for the external PSEN jumper itself. Embedded Serial Port Debugger From a hardware perspective, entry to Serial Port Debug mode is identical to the serial download entry sequence described above. In fact, both Serial Download and Serial Port Debug modes can be thought of as essentially one mode of operation used in two different ways. Note that the serial port debugger is fully contained on the ADuC836 device, (unlike ROM monitor type debuggers) and therefore no external memory is needed to enable in-system debug sessions. Single-Pin Emulation Mode Also built into the ADuC836 is a dedicated controller for single-pin in-circuit emulation (ICE) using standard production ADuC836 devices. In this mode, emulation access is gained by connection to a single pin, the EA pin. Normally, this pin is hard-wired either high or low to select execution from internal or external program memory space, as described earlier. To enable single-pin emulation mode, however, users will need to pull the EA pin high through a 1 k resistor, as shown in Figure 66. The emulator will then connect to the 2-pin header also shown in Figure 66. To be compatible with the standard connector that comes with the single-pin emulator available from Accutron Limited (www.accutron.com), use a 2-pin 0.1-inch pitch Friction Lock header from Molex (www.molex.com) such as their part number 22-27-2021. Be sure to observe the polarity of this header. As represented in Figure 66, when the Friction Lock tab is at the right, the ground pin should be the lower of the two pins (when viewed from the top). –67– ADuC836 Typical System Configuration its resistance. This differential voltage is routed directly to the positive and negative inputs of the primary ADC (AIN1, AIN2, respectively). The same current that excited the RTD also flows through a series resistance RREF, generating a ratiometric voltage reference VREF. The ratiometric voltage reference ensures that variations in the excitation current do not affect the measurement system as the input voltage from the RTD and reference voltage across RREF vary ratiometrically with the excitation current. Resistor RREF must, however, have a low temperature coefficient to avoid errors in the reference voltage over temperature. RREF must also be large enough to generate at least a 1 V voltage reference. A typical ADuC836 configuration is shown in Figure 66. It summarizes some of the hardware considerations discussed in the previous paragraphs. Figure 66 also includes connections for a typical analog measurement application of the ADuC836, namely an interface to an RTD (Resistive Temperature Device). The arrangement shown is commonly referred to as a 4-wire RTD configuration. Here, the on-chip excitation current sources are enabled to excite the sensor. The excitation current flows directly through the RTD, generating a voltage across the RTD proportional to DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) DVDD 1k DVDD 49 48 45 44 43 42 P1.2/IEXC1/DAC 200A/400A EXCITATION CURRENT AVDD 39 38 36 AVDD DVDD DGND 35 AGND DVDD 34 ADuC836 REFIN– XTAL2 33 XTAL1 32 REFIN+ RREF 5.6k 40 2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN) 37 P1.3/AIN5/DAC RTD 41 EA 50 46 PSEN 51 DVDD 52 47 DGND 1k P1.4/AIN1 31 P1.5/AIN2 30 32.768kHz DVDD 28 DGND DVDD TXD RXD RESET 29 27 NOT CONNECTED IN THIS EXAMPLE DVDD ALL CAPACITORS IN THIS EXAMPLE ARE 0.1F CERAMIC CAPACITORS. RS232 INTERFACE* ADM3202 C1+ V+ VCC STANDARD D-TYPE SERIAL COMMS CONNECTOR TO PC HOST GND 1 C1– T1OUT 2 C2+ R1IN 3 C2– R1OUT 4 V– T1IN 5 T2OUT T2IN 6 R2OUT 7 R2IN 8 9 *EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS PART OF AN EXTERNAL DONGLE AS DESCRIBED IN uC006. Figure 66. Typical System Configuration –68– REV. A ADuC836 QUICKSTART DEVELOPMENT SYSTEM The QuickStart Development System is a full featured, low cost development tool suite supporting the ADuC836. The system consists of the following PC based (Windows® compatible) hardware and software development tools: Hardware: ADuC836 Evaluation Board and Serial Port Cable Code Development: 8051 Assembler Code Functionality: ADSIM, Windows MicroConverter Code Simulator In-Circuit Code Download: Serial Downloader In-Circuit Debugger/Emulator: Serial Port/Single Pin Debugger/Emulator with Assembly and C Source Debug Miscellaneous Other: CD-ROM Documentation and Two Additional Prototype Devices Figure 67 shows the typical components of a QuickStart Development System while Figure 68 shows a typical debug session. A brief description of some of the software tools’ components in the QuickStart Development System follows. Download—In Circuit Downloader The Serial Downloader is a software program that allows the user to serially download an assembled program (Intel Hex format file) to the on-chip program Flash memory via the serial COM1 port on a standard PC. Application Note uC004 details this serial download protocol and is available from www.analog.com/microconverter. Debugger/Emulator—In-Circuit Debugger/Emulator The Debugger/Emulator is a Windows application that allows the user to debug code execution on silicon using the MicroConverter UART serial port or via a single pin to provide nonintrusive debug. The debugger provides access to all on-chip peripherals during a typical debug session, including single-step and multiple break-point code execution control. C source and assembly level debug are both possible with the emulator. ADSIM—Windows Simulator The Simulator is a Windows application that fully simulates the MicroConverter functionality including ADC and DAC peripherals. The simulator provides an easy-to-use, intuitive, interface to the MicroConverter functionality and integrates many standard debug features including multiple breakpoints, single stepping, and code execution trace capability. This tool can be used both as a tutorial guide to the part as well as an efficient way to prove code functionality before moving to a hardware platform. Figure 68. Typical Debug Session Figure 67. Components of the QuickStart Development System REV. A –69– ADuC836 TIMING SPECIFICATIONS1, 2, 3 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise noted.) Parameter 32.768 kHz External Crystal Typ Max Min CLOCK INPUT (External Clock Driven XTAL1) tCK XTAL1 Period tCKL XTAL1 Width Low tCKH XTAL1 Width High tCKR XTAL1 Rise Time tCKF XTAL1 Fall Time 1/tCORE ADuC836 Core Clock Frequency4 tCORE ADuC836 Core Clock Period5 tCYC ADuC836 Machine Cycle Time6 30.52 6.26 6.26 9 9 0.098 s s s s s MHz s s 12.58 0.636 7.6 0.95 Unit 122.45 NOTES 1 AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1, and 0.45 V for a Logic 0. Timing measurements are made at VIH min for a Logic 1, and VIL max for a Logic 0, as shown in Figure 70. 2 For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs, as shown in Figure 70. 3 CLOAD for Port 0, ALE, PSEN outputs = 100 pF; CLOAD for all other outputs = 80 pF, unless otherwise noted. 4 ADuC836 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a stable 12.583 MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR. 5 This number is measured at the default Core_Clk operating frequency of 1.57 MHz. 6 ADuC836 Machine Cycle Time is nominally defined as 12/Core_Clk. tCKR tCKH tCKL tCKF tCK Figure 69. XTAL1 Input DVDD – 0.5V 0.45V 0.2DVDD + 0.9V TEST POINTS 0.2DVDD – 0.1V VLOAD – 0.1V VLOAD VLOAD + 0.1V TIMING REFERENCE POINTS VLOAD – 0.1V VLOAD VLOAD + 0.1V Figure 70. Timing Waveform Characteristics –70– REV. A ADuC836 Parameter EXTERNAL PROGRAM MEMORY tLHLL ALE Pulsewidth tAVLL Address Valid to ALE Low tLLAX Address Hold after ALE Low tLLIV ALE Low to Valid Instruction In tLLPL ALE Low to PSEN Low tPLPH PSEN Pulsewidth tPLIV PSEN Low to Valid Instruction In tPXIX Input Instruction Hold after PSEN tPXIZ Input Instruction Float after PSEN tAVIV Address to Valid Instruction In tPLAZ PSEN Low to Address Float tPHAX Address Hold after PSEN High 12.58 MHz Core_Clk Min Max Min 119 39 49 2tCORE – 40 tCORE – 40 tCORE – 30 218 49 193 tCORE – 30 3tCORE – 45 133 0 0 54 292 25 0 Variable Core_Clk Max 0 tLHLL ALE (O) tPLPH tLLPL tLLIV tPLIV PSEN (O) PORT 0 (I/O) tPXIZ tPLAZ tLLAX tPXIX PCL (OUT) INSTRUCTION (IN) tAVIV PORT 2 (O) tPHAX PCH Figure 71. External Program Memory Read Cycle REV. A –71– 3tCORE – 105 tCORE – 25 5tCORE – 105 25 CORE_CLK tAVLL 4tCORE – 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ADuC836 Parameter EXTERNAL DATA MEMORY READ CYCLE tRLRH RD Pulsewidth tAVLL Address Valid after ALE Low tLLAX Address Hold after ALE Low tRLDV RD Low to Valid Data In tRHDX Data and Address Hold after RD tRHDZ Data Float after RD tLLDV ALE Low to Valid Data In tAVDV Address to Valid Data In tLLWL ALE Low to RD Low tAVWL Address Valid to RD Low tRLAZ RD Low to Address Float tWHLH RD High to ALE High 12.58 MHz Core_Clk Min Max Min 377 39 44 6tCORE – 100 tCORE – 40 tCORE – 35 232 0 0 89 486 550 288 188 188 3tCORE – 50 4tCORE – 130 0 119 39 Variable Core_Clk Max tCORE – 40 5tCORE – 165 2tCORE – 70 8tCORE – 150 9tCORE – 165 3tCORE + 50 0 tCORE + 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns CORE_CLK ALE (O) tWHLH PSEN (O) tLLDV tLLWL tRLRH RD (O) tAVWL tAVLL PORT 0 (I/O) tLLAX tRLDV tRHDX tRHDZ tRLAZ A0–A7 (OUT) DATA (IN) tAVDV PORT 2 (O) A16–A23 A8–A15 Figure 72. External Data Memory Read Cycle –72– REV. A ADuC836 Parameter 12.58 MHz Core_Clk Min Max Min EXTERNAL DATA MEMORY WRITE CYCLE tWLWH WR Pulsewidth tAVLL Address Valid after ALE Low tLLAX Address Hold after ALE Low tLLWL ALE Low to WR Low tAVWL Address Valid to WR Low tQVWX Data Valid to WR Transition tQVWH Data Setup before WR tWHQX Data and Address Hold after WR tWHLH WR High to ALE High 377 39 44 188 188 29 406 29 39 6tCORE – 100 tCORE – 40 tCORE – 35 3tCORE – 50 4tCORE – 130 tCORE – 50 7tCORE – 150 tCORE – 50 tCORE – 40 288 119 Variable Core_Clk Max CORE_CLK ALE (O) tWHLH PSEN (O) tLLWL tWLWH WR (O) tAVWL tAVLL tLLAX PORT 0 (O) A0–A7 PORT 2 (O) A16–A23 tQVWX tWHQX tQVWH DATA A8–A15 Figure 73. External Data Memory Write Cycle REV. A –73– 3tCORE + 50 tCORE + 40 Unit ns ns ns ns ns ns ns ns ns ADuC836 Parameter 12.58 MHz Core_Clk Min Typ Max UART TIMING (Shift Register Mode) tXLXL Serial Port Clock Cycle Time tQVXH Output Data Setup to Clock tDVXH Input Data Setup to Clock tXHDX Input Data Hold after Clock tXHQX Output Data Hold after Clock 662 292 0 42 0.95 Variable Core_Clk Typ Min 10tCORE – 133 2tCORE + 133 0 2tCORE – 117 12tCORE Max Unit s ns ns ns ns ALE (O) tXLXL TxD (OUTPUT CLOCK) 01 67 SET RI OR SET TI tQVXH tXHQX RxD (OUTPUT DATA) BIT 6 MSB BIT 1 tDVXH RxD (INPUT DATA) MSB tXHDX BIT 1 BIT 6 LSB Figure 74. UART Timing in Shift Register Mode –74– REV. A ADuC836 Parameter Min SPI MASTER MODE TIMING (CPHA = 1) tSL SCLOCK Low Pulsewidth* tSH SCLOCK High Pulsewidth* tDAV Data Output Valid after SCLOCK Edge tDSU Data Input Setup Time before SCLOCK Edge tDHD Data Input Hold Time after SCLOCK Edge tDF Data Output Fall Time tDR Data Output Rise Time tSR SCLOCK Rise Time tSF SCLOCK Fall Time Typ Max 630 630 100 100 50 10 10 10 10 25 25 25 25 Unit ns ns ns ns ns ns ns ns ns *Characterized under the following conditions: Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 1.57 MHz, and SPI bit rate selection bits SPR1 and SPR0 in SPICON SFR are both set to 0. SCLOCK (CPOL = 0) tSH tSL tSF tSR SCLOCK (CPOL = 1) tDAV MOSI tDOSU tDF MSB MISO MSB IN tDSU tDR BITS 6–1 BITS 6–1 LSB LSB IN tDHD Figure 75. SPI Master Mode Timing (CPHA = 1) REV. A –75– ADuC836 Parameter Min SPI MASTER MODE TIMING (CPHA = 0) tSL SCLOCK Low Pulsewidth* tSH SCLOCK High Pulsewidth* tDAV Data Output Valid after SCLOCK Edge tDOSU Data Output Setup before SCLOCK Edge tDSU Data Input Setup Time before SCLOCK Edge tDHD Data Input Hold Time after SCLOCK Edge tDF Data Output Fall Time tDR Data Output Rise Time tSR SCLOCK Rise Time tSF SCLOCK Fall Time Typ Max 630 630 100 100 50 150 10 10 10 10 25 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns *Characterized under the following conditions: 1. Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57 MHz. 2. SPI bit rate selection bits SPR1 and SPR0 in SPICON SFR are both set to 0. SCLOCK (CPOL = 0) tSH tSL tSR SCLOCK (CPOL = 1) tDAV tDF MOSI tDR BITS 6–1 MSB MISO BITS 6–1 MSB IN tDSU tSF LSB LSB IN tDHD Figure 76. SPI Master Mode Timing (CPHA = 0) –76– REV. A ADuC836 Parameter Min SPI SLAVE MODE TIMING (CPHA = 1) tSS SS to SCLOCK Edge tSL SCLOCK Low Pulsewidth tSH SCLOCK High Pulsewidth tDAV Data Output Valid after SCLOCK Edge tDSU Data Input Setup Time before SCLOCK Edge tDHD Data Input Hold Time after SCLOCK Edge tDF Data Output Fall Time tDR Data Output Rise Time tSR SCLOCK Rise Time tSF SCLOCK Fall Time tSFS SS High after SCLOCK Edge Typ 0 Max 330 330 100 100 ns ns ns ns ns ns ns ns ns ns ns 50 10 10 10 10 0 Unit 25 25 25 25 SS tSFS tSS SCLOCK (CPOL = 0) tSL tSH tSR tSF SCLOCK (CPOL = 1) tDAV tDF MISO MOSI BITS 6–1 MSB BITS 6–1 MSB IN tDSU tDR tDHD Figure 77. SPI Slave Mode Timing (CPHA = 1) REV. A –77– LSB LSB IN ADuC836 Parameter Min SPI SLAVE MODE TIMING (CPHA = 0) tSS SS to SCLOCK Edge tSL SCLOCK Low Pulsewidth tSH SCLOCK High Pulsewidth tDAV Data Output Valid after SCLOCK Edge tDSU Data Input Setup Time before SCLOCK Edge tDHD Data Input Hold Time after SCLOCK Edge tDF Data Output Fall Time tDR Data Output Rise Time tSR SCLOCK Rise Time tSF SCLOCK Fall Time tSSR SS to SCLOCK Edge tDOSS Data Output Valid after SS Edge tSFS SS High after SCLOCK Edge 0 100 100 Typ Max 330 330 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 50 10 10 10 10 25 25 25 25 50 20 0 SS tSFS tSS SCLOCK (CPOL = 0) tSH tSL tSF tSR SCLOCK (CPOL = 1) tDAV tDOSS tDF MISO MOSI MSB MSB IN tDSU tDR BITS 6–1 BITS 6–1 LSB LSB IN tDHD Figure 78. SPI Slave Mode Timing (CPHA = 0) –78– REV. A ADuC836 Parameter Min Max Unit 2 I C-SERIAL INTERFACE TIMING tL SCLOCK Low Pulsewidth tH SCLOCK High Pulsewidth tSHD Start Condition Hold Time tDSU Data Setup Time tDHD Data Hold Time tRSU Setup Time for Repeated Start tPSU Stop Condition Setup Time tBUF Bus Free Time between a STOP Condition and a START Condition tR Rise Time of Both SCLOCK and SDATA tF Fall Time of Both SCLOCK and SDATA tSUP* Pulsewidth of Spike Suppressed 4.7 4.0 0.6 100 µs µs µs ns µs µs µs µs 0.9 0.6 0.6 1.3 300 300 50 ns ns ns *Input filtering on both the SCLOCK and SDATA inputs surpresses noise spikes less than 50 ns. tBUF tSUP SDATA (I/O) MSB tDSU tPSU LSB tL tR tRSU 8 2-7 tF tDHD 9 tSUP 1 S(R) REPEATED START STOP START CONDITION CONDITION Figure 79. I 2C Compatible Interface Timing REV. A MSB tDSU tH 1 PS ACK tDHD tSHD SCLK (I) tR –79– tF ADuC836 OUTLINE DIMENSIONS 52-Lead Metric Quad Flat Package [MQFP] (S-52) Dimensions shown in millimeters 14.15 13.90 SQ 13.65 2.45 MAX 39 27 40 SEATING PLANE C02991–0–4/03(A) 1.03 0.88 0.73 26 7.80 REF 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) VIEW A PIN 1 52 14 1 0.23 0.11 13 0.65 BSC 0.38 0.22 2.10 2.00 1.95 7 0 0.10 MIN COPLANARITY VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MO-022-AC-1 56-Lead Lead Frame Chip Scale Package [LFCSP] 8 8 mm Body (CP-56) Dimensions shown in millimeters 8.00 BSC SQ 0.60 MAX 0.60 MAX 42 PIN 1 INDICATOR 7.75 BSC SQ TOP VIEW 0.20 REF 12 MAX PIN 1 INDICATOR 56 1 6.25 6.10 SQ 5.95 BOTTOM VIEW 0.50 0.40 0.30 1.00 0.90 0.80 43 0.30 0.23 0.18 29 28 15 14 6.50 REF 0.70 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2 Revision History Location Page 4/03—Data Sheet changed from REV. 0 to REV. A. Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 –80– REV. A