AKM AK8136A

AK8136A
Low Power
Multiclock Generator with VCXO
AK8136A
Features
Description
The AK8136A is a member of AKM’s low power
multi clock generator family designed for a feature
rich DTV or STB, requiring a range of system
clocks with high performance. The AK8136A
generates different frequency clocks from a 27MHz
crystal oscillator and provides them to up to four
outputs configured by register-setting. The on-chip
VCXO accepts a voltage control input to allow the
output clocks to vary by ±150 ppm for
synchronizing to the external clock system. Both
circuitries of VCXO and PLL in AK8136A are
derived from AKM’s long-term-experienced clock
device technology, and enable clock output to
perform low jitter and to operate with very low
current consumption. The AK8136A is available
in a 20-pin SSOP package.
27MHz Crystal Input
One 27MHz-Reference Output
2 wire serial register interface
Selectable Clock out Frequencies:
- 148.352, 148.5MHz
- 100.71, 108MHz
- 22.5792, 24.576, 33.8688, 36.864MHz
- 27.0MHz
Built-in VCXO
- Pull Range: ±150ppm (typ.)
Low Jitter Performance
- Period Jitter:
150 psec (Typ.) at CLK2,CLK3,CLK4
- TIE：
100 psec (Max) at CLK1p,CLK1n
- Long term jitter：
160 psec (Typ.) at REFOUT
Low Current Consumption:
32 mA (Typ.) at 3.3V
Supply Voltage:
3.0 – 3.6V
Operating Temperature Range:
-20 to +85℃
Package:
20-pin SSOP (Lead free, Halogen free)
Applications

Set-Top-Boxes
VDD
XI
XO
Voltage
Controlled
Crystal
Oscillator
PLL1
CLK1p
CLK1n
PLL2
VIN
CLK2
CLK3
PLL3
Full PD
CLK4
REFOUT
SDA
SCL
Control
Register
VREF
GND
AK8136A Multi Clock Generator
MS1108-E-04
Dec-2013
-1-
AK8136A
Pin Descriptions
Package: 20-Pin SSOP(Top View)
XI
1
20
XO
GND3
2
19
VDD3
VIN
3
18
REFOUT
GND4
4
17
VDDI
CLK2
5
16
SCL
VDD2
6
15
SDA
GND2
7
14
CLK1n
CLK3
8
13
CLK1p
CLK4
9
12
VDD1
VREF
10
11
GND1
Pin
No.
Pin
Name
Pin
Type
1
XI
AIN
2
GND3
PWR
Description
Crystal connection, Connect to 27.000MHz crystal
Ground 3
3
VIN
AIN
4
GND4
PWR
VCXO Control Voltage Input
5
CLK2
DO
6
VDD2
PWR
Power Supply 2
7
GND2
PWR
Ground 2
8
CLK3
DO
9
CLK4
DO
10
VREF
AO
11
GND1
PWR
Ground 1
12
VDD1
PWR
Power Supply 1
13
CLK1p
DO
Clock output 1, these are differential pair. See register description
14
CLK1n
DO
In full power down or disable, these pins are “L”.
15
SDA
DI/DO
16
SCL
DI
17
VDDI
PWR
18
REFOUT
DO
19
VDD3
PWR
20
XO
AO
Ground 4
Clock output 2, See register description.
In full power down or disable, this pin is “L”.
Clock output 3, See register description
In full power down or disable, this pin is “L”.
Clock output 4, Copy of CLK3 See register description
In full power down or disable, this pin is “L”.
VREF Pin Connect 1uF capacitor.
Hi-Z in full power down state.
Serial data input and output pin. Open drain.
Serial interface clock input.
Power supply for serial interface.
1.8V or 3.3V can be used.
Reference Clock Output of VCXO based on 27.000MHz Crystal
In full power down or disable, this pin is “L”.
Power Supply 3
Crystal connection, Connect to 27.000MHz crystal
Ordering Information
Part Number
Marking
Shipping
Packaging
Package
Temperature
Range
AK8136A
8136A
Tape and Reel
20-pin SSOP
-20 to 85℃
Dec-2013
MS1108-E-04
-2-
AK8136A
Absolute Maximum Rating
Over operating free-air temperature range unless otherwise noted
Items
Supply voltage
(1)
Symbol
Ratings
Unit
VDD/VDDI
-0.3 to 4.6
V
Vin
VSS-0.3 to VDD+0.3
V
IIN
±10
mA
Tstg
-55 to 130
C
Input voltage
Input current (any pins except supplies)
Storage temperature
Note
(1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions beyond those
indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating
conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
ESD Sensitive Device
This device is manufactured on a CMOS process, therefore, generically susceptible to
damage by excessive static voltage. Failure to observe proper handling and
installation procedures can cause damage. AKM recommends that this device is handled with
appropriate precautions.
Recommended Operation Conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
-20
85
C
(1)
VDDI
Pin: VDDI
1.7
3.6
V
(2)
Supply voltage 2
VDD
Pin: VDD1,VDD2,VDD3
3.0
3.6
V
Output Load Condition
CL1
Operating temperature
Supply voltage 1
Output Load Capacitance
Ta
3.3
Pin: CLK1p,CLK1n
See Figure 1
Cp1
Pin: CLK2,CLK3,CLK4
15
pF
Cp2
Pin: REFOUT
25
pF
Note:
(1) A decoupling capacitor for power supply line should be installed close to VDDI pin.
(2)Power to VDD1, VDD2, VDD3 requires to be supplied from a single source.
supply line should be installed close to each VDD pin.
MS1108-E-04
A decoupling capacitor for power
Dec-2013
-3-
AK8136A
DC Characteristics
VDD: over 3.0 to 3.6V,VDDI:over 1.7 to 3.6V, Ta: -20 to +85℃, 27MHz Crystal, unless otherwise noted
Parameter
Symbol
Conditions
High Level Input Voltage
VIH
Pin: SDA,SCL
Low Level Input Voltage
VIL
Pin: SDA,SCL
Input Current 1
IL 1
Pin: SDA,SCL
IL 2
Pin: VIN
Input Current 2
High Level Output
Voltage
VOH
Low level Output
Voltage
VOL
IOH=-4mA
Pin:VREF
Cvref=1μF
MAX
0.7VDDI
Unit
V
0.3VDDI
V
-10
+10
μA
-3
+3
μA
0.8VDD
V
IOL=+4mA
Ta=25℃,3.3V
VREF
TYP
Pin: CLK2-4, REFOUT
Pin:CLK1p,CLK1n
Output impedance
VREF Voltage
Pin: CLK2-4, REFOUT
MIN
0.2VDD
V
14
20
26
Ω
0.72
0.8
0.88
V
No load
Current Consumption 1
IDD1
Clock out selection by note(1)
VDD/VDDI=3.3V, Ta=25℃
32
mA
46
mA
On load(2)
Current Consumption 2
IDD2
Clock out selection by note(1)
VDD/VDDI=3.3V, Ta=25℃
Current Consumption 3
IDDPD
FULL_PD=”H”
VDD/VDDI=3.3V, Ta=25℃
0
150
μA
(1) CLK1p/1n:148.5MHz, CLK2=108MHz,CLK3/4=36.864MHz,REFOUT=27.0MHz
(2) CLK1p/1n: Figure1, CLK2-4: Cp1=15pF, REFOUT:Cp2=25pF
Dec-2013
MS1108-E-04
-4-
AK8136A
AC Characteristics (Clock signals)
VDD: over 3.0 to 3.6V, VDDI over 1.7 to 3.6V,Ta: over -20 to +85℃, 27MHz Crystal, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX
Unit
Crystal Clock Frequency
Fosc
Pin:XI,XO
27.0000
MHz
Output Clock Accuracy
Faccuracy
Pin:CLK2 100.71MHz
Relative to 27.0MHz
106.25
ppm
PRvcxo
VIN at over 0 to VDD V
±150
ppm
GVCXO
VIN range at 1.5V±1.0V
ppm/V
Jit_period
Pin:REFOUT ,CLK2-4
150
150
(6σ)
Jit_tie
Pin:CLK1
VCXO Pullable Range
(1)
VCXO Gain
Period Jitter
(5)
Time Interval Error
Long Term Jitter
(6)
(7)
Jit_long
Output Clock Duty
Cycle
DtyCyc
(2)
(3)
(4)
ps
100
Pin:REFOUT
1000 cycle delay
(4)
Pin: CLK1p,n Figure.3
(3)
CLK2-4
(2)
Pin: REFOUT
Output Clock Slew Rate
Slew_rise_fall
Pin:CLK1p,n
(4)
Slew rate matching
Slew_ver
Pin:CLK1p,n
(4)
Figure.2
Figure.3
ps
160
ps
45
50
55
%
40
50
60
%
8.0
V/ns
20
%
2.5
Differential output swing
V_swing
Pin:CLK1p,n
(4)
Figure.3
300
Crossing point voltage
V_cross
Pin:CLK1p,n
(4)
Figure.2
300
mV
550
mV
Variation of Vcrs
V_cross_delta
Pin:CLK1p,n
(4)
Figure.2
140
mV
Maximum output voltage
V_max
Pin:CLK1p,n
(4)
Figure.2
1.15
V
Pin:CLK1p,n
(4)
Figure.2
Minimum output voltage
V_min
Output Clock Rise Time
T_rise
Output Clock Fall Time
Output enable/disable Time
T_fall
(8)
T_en_dis
Power-up Time 1
(9)
T_put1
Power-up Time 2
(10)
T_put2
Pin: CLK2-4
Pin: REFOUT
Pin: CLK2-4
-0.3
(3)
(2 )
(3)
(2 )
Pin: REFOUT
Pin: REFOUT,CLK1p,n
CLK2-4
Pin: REFOUT,CLK1p,n
CLK2-4
Pin: REFOUT,CLK1p,n
CLK2-4
V
1.0
3.0
ns
2.5
5.0
ns
1.0
3.0
ns
2.5
5.0
ns
500
ns
4
ms
150
ms
(1) Pullable range depends on crystal characteristics, on-chip load capacitance, and stray capacity of PCB.
Typ. ±150ppm is applied to AKM’s authorized test condition.
Please contact us when you plan the use of other crystal unit.
(2) Measured with load capacitance of 25pF
(3) Measured with load capacitance of 15pF
(4) Measured with load condition shown in Figure.1
(5) ±3 in 10000 sampling or more
(6) 16ms accumulate with higher than 10GSa/s.
(7) ±3 in 10000 sampling or more
(8) Refer to Figure.7 on Clock enable and disable sequence.
(9) Time to settle output into 0.1% of specified frequency from FULL_PD is “L”.
Power Down sequence”.
Refer to Figure.6 on “Full
(10) Refer to Figure.5 on “Power on Reset sequence”.
MS1108-E-04
Dec-2013
-5-
AK8136A
3.3V
<5inch
T-Line
Z=50
30+/-5%
Rs
Measure point
PLL
2pF
Core
T-Line
Z=50
Vref
2pF
Figure.1 CLK1 Load condition
V_max=1.15V
CLK1p
V_cross_max=550mV
V_cross
V_cross_min=300mV
CLK1n
V_min=-0.3V
CLK1p
V_cross_delta_max=140mV
V_cross_delta
CLK1n
CLK1n
Slew_rise SE(Avg)
+75mV
Slew_fall SE(Avg)
+75mV
V_cross(Avg)
-75mV
-75mV
CLK1p
Figure.2 Single ended (SE) measurement waveforms
Dec-2013
MS1108-E-04
-6-
AK8136A
Period
-DtyCyc
0.0V
CLK1_diff
+DtyCyc
Slew_fall
Slew_rise
+150mV
0.0V
V_swing
0.0V
-150mV
CLK1_diff
Figure.3 Differential (DIFF) measurement waveforms
MS1108-E-04
Dec-2013
-7-
AK8136A
AC Characteristics (Serial interface）
VDD: over 3.0 to 3.6V, VDDI over 1.7 to 3.6V,Ta: over -20 to +85℃, 27MHz Crystal, unless otherwise noted
Parameter
Symbol
Conditions
MIN
MAX
Unit
400
kHz
SCL clock frequency
fSCL
SCL Clock Low Period
tLOW
1.3
μs
SCL Clock High Period
tHIGH
0.6
μs
Pulse width of spikes which must
be suppressed
tI
50
ns
tAA
0.3
μs
tBUF
1.3
μs
Start Condition Hold Time
tHD.STA
0.6
μs
Start Condition Setup Time
(for a Repeated Start condition)
tSU.STA
0.6
ms
Data in Hold Time
tHD.DAT
0
s
Data in Setup Time
tSU.DAT
100
ns
SLC Low to SDA Data Out
Bus free time between a STOP
and START condition
SDA and SCL Rise Time
tR
0.3
μs
SDA and SCL Fall Time
tF
0.3
μs
Stop Condition Setup Time
tSU.STO
Bus Line Load
μs
0.6
200
Cb
tF
pF
tR
SCL (IN)
tSU.STA
tLOW
tHIGH
tHD.DAT
tHD.STA
tSU.STO
tSU.DAT
SDA (IN)
tAA
tDH
tBUF
SDA (OUT)
Figure.4 Serial Interface Timing
Dec-2013
MS1108-E-04
-8-
AK8136A
Function Description
Power On Reset sequence
AK8136A has the POR(Power On Reset) circuit. In power up, the POR works and the register is set to the
initial value and all clock output becomes enable without glitch.
Note1) The assumption power start time to reach 90 % of VDD is within 20 ms.
Note2) The first register setting should be done after the 150 ms elapse after the power on.
VDD1/2/3
VDD*0.9
POR
(Internal signal)
SCL/SDA
Register setting available
CLK1p/CLK2-4/REFOUT
CLK1n
Max:20ms
Min:150ms
Figure.5 Recommend Power Up Sequence
MS1108-E-04
Dec-2013
-9-
AK8136A
Serial interface
Read/Write performance of serial interface is expressed below. The device address #1 of
AK8136A is fixed as ”1010”. The device address #2 is “110”.
Device address of AK8136A
1 0 1 0
Device Adress#1
1
R:1
W:0
1 0 R/W
Device Adress#2
Byte wtire operation
Byte write operation is described below. Data must be sent after sending 8 bits address and receiving
ACK.
Byte write
SDA
1 0 1 0 1 1 0 0
S
T
A
R
T
Device
Address
-1
Device R A
Address / C
W K
-2
Address
(MSB First)
A
C
K
Data
(MSB First)
A S
C T
K O
P
Page write operation
Page write operation is described below. Only lower 4 bits of address are valid. Upper 4 bits are fixed
as “1111”. Therefore the address which is written after “1111 1111” becomes “1111 1110”.
Page write
････
1 0 1 0 1 1 0 0
SDA
S
T
A
R
T
Device
Address
-1
Device R A
Address / C
W K
-2
Address
(MSB First)
A
C
K
Data
A
C
K
(Address)
Data
(Address+1)
A
C
K
A
C
K
Data
(Address+n)
A S
C T
K O
P
Current address read
Current address read operation is described below. The data that is read by this operation is obtained
as “last accessed address + 1”. Therefore, It is consequent to return “1111 1110” after accessing the
address “1111 1111”.
Current address read
SDA
1 0 1 0 1 1 01
S
T
A
R
T
Device
Address
-1
Device R A
Address / C
W K
-2
Data
(MSB First)
N
O
A
C
K
S
T
O
P
Dec-2013
MS1108-E-04
- 10 -
AK8136A
Random read
Random read operation is described below. It is necessary to operate “dummy write” before sending
read command. Dummy write is to send the address to read.
Random read
SDA
1 0 1 0 1 1 0 0
S
T
A
R
T
Device
Address
-1
Device R A
Address / C
W K
-2
1 0 1 0 1 1 0 1
Address
(MSB First)
A S
C T
K A
R
T
Device
Address
-1
Device R A
Address / C
W K
-2
Data
(MSB First)
N
O
A
C
K
S
T
O
P
Dummy Write
Sequential read
Sequential read operation is described below. It is possible to read next address sequentially by
sending ACK instead of stop condition.
Sequential read
SDA ････ 1 1 0 1
････
Device R A
Address / C
W K
-2
Data (MSB First)
(Address)
A
C
K
Data (MSB First)
(Address+1)
A
C
K
A
C
K
Data (MSB First)
(Address+n)
N
O
A
C
K
S
T
O
P
Change data
Change data operation is described below. It is available when SCL is Low.
Change data
SCL
SDA
DATA STABLE
DATA
CHANGE
Start / Stop timing
Start / Stop timing is described below. The sequence is started when SDA goes from high to low
during SCL is high. The sequence is stopped when SDA goes from low to high during SCL is high.
Start / Stop timing
SCL
SDA
START
STOP
MS1108-E-04
Dec-2013
- 11 -
AK8136A
Register description
The AK8136A generates a range of low-jitter and hi-accuracy clock frequencies with three built-in PLLs and
provides to up to five assigned outputs. A frequency selection at assigned output pin and power down
control is configured by register-setting.
Register Map
Address
D7
D6
D5
D4
D3
D2
D1
D0
FULL_PD
-
-
-
CLK3S[1]
CLK3S[0]
CLK2S
CLK1S
0
-
-
-
1
1
0
0
CLK4_DIS
CLK3_DIS
CLK2_DIS
CLK1_DIS
REF_DIS
0
0
0
0
0
Note
FF
Default
FE
Default
Register definition
FULL_PD
(Address FF:D7)
Power Down Control
0
Device Active (PLL ON)
Enable VCXO, VREF and PLLs
1
Full Power Down
Disable VCXO, VREF and PLLs
(default)
Full Power Down sequence
The full power down setting is done by following sequence.
1) Change CLKn_DIS(n=1,2,3,4) and REF_DIS to "1" .
2) Change FULL_PD to "1" from "0".
The output transfers to the disabled state without glitch.
The full power down state is released by following sequence.
1) Changing FULL_PD to "0" from "1" .
2) After more than 4 ms elapse, change CLKn_DIS and REF_DIS
The output transfers to the enable state without glitch.
"0" to "1".
CLKn_DIS,
REF_DIS
FULL_PD
CLK1p/CLK2-4/REFOUT
>4ms
CLK1n
Figure.6 Full Down sequence
Dec-2013
MS1108-E-04
- 12 -
AK8136A
CLK3S[1:0]
(Address FF:D3,D2)
CLK3&4 Output frequency selection
CLK2S
00
22.5792MHz
01
24.576MHz
10
33.8688MHz
11
36.864MHz
(default)
(Address FF:D1)
CLK2 Output frequency selection
CLK1S
0
108MHz.
1
100.71MHz
(default)
(Address FF:D0)
CLK1 Output frequency selection
0
148.5MHz/1.001
1
148.5MHz
(default)
CLK4_DIS (Address FE:D7)
CLK4 Output Disable
0
Enable (CLK4 Active)
1
Disable(CLK4=”L”)
(default)
CLK3_DIS (Address FE:D6)
CLK3 Output Disable
0
Enable (CLK3 Active)
1
Disable(CLK3=”L”)
(default)
CLK2_DIS (Address FE:D5)
CLK2 Output Disable
0
Enable (CLK2 Active)
1
Disable(CLK2=”L”)
(default)
CLK1_DIS (Address FE:D4)
CLK1 Output Disable
0
Enable (CLK1 Active)
1
Disable(CLK1p,CLK1n=”L” )
MS1108-E-04
(default)
Dec-2013
- 13 -
AK8136A
REF_DIS (Address FE:D3)
REFOUT Output Disable
0
Enable (REFOUT Active)
1
Disable(REFOUT=”L”)
(default)
Clock Enable and Disable sequence
The enabling and disabling of the clock output are executed without glitch within 500 ns from
the rising edge of SCL during the acknowledge operation after the corresponding byte date
reception.
SCL
SDA
Disable
ACK
< 500ns
CLKn
REFOUT
SCL
SDA
Enable
ACK
< 500ns
CLKn
REFOUT
Figure.7 Output Enable and Disable sequence
Dec-2013
MS1108-E-04
- 14 -
AK8136A
Voltage Controlled Crystal Oscillator (VCXO)
The AK8136A has a voltage controlled crystal oscillator (VCXO), featuring fine frequency tuning for 27MHz
of primary clock frequency by external DC voltage control. This tuning enables output clock frequency to
synchronize the external clock system. VIN (Pin3) accepts DC voltage control from a processor or a
system controller, and pulls the primary frequency of crystal to higher or lower. This pulling range is
determined by crystal characteristic, on-chip load capacitor, and stray capacitance of PCB. The AK8136A
is designed to range ±150ppm of primary frequency in AKM’s authorized condition, and the typical pulling
profile is shown in Figure 8. For details about the condition and other specific crystal application case,
refer the AK8136A application note.
27MHz VCXO Characteristics
KDS DSX530GA
200
150
100
50
0
0
0.5
1
1.5
2
2.5
3
3.5
-50
-100
-150
-200
Figure 8: Typical VCXO Pulling Profile
MS1108-E-04
Dec-2013
- 15 -
AK8136A
KDS DSX530GA
Item
MIN
TYP
MAX
27.000
Unit
Remark
MHz
CL=10.0pF
Nominal frequency
f0
Equivalent resistance
R1
Shunt capacitance
C0
3.0
pF
Motional capacitance
C1
11.4
fF
Motional inductance
L1
3.0
mH
50
Ω
Drive Level
10
300
uW
Spurious ・No spurious within 3fo±13kHz
・With in f0±500kHz the attenuation of the spurious response should be more
than 3dB.
L1
R1
C1
Crystal unit
C0
Load capacitance CL
CL
Figure.9 Equivalent parameter and load
capacitance
Dec-2013
MS1108-E-04
- 16 -
AK8136A
+0.10
-0.05
0.50±0.20
Package Information
+0.30
-0.10
0.15
6.5
11
4.40±0.20
6.40±0.30
20
1
10
0.10
M
0゜～10゜
0.22±0.10
0.65
0.45MAX
S
1.15±0.10
0.10
0.10±0.10
S
 Marking
20
11
b
8136A
XXXXX
AKM
c
d
a
a:
#1 Pin Index
b:
Part number
c:
Date code (5 digits)
d
Product Family Logo
(1)
10
1
 RoHS Compliance
All integrated circuits form Asahi Kasei Microdevices Corporation (AKM)
assembled in “lead-free” packages* are fully compliant with RoHS.
(*) RoHS compliant products from AKM are identified with “Pb free” letter indication on
product label posted on the anti-shield bag and boxes.
MS1108-E-04
Dec-2013
- 17 -
AK8136A
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application of
AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM
or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of AKM or any third party with respect to the
information in this document. You are fully responsible for use of such information contained in this
document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY
LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH
INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact, including
but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry,
medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic
signaling equipment, equipment used to control combustions or explosions, safety devices, elevators
and escalators, devices related to electric power, and equipment used in finance-related fields. Do not
use Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible
for complying with safety standards and for providing adequate designs and safeguards for your
hardware, software and systems which minimize risk and avoid situations in which a malfunction or
failure of the Product could cause loss of human life, bodily injury or damage to property, including
data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile
technology products (mass destruction weapons). When exporting the Products or related technology
or any information contained in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. The Products
and related technology may not be used for or incorporated into any products or systems whose
manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation, the
EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in
this document shall immediately void any warranty granted by AKM for the Product and shall not
create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
Dec-2013
MS1108-E-04
- 18 -