AVAGO AMMC-5033

AMMC-5033
17.7 - 32 GHz Power Amplifier
Data Sheet
Chip Size: 2730 x 1300 µm (108 x 51.6 mils)
Chip Size Tolerance: ± 10 µm (±0.4 mils)
Chip Thickness: 100 ± 10 µm (4 ± 0.4 mils)
Pad Dimensions: 80 x 80 µm (2.95 ± 0.4 mils)
Description
Features
Avago’s AMMC-5033 is a MMIC power amplifier designed
for use in wireless transmitters that operate within
17.7 GHz to 32 GHz range. At 25 GHz, it provides 27 dBm
of output power (P-1dB) and 20 dB of small- signal gain
from a small easy-to-use device. The device has input
and output matching circuitry for use in 50 Ω environments. The AMMC- 5033 also integrates a temperature
compensated RF power detection circuit that enables
power detection of 0.1 V/W at 22 GHz. For improved
reliability and moisture protection, the die is passivated
at the active areas.
• Wide frequency range: 17.7 – 32 GHz
• High power: P-1dB @ 25 GHz = 27 dBm
• High gain: 20 dB
• Return loss: Input: -13 dB, Output: –20 dB
• Integrated RF power detector
AMMC-5033 Absolute Maximum Ratings[1]
Symbol
Parameters/Conditions
Units
Vd1,2
Positive Drain Voltage
V
7
Vg1, Vgg
Gate Supply Voltage
V
0.5
Applications
• Designed for use in transmitters that operate in various
frequency bands between 17.7 GHz and 32 GHz.
• Can be driven by the AMMC-5040 (20-40 GHz) or the
AMMC-5618 (6-20 GHz) MMIC amplifiers, increasing
the power handling capability of transmitters requiring
linear operation.
Min. Max.
-3
Det Bias Applied Detector Bias
(Optional)
V
7
Id1
First Stage Drain Current
mA
320
Id2
Second Stage Drain Current mA
640
Pin
CW Input Power
dBm
23
Tch
Operating Channel Temp. °C
+150
Tstg
Storage Case Temp. °C
Tmax Maximum Assembly Temp. °C
(60 sec max)
-65 +150
+300
Note:
1. Operation in excess of any one of these conditions may result
in permanent damage to this device.
Note: These devices are ESD sensitive. The following precautions are strongly recommended:
Ensure that an ESD approved carrier is used when dice are transported from one destination to another.
Personal grounding is to be worn at all times when handling these devices.
AMMC-5033 DC Specifications/Physical Properties[1]
Symbol
Id1
Id2
Vgg
DETBias
θc1(ch-bs)
θc2(ch-bs)
Parameters and Test Conditions
First Stage Drain Supply Current
(Vd1 = 3.5 V, Vg1 = Open, Vgg set for Id2 Typical)
Second Stage Drain Supply Current
(Vd2 = 5 V, Vg1 = Open, Vgg set for Id2 Typical)
Gate Supply Operating Voltage
(Id1(Q) + Id2(Q) = 780 (mA))
Detector Bias Voltage (Optional)
First Stage Thermal Resistance[2]
(Backside Temperature, Tb = 25°C)
Second Stage Thermal Resistance[2, 3]
(Backside Temperature, Tb = 25°C)
Units
Min. mA
Typ. 280
V
500
V
-0.6
-0.75
V
°C/W
Vd2
31
°C/W
19
Max.
320
-0.4
Notes:
1. Backside temperature Tb = 25°C unless otherwise noted.
2. Channel-to-backside Thermal Resistance (θch-b) = 42°C/W at Tchannel (Tc) = 150°C as measured using infrared microscopy. Thermal Resistance at backside temperature (Tb) = 25°C calculated from measured data.
3. Channel-to-backside Thermal Resistance (θch-b) = 24°C/W at Tchannel (Tc) = 150°C as measured using infrared microscopy. Thermal Resistance at backside temperature (Tb) = 25°C calculated from measured data.
AMMC-5033 RF Specifications[4, 5]
Tb = 25°C, Vd1 = 3.5 V, Vd2 = 5 V, Id1(Q) = 280 mA, Id2(Q) = 500 mA, Zo = 50 Ω
Lower Band Mid Band Upper Band
Specifications Specifications Specifications
Parameters and (17.7 - 21 GHz) (21 - 26.5 GHz) (26.5 - 32 GHz)
Symbol
Test Condition
Unit
Min.
Typ.
Gain
Small-Signal Gain dB
20
P-1dB
Output Power at 1dB Gain
Compression[6]
dB
23.5
P-3dB
Output Power at 3dB Gain
Compression[6]
dB
OIP3
Output Third Order Intercept dBm
Point;[6]; ∆f = 2 MHz;
Pin = +2 dBm
RLin
Input Return Loss[5]
RLout
Output Return Loss [5]
[5]
Isolation Min. Reverse Isolation
Min.
Typ.
22
17.5
25
25.5
Max.
Min.
Typ.
20
16.5
18.5
27
25
26.5
27
28
27
27
29
29.5
32
29
32
dB
11.5
13.5
11
13
11
13
dB
14
20
14
19
15
22
dB
47
Notes:
4. Data measured in wafer form Tb = 25°C.
5. 100% on-wafer RF test is done at frequency = 17.7, 21, 26.5 and 32 GHz.
6. 100% on-wafer test frequency = 17.7, 26.5 and 32 GHz.
Max.
48
46
Max.
AMMC-5033 Typical Performances
(Tb = 25°C, Vd1 = 3.5 V, ID1 = 280 mA, Vd2 = 5 V, Id2 = 500 mA, Zin = Zout = 50 Ω)
40
0
25
-40
20
S12 (dB)
-20
30
15
-10
-15
-20
-60
10
-25
5
0
17
S22 (dB)
S11 (dB)
-5
RETURN LOSS (dB)
35
S21 (dB)
0
S21 (dB)
S12 (dB)
19
21
23
25
27
29
31
-80
33
-30
17
19
21
FREQUENCY (GHz)
30
10
28
8
26
24
P-1
P-3
22
19
21
23
25
27
29
31
33
38
36
IP3 (dBm)
34
32
30
28
26
21
23
25
27
29
FREQUENCY (GHz)
Figure 5. Output 3rd order intercept point
29
31
33
31
33
6
4
0
17
19
21
23
25
27
FREQUENCY (GHz)
Figure 3. Output power at 1 dB and 3 dB gain compression
19
27
2
FREQUENCY (GHz)
24
17
25
Figure 2. Return loss (input and output)
NOISE FIGURE (dB)
P-1 (dBm), P-3 (dBm)
Figure 1. Gain and reverse isolation
20
17
23
FREQUENCY (GHz)
31
33
Figure 4. Noise figure
29
AMMC-5033 Typical Performance Curves (Over Temperature and Voltage)
0.10
40
0.1
0.01
0.04
30
GAIN (dB)
0.06
(DET_R)-(DET_O) (V)
(DET_R)-(DET_O) (V)
0.08
10
0.02
0.00
0.001
0
5
10
15
20
25
20
0
17
30
5V/0.5A
4V/0.5
3.5V/0.5A
19
21
Figure 6. Linear and log detector voltage and output power,
freq. = 22 GHz, Det_B = 5 V
S11_85 C
S11_25 C
S11_-40 C
-5
S11 and S22 (dB)
P-1 (dBm)
27
29
31
33
0
28
26
24
5V/0.5A
4V/0.5
3.5V/0.5A
22
19
21
23
25
27
S22_85 C
S22_25 C
S22_-40 C
-10
-15
-20
-25
29
31
33
FREQUENCY (GHz)
Figure 8. Output power at 1 dB gain compression and Vd2 voltage, Vd1 = 3.5 V
(constant)
25
Figure 7. Gain and Vd2 voltage, Vd1 = 3.5 V (constant)
30
20
17
23
FREQUENCY (GHz)
RF Output Power (dBm)
-30
17
19
21
23
25
27
29
FREQUENCY (GHz)
Figure 9. Return-loss with temperature
31
33
30
25
Pout (dBm), PAE (%)
P-1 (dBm)
28
26
24
85 C
25 C
-40 C
22
20
17
19
21
23
25
27
29
31
33
FREQUENCY (GHz)
50
40
S21 (dB)
30
20
10
0
-10
85 C
25 C
-40 C
-20
19
21
23
25
27
FREQUENCY (GHz)
Figure 12. Gain with temperature
1000
20
800
15
600
10
400
5
200
0
-30
-20
-10
0
10
20
0
Pin (dBm)
Figure 10. Output power at 1 dB gain compression and temperature
-30
17
1200
Pout
PAE
Id
Id (mA)
30
29
31
33
Figure 11. Output power, PAE, and total drain. Current vs. input power at 25 GHz
Typical Scattering Parameters[1]
(Tb = 25°C, Vd1 = 3.5 V, ID1 = 280 mA, Vd2 = 5 V, ID2 = 500 mA, Zin = Zout = 50 Ω)
Freq
[GHz]
dB
1
-10.7
2
-11.0
3
-11.4
4
-12.1
5
-15.3
6
-12.2
7
-14.0
8
-15.3
9
-17.6
10
-19.4
11
-18.6
12
-19.7
13
-24.5
14
-27.4
15
-30.6
16
-24.1
17
-21.2
18
-18.0
19
-15.5
20
-14.0
21
-13.3
22
-13.0
23
-12.9
24
-12.9
25
-13.0
26
-13.3
27
-13.9
28
-14.9
29
-15.8
30
-17.0
31
-19.1
32
-21.0
33
-20.5
34
-17.0
35
-14.9
36
-12.8
37
-10.7
38
-9.8
39
-9.1
40
-8.5
41
-8.6
42
-8.6
43
-8.0
44
-7.6
45
-6.0
46
-4.4
47
-3.5
48
-2.7
49
-1.8
50
-1.7
S11
Mag
Phase
dB
0.29
173
-51.1
0.28
167
-70.1
0.27
161
-46.6
0.25
153
-37.3
0.17
140
-22.6
0.25
149
-20.4
0.2
143
-20.5
0.17
139
-25.4
0.13
138
-33.1
0.11
145
-18.9
0.12
152
-18.2
0.1
141
-29.0
0.06
134
-15.4
0.04
159
0.9
0.03
-148
12.7
0.06
-121
22.6
0.09
-116
28.8
0.13
-116
28.7
0.17
-123
26.4
0.2
-133
24.7
0.22
-142
23.4
0.22
-151
22.4
0.23
-157
21.5
0.23
-163
20.8
0.23
-172
20.3
0.22
-178
19.9
0.2
174
19.7
0.18
165
19.5
0.16
155
19.4
0.14
140
19.3
0.11
113
19.1
0.09
75
18.6
0.1
30
18.1
0.14
-9
17.2
0.18
-31
16.2
0.23
-45
14.6
0.29
-58
12.1
0.33
-71
7.7
0.35
-77
1.9
0.38
-85
-3.5
0.37
-92
-9.2
0.37
-92
-16.1
0.4
-92
-23.2
0.42
-90
-32.0
0.5
-87
-31.7
0.6
-93
-40.7
0.67
-98
-46.2
0.74
-102
-58.4
0.81
-111
-46.4
0.83
-118
-44.2
Note:
1. Data obtained from on-wafer measurements.
S21
Mag
Phase dB
0.003
-163
-95.1
0
79
-83.1
0.005
-103
-74.5
0.014
72
-74.5
0.074
-31
-80.3
0.096
144
-80.1
0.095
79
-80.3
0.053
-3
-74.1
0.022
108
-81.4
0.113
54
-81.4
0.123
-37
-81.3
0.035
-77
-74.6
0.169
103
-81.3
1.107
61
-81.2
4.316
-8
-74.6
13.52
-87
-76.2
27.62
174
-74.7
27.25
73
-64.8
20.92
3
-64.3
17.18
-53
-64.4
14.82
-103
-69.7
13.2
-151
-58.2
11.9
164
-63.3
10.97
121
-61.0
10.36
79
-66.1
9.895
37
-64.3
9.691
-6
-63.1
9.457
-49
-60.2
9.384
-94
-61.9
9.247
-141
-56.3
8.972
171
-57.7
8.519
121
-58.2
7.989
69
-56.0
7.281
14
-57.7
6.44
-43
-59.0
5.378
-104
-60.8
4.014
-171
-62.9
2.42
122
-57.1
1.238
65
-61.0
0.671
14
-60.9
0.347
-41
-67.6
0.157
-90
-59.2
0.069
-134
-61.0
0.025
-172
-62.0
0.026
-148
-64.6
0.009
-164
-61.1
0.005
62
-102.4
0.001
80
-60.1
0.005
50
-59.2
0.006
113
-61.9
S12
Mag
Phase
dB
1.77E-05
128
-0.5
6.97E-05
76
-0.7
1.89E-04
81
-1.2
1.88E-04
69
-2.2
9.66E-05
-47
-2.4
9.90E-05
-126
-2.8
9.68E-05
94
-4.0
1.97E-04
35
-4.2
8.52E-05
-62
-3.5
8.56E-05
-162
-3.8
8.59E-05
151
-4.4
1.86E-04
178
-5.2
8.65E-05
-180
-6.3
8.70E-05
-20
-7.9
1.86E-04
152
-10.1
1.55E-04
144
-13.3
1.84E-04
-164
-20.5
5.75E-04
165
-20.0
6.08E-04
123
-19.4
6.03E-04
90
-19.1
3.27E-04
76
-18.7
1.23E-03
80
-18.5
6.80E-04
92
-19.0
8.96E-04
44
-20.7
4.97E-04
55
-21.8
6.09E-04
53
-22.9
7.00E-04
58
-22.9
9.75E-04
68
-22.6
8.00E-04
38
-22.1
1.53E-03
25
-22.4
1.31E-03
15
-24.9
1.23E-03
1
-31.9
1.59E-03
-15
-31.4
1.31E-03
-12
-24.4
1.12E-03
-36
-20.0
9.14E-04
-40
-16.2
7.13E-04
-31
-13.1
1.40E-03
-55
-11.1
8.94E-04
-61
-10.1
9.04E-04
-59
-9.8
4.15E-04
-65
-9.7
1.09E-03
-82
-10.1
8.95E-04
-75
-10.6
7.96E-04
-59
-11.4
5.91E-04
-123
-12.3
8.84E-04
-82
-13.2
7.57E-06
-171
-14.2
9.93E-04
176
-14.8
1.10E-03
-69
-14.7
8.00E-04
26
-14.9
S22
Mag
0.95
0.92
0.87
0.78
0.76
0.73
0.63
0.62
0.67
0.64
0.6
0.55
0.48
0.41
0.31
0.22
0.09
0.1
0.11
0.11
0.12
0.12
0.11
0.09
0.08
0.07
0.07
0.07
0.08
0.08
0.06
0.03
0.03
0.06
0.1
0.16
0.22
0.28
0.31
0.33
0.33
0.31
0.29
0.27
0.24
0.22
0.2
0.18
0.18
0.18
Phase
-26
-51
-76
-95
-112
-130
-146
-150
-166
177
161
146
131
115
100
86
76
133
130
135
133
129
124
119
122
131
135
142
136
125
117
126
-148
-141
-145
-152
-167
174
154
134
116
98
80
62
41
21
0
-27
-49
-77
Biasing and Operation
Assembly Techniques
The recommended quiescent DC bias condition for
optimum efficiency, performance, and reliability is
Vd1 = 3.5 volts and Vd2 = 5 volts with Vgg set for
Id1 + Id2 = 780 mA (no connection to Vg1). This bias arrangement results in default quiescent drain currents
Id1 = 280 mA, Id2 = 500 mA. A single DC gate supply
connected to Vgg will bias all gain stages.
The backside of the AMMC- 5033 chip is RF ground. For
microstripline applications, the chip should be attached
directly to the ground plane (e.g., circuit carrier or heatsink) using electrically conductive epoxy.[1]
If operation with both Vd1 and Vd2 at 5 volts is desired,
an additional wire bond connection from the Vg1 pad
to Vgg external bypass chip capacitor (shorting Vg1 to
Vgg) will balance the current in each gain stage. Vgg (=
Vg1) can be adjusted for Id1 + Id2 = 780 mA. Muting can
be accomplished by setting Vg1 and/or Vgg to the pinchoff voltage Vp.
An optional output power detector network is also
provided. Detector sensitivity can be adjusted by biasing the diodes with typically 1 to 5 volts applied to the
Det- bias terminal. Simply connecting Det-Bias to the Vd2
supply is a convenient method of biasing this detector
network. The differential voltage between the Det-Ref
and Det-Out pads can be correlated with the RF power
emerging from the RF output port. The detected voltage is given by:
V = (Vref - Vdet) - Vofs
Where Vref is the voltage at the DET_REF port, Vdet is
a voltage at the DET_OUT port, and Vofs is the zero-input-power offset voltage. There are three methods to
calculate Vofs:
1. Vofs can be measured before each detector measurement (by removing or switching off the power source
and measuring Vref - Vdet ). This method gives an error
due to temperature drift of less than 0.0002 dB/°C.
2. Vofs can be measured at a single reference temperature.
The drift error will be less than 0.25 dB.
3. Vofs can either be characterized over temperature and
stored in a lookup table, or it can be measured at
two temperatures and a linear fit used to calculate
Vofs at any temperature. This method gives an error
close to method #1.
With reference to Figure 13, the RF input is DC coupled
to a shunt 50 Ω resistor but it is DC blocked to the input
of the first stage. The RF output is DC blocked to the
output of the second stage, however, it is DC coupled
to the detector bias circuit. If the output detector is
biased using the on-chip optional Det-Bias network,
an external DC blocking capacitor may be required at
the RF Output port.
No ground wires are needed since ground connections
are made with plated through-holes to the backside of
the device.
For best performance, the topside of the MMIC should
be brought up to the same height as the circuit surrounding it. This can be accomplished by mounting a
gold plated metal shim (same length and width as the
MMIC) under the chip, which is of the correct thickness
to make the chip and adjacent circuit coplanar.
The amount of epoxy used for chip and or shim attachment should be just enough to provide a thin fillet
around the bottom perimeter of the chip or shim. The
ground plane should be free of any residue that may
jeopardize electrical or mechanical attachment.
The location of the RF bond pads is shown in Figure
14. Note that all the RF input and output ports are in
a Ground-Signal-Ground configuration.
RF connections should be kept as short as reasonable to
minimize performance degradation due to undesirable
series inductance. A single bond wire is sufficient for
signal connections, however double-bonding with 0.7
mil gold wire or the use of gold mesh[2] is recommended
for best performance, especially near the high end of
the frequency range.
Thermosonic wedge bonding is the preferred method
for wire attachment to the bond pads. Gold mesh can
be attached using a 2 mil round tracking tool and a
tool force of approximately 22 grams with an ultrasonic
power of roughly 55 dB for a duration of 76 ± 8 mS. A
guided wedge at an ultrasonic power level of 64 dB can
be used for the 0.7 mil wire. The recommended wire
bond stage temperature is 150 ± 2°C.
Caution should be taken to not exceed the Absolute
Maximum Rating for assembly temperature and time.
The chip is 100 µm thick and should be handled
with care. This MMIC has exposed air bridges on the
top surface and should be handled by the edges or
with a custom collet (do not pick up die with vacuum
on die center.)
This MMIC is also static sensitive and ESD handling
precautions should be taken.
Notes:
1. Ablebond 84-1 LM1 silver epoxy is recommended.
2. Buckbee-Mears Corporation, St. Paul, MN, 800-262-3824
GND
Vgg g
Vd1
DQ
Vd2
DQ
GND
DET. _ OUT
D1
50
50
RF _ Input
RF _ OUT
DET . _ BIAS
Ref_ D2
50
DET . _ REF
250
50
1000
GND
Vg1
Vgg
Figure 13. AMMC-5033 schematic
Figure 14. AMMC-5033 bonding pad locations, dimensions are in microns
Vd2
DQ
GND
VD2, 500 mA
VD1, 280 mA
68 pF
RFOutput
VD2
VD1
RFInput
RFI
RFO
AMMC-5033
VD2
Notes:
1. 1µF capacitors on gate and drain lines not shown required.
VGG
68 pF
VEE
Figure 15. AMMC-5033 assembly diagram
Ordering Information:
AMMC-5033-W10 = 10 devices per tray
AMMC-5033-W50 = 50 devices per tray
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-3935EN
AV02-0682EN - September 5, 2007