The Analog Mixed Signal Company Amplifier ID: 010 AMP-05 Name Description This op-amp is designed for on chip signal processing, especially as a low-noise input amplifier. It uses pole splitting for compensation. Stable operation at unity gain frequency is not feasible due to the three stage amplifier architecture. The results are simulated with extracted parasitics. To adapt this op-amp to other demands, scale the output stage and the Miller-caps or change the bias currents. Conditions Temperature Reference Current (Iref) VDD 27°C 10 µA 2.5 V VSS -2.5 V Load 10 kOhms || 10 pF Simulated Data Parameter Supply Voltage Reference Current Symbol VDD Unit V Iref µA Supply Current IDD µA Input Offset Voltage VIO mV Min Typ 5 Max 10 525 Voltage Gain Transit Frequency Phasemargin TK(VIO) µV/K v fT Îm dB MHz deg 9.84 122.1 4.2 -65 0.01% Settling Time ns Slew Rate S V/µs Maximum Large Signal Frequency Output Swing VOUT kHz V -1.13 VCM ppm V -2 dB dB 1 204.8 184.2 Static Nonlinearity Commonmode Range Common Mode Rejection Ratio Power Supply Rejection Ratio CMRR PSRR Unity Gain Unity Gain, No Parasitics, delta L=0.1µm Unity Gain, No Parasitics, delta L=0.1µm 0.91 TK VIO Condition 1.39 5 No stable operation at unity gain possible. No stable operation at unity gain possible. No stable operation at unity gain possible. < 5 ppm VDD = +5 V, Unity Gain CMRR > 70 dB @ 10 Hz CMRR > 223.2 dB @ 10 Hz f CM= 10 kHz, VCM = 0V f PS= 1 Hz