www.fairchildsemi.com AN-6861 Applying FAN6861 to a Flyback Power Supply with Peak Load Current Profile The frequency-hopping function reduces electro-magnetic interference (EMI) of a power supply by spreading the energy over a wider frequency range. The constant power limit function minimizes the component stress in abnormal condition and helps to optimize the power stage. Protection functions; such as OCP, OLP, OVP, and OTP are fully integrated into FAN6861, which improves the SMPS reliability without increasing system cost. 1. Introduction Highly integrated PWM controller, FAN6861, is optimized for applications with motor load, such as printers and scanners, that inherently impose some kind of overload condition on the power supply during acceleration mode. The two-level OCP function allows the SMPS to stably deliver peak power during the motor acceleration without causing premature shutdown, while protecting the SMPS from overload condition. This application note presents design considerations to apply FAN6861 to a flyback power supply with peak load current profile. It covers designing the transformer, selecting the components, and closing the feedback loop. Figure 1 shows a typical application circuit using FAN6861. The green-mode and burst-mode functions with a low operating current (2.2mA maximum in green mode) maximize the light-load efficiency so that the power supply can meet stringent standby power regulations. L RSN2 CSN2 EMI AC input RSN1 Filter + CIN N D OUT VIN + 5 DSN VO - COUT 2 + CDD 2 GATE 6 2 FB SENSE 4 RCSF GND C FB DDD 2 RG VDD 3 RT CDD 1 VO + + COUT 1 R DAMP DDD1 RSTART CSN1 1 FAN6861 CCSF RCS RBIAS R1 RDB CF R2 KA431 Figure 1. Typical Application © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 6/9/09 www.fairchildsemi.com AN-6861 APPLICATION NOTE (Design Example) The specifications of the target system are: • VLINEMIN =90VRMS VLINEMAX)=264VRMS • Line frequency (fL) = 60Hz • Nominal output power (PNO) = 20W (32V/0.625A) • Peak output power (PPO) = 50W (32V/1.56A) • Peak load duration (tPO) < 500ms • Estimated efficiency: ηN = 0.87 and ηP = 0.82 P 50 PINP = PO = = 61W η P 0.82 P 20 PINN = NO = = 23W η N 0.87 FAN6861 can be used for this application because the peak load duration is less than the OCP delay time of 780ms. 2. Design Considerations Flyback converters have two operation modes; continuous conduction mode (CCM) and discontinuous conduction mode (DCM). CCM and DCM have their own advantages and disadvantages, respectively. In general, DCM provides better switching conditions for the rectifier diodes, since the diodes are operating at zero current just before becoming reverse biased and the reverse recovery loss is minimized. The transformer size can be reduced using DCM because the average energy storage is low compared to CCM. However, DCM inherently causes high RMS current, which increases the conduction loss of the MOSFET severely for low line condition. Thus, especially for applications with peak load profile, such as printer and scanner; it is typical to design the converter such that the converter operates in CCM for low line and peak load condition to maximize efficiency. In this section, a design procedure is presented using the schematic of Figure 1 as a reference. An off line SMPS with 20W/32V nominal output power and 50W/32V peak output power has been selected as a design example. [STEP-2] Determine the Input Capacitor (CIN) and the Input Voltage Range It is typical to select the input capacitor as 1.5~2μF per watt of peak input power for universal input range (85-265VRMS) and 0.7~0.8μF per watt of peak input power for European input range (195V-265VRMS). With the input capacitor chosen, the minimum input capacitor voltage at peak load condition is obtained as: [STEP-1] Define the System Specifications Designing a power supply with peak load current profile, the following specifications should be determined first: Line voltage range (VLINEMIN and VLINEMAX) VINP MIN = 2 ⋅ (VLINE MIN ) 2 − Line frequency (fL). PINP ⋅ (1 − DCH ) C IN ⋅ f L (3) The minimum input capacitor voltage at nominal load condition is obtained as: Nominal output power (PNO) Peak output power (PPO) and its duration (tPO) VINN MIN = 2 ⋅ (VLINE MIN ) 2 − Estimated efficiencies for nominal load (ηN) and peak load (ηP): The power conversion efficiency must be estimated to calculate the input powers for each condition. Typically, the efficiency at peak load condition is lower than that of nominal load since most of the components of power supply are selected for nominal load condition. If no reference data is available, set ηN = 0.7~0.75 and ηP = 0.65~0.7 for low-voltage output applications and ηN = 0.8~0.85 and ηP = 0.75~0.8 for high-voltage output applications. PINN ⋅ (1 − DCH ) C IN ⋅ f L (4) where DCH is the input capacitor charging duty ratio defined as shown in Figure 2, which is typically about 0.2. The maximum input capacitor voltage is given as VIN MAX = 2VLINE MAX (5) With the estimated efficiency, the input power for peak load condition is given by: PINP = PPO (1) ηP The input power for nominal load condition is given by: PINN = PNO ηN © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 6/9/09 (2) Figure 2. Input Capacitor Voltage Waveform www.fairchildsemi.com 2 AN-6861 APPLICATION NOTE As can be seen in Equation (7), the voltage stress across the MOSFET can be reduced by reducing VRO. However, this increases the voltage stresses on the rectifier diodes in the secondary side. Therefore, VRO should be determined by a trade-off between the voltage stresses of MOSFET and diode. Because the actual drain voltage rises above the nominal MOSFET voltage due to the leakage inductance of the transformer, as shown in Figure 3, it is typical to set VRO around 70~100V so that VDSNOM is 430~450V for 600V MOSFET (73~78% of MOSFET voltage rating). (Design Example) By choosing a 100μF capacitor for the input capacitor, the minimum input voltages for peak and nominal load are obtained, respectively, as: VINP MIN = 2 ⋅ (VLINE MIN ) 2 − = 2 ⋅ (90) 2 − 61 ⋅ (1 − 0.2) = 90V 100 × 10 −6 ⋅ 60 VINN MIN = 2 ⋅ (VLINE MIN ) 2 − = 2 ⋅ (90) 2 − PINP ⋅ (1 − DCH ) C IN ⋅ f L PINN ⋅ (1 − DCH ) C IN ⋅ f L (Design Example) By determining VRO as 100V: 23 ⋅ (1 − 0.2) = 115V 100 × 10 −6 ⋅ 60 DMAX = The maximum input voltage is obtained as VRO VRO 100 = = 0.53 MIN 100 + 90 + VINP VDS NOM = VIN MAX + VRO = 273 + 100 = 473V VIN MAX = 2 ⋅ VLINE MAX = 2 ⋅ 264 = 373V [STEP-3] Determine the Reflected Output Voltage (VRO) [STEP-4] Determine Inductance (LM) When the MOSFET is turned off, the input voltage (VIN), together with the output voltage reflected to the primary, (VRO) are imposed across the MOSFET, as shown in Figure 3. With a given VRO, the maximum duty cycle (DMAX) and the maximum nominal MOSFET voltage (VDSNOM) are obtained as: DMAX = VRO VRO + VINP MIN VDS NOM = VIN MAX + VRO the Transformer Primary-Side The transformer primary-side inductance is determined for the minimum input voltage and peak load condition. With the DMAX from Step-3, the primary-side inductance (LM) of the transformer is obtained as (6) LM = (7) (VINP MIN ⋅ DMAX ) 2 2 P INP f SW K RF (8) where fSW is the switching frequency and KRF is the ripple factor at peak load and minimum input voltage condition, as shown in Figure 4. The ripple factor is closely related to the transformer size and the RMS value of the MOSFET current. Even though the conduction loss in the MOSFET can be reduced by reducing the ripple factor, too small a ripple factor forces an increase in transformer size. From practical point of view, it is reasonable to set KRF = 0.3~0.6 for the universal input range and KRF = 0.4~0.8 for the European input range. Once LM is calculated by determining KRF from Equation (8), the peak current and RMS current of the MOSFET for minimum input voltage and peak load condition are obtained as: I DS PK = I EDC + ΔI 2 (9) ΔI ⎤ D ⎡ I DS RMS = ⎢3( I EDC ) 2 + ( ) 2 ⎥ MAX 2 ⎦ 3 ⎣ PINP where: I EDC = MIN VINP ⋅ DMAX Figure 3. The Output Voltage Reflected to the Primary © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 6/9/09 and ΔI = VINP MIN DMAX LM f SW (10) (11) (12) www.fairchildsemi.com 3 AN-6861 APPLICATION NOTE K RF The peak drain current at minimum input voltage and peak load condition was obtained from Equation (9) in Step-4. The peak drain current at minimum input voltage and nominal load condition is given as: ΔI = 2 I EDC ΔI PINN ⋅ (VIN MIN + VRO ) VINN MIN ⋅ VRO I DS . N PK = I DS PK LM = 2 = 503μ H I EDC = ΔI = I DS 2 PINN LM f SW ⋅ PINP 61 = = 1.28 A VINP MIN ⋅ DMAX 90 ⋅ 0.53 RMS (14) : DCM (VINN MIN + VRO ) > 1 : CCM VINN MIN ⋅ VRO (15) (V MIN + V ) ⋅ INN MIN RO < 1 : DCM VINN ⋅ VRO 2 PINN LM f SW VINP MIN DMAX 90 ⋅ 0.53 = = 1.46 A LM f SW 503 × 10 −6 ⋅ 65 × 103 I DS PK = I EDC + : CCM Whether the converter operates in CCM or DCM at minimum input voltage and nominal load condition is determined by: (VINP ⋅ DMAX ) (90 ⋅ 0.53) = 2 P INP f SW K RF 2 ⋅ 61 ⋅ 65 × 103 ⋅ 0.57 2 2 ⋅ PINN f SW ⋅ LM I DS . N PK = (Design Example) Determining the ripple factor as 0.57 MIN VINN ⋅ VRO 2 LM f SW ⋅ (VINN MIN + VRO ) + Figure 4. MOSFET Current and Ripple Factor (KRF) (13) MIN The condition for the sensing resistor is given as: ΔI = 1.28 + 0.73 = 2.01A 2 RCS < ΔI ⎤ D ⎡ = ⎢3( I EDC ) 2 + ( ) 2 ⎥ MAX 2 ⎦ 3 ⎣ RCS 0.53 = ⎣⎡3(1.28) 2 + (0.73) 2 ⎦⎤ = 0.98 A 3 0.5 I DS . N PK (16) 0.89 < I DS PK (Design Example) For minimum input voltage and nominal load condition, the operation mode is DCM as: [STEP-5] Determine the Sensing Resistor Value The current sensing resistor value should be determined considering the over-current protection threshold and the pulse-by-pulse current limit threshold, as shown in Figure 5. The peak value of current sensing voltage (VCS) should be lower than the pulse-by-pulse current limit level for peak load condition. It should be lower than the OCP threshold for nominal load conditions to prevent false triggering of OCP protection during normal operation. 2 PINN LM f SW ⋅ (VINN MIN + VRO ) VINN MIN ⋅ VRO = 2 ⋅ 23 ⋅ 503 × 10 −6 ⋅ 65 × 103 ⋅ (115 + 100) <1 115 ⋅100 The peak drain current at minimum input voltage and nominal power condition is given as: 2 ⋅ PINN = f SW ⋅ LM I DS.N PK = 2 ⋅ 23 = 1.19 A 65 × 10 ⋅ 503 × 10 −6 3 The conditions for the sensing resistor are given as: RCS < RCS < VCS = I DS ⋅ RCS Figure 5. Determining Current Sensing Resistor © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 6/9/09 0.5 I DS . N PK 0.89 I DS . P 2 PK = 0.5 = 0.42Ω 1.19 = 0.89 = 0.44Ω 2.01 Thus, a 0.39Ω resistor is selected for the current-sensing resistor www.fairchildsemi.com 4 AN-6861 APPLICATION NOTE [STEP-7] Determine the Number of Turns for Each Winding [STEP-6] Determine the Minimum Primary Turns With a given core, the minimum number of turns for the transformer primary side to avoid the core saturation is given by: N P min = L ⋅ 0.89 / RCS LM I LIM × 106 = M × 10 6 BSAT Ae BSAT Ae Figure 7 shows a simplified diagram of the transformer. First, calculate the turn ratio (n) between the primary side and the secondary side from the reflected output voltage determined in Step-3, as: (17) n= where Ae is the cross-sectional area of the core in mm2, ILIM is the pulse-by-pulse current limit level determined by 0.89V threshold, RCS is current sensing resistor, and BSAT is the saturation flux density in Tesla. VRO NP = N S VO + VF (18) where NP and NS are the number of turns for primary side and secondary side, respectively, VO is the output voltage; and VF is the diode (DO) forward-voltage drop. Then, determine the proper integer for NS such that the resulting NP is larger than NPmin obtained from Equation (17). The pulse-by-pulse current limit level is included in Equation (17) because the inductor current reaches the pulse-by-pulse current limit level during the load transient or overload condition. Figure 6 shows the typical characteristics of ferrite core from TDK (PC40). Since the saturation flux density (BSAT) decreases as the temperature goes high, the high temperature characteristics should be considered. If there is no reference data, use BMAX =0.3T. The number of turns for the auxiliary winding for VDD supply is determined as: NA = VDD * + VF ⋅ N S1 VO + VFA (19) where VDD is the nominal value of the supply voltage and VFA is the forward voltage drop of DDD as defined in Figure 7. Since VDD increases as the output load increases, it is proper to set VDD at 3~5V higher than VDD UVLO level (9.5V) to avoid the over-voltage protection condition during the peak load operation. Figure 6. Typical B-H Characteristics of Ferrite Core (TDK/PC40) Figure 7. Simplified Transformer Diagram (Design Example) Assuming the diode forwardvoltage drop is 1V, the turn ratio is obtained as: VRO N 100 n= P = = = 3.03 N S VO + VF 32 + 1 Then, determine the proper integer for NS such that the resulting NP is larger than NPmin as: N S = 20, N P = n ⋅ N S = 61 > N P min Setting VDD* as 12.5V, the number of turns for the auxiliary winding is obtained as: V * + VF 12.5 + 1 ⋅ NS = ⋅ 20 = 8 N A = DD 32 + 1 VO + VFA (Design Example) A EF25/13/11 core is selected, whose effective cross-sectional area is 78mm2. Choosing the saturation flux density as 0.25T, the minimum number of turns for the primary side is obtained as: L ⋅ 0.89 / RCS N P min = M × 106 BSAT Ae = 503 × 10 −6 ⋅ 0.89 / 0.39 × 106 = 59 0.25 ⋅ 78 © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 6/9/09 www.fairchildsemi.com 5 AN-6861 APPLICATION NOTE [STEP-8] Determine the Wire Diameter for Each Winding Based on the RMS Current of Winding. (Design Example) The diode voltage and current are calculated as: V MAX 373 VDO = VO + IN = 32 + = 154V 3.05 n 1 − DMAX I DO RMS = n ⋅ I DS RMS DMAX The maximum RMS current of the secondary winding is obtained as: I SEC RMS = n ⋅ I DS RMS 1 − DMAX DMAX (20) The current density is typically 6~10A/mm2 when the wire is long (>1m). When the wire is short with a small number of turns, a current density of 8~14A/mm2 is also acceptable. These current densities are based on the peak load condition and therefore almost twice of conventional power supply design. Avoid using wire with a diameter larger than 1mm to avoid severe eddy current losses and to make winding easier. For high current output, use parallel windings with multiple strands of thinner wire to minimize skin effect. 1 − 0.53 = 2.8 A 0.53 10A and 200V diode is selected assuming very small heat-sink is used for the diode = 3.05 ⋅ 0.98 [STEP-10] Feedback Circuit Configuration The FAN6861 employs peak-current-mode control as shown in Figure 8 . A current-to-voltage conversion is accomplished externally with current-sense resistor RCS. Under normal operation, the FB level controls the peak inductor current as: (Design Example) The RMS current of the primary- side winding is obtained from Step-4 as 1.01A. The RMS current of the secondary-side winding is calculated as: I SEC RMS = n ⋅ I DS RMS I DS ⋅ RCS + VSLOPE = I DS ⋅ RCS + 0.35 ⋅ D = 1 − DMAX DMAX VFB - 1.2 4 (25) where VFB is the voltage of FB pin, VSLOPE is synchronized positive-going ramp, and D is duty cycle ratio. 1 − 0.53 = 3.05 ⋅ 0.98 = 2.8 A 0.53 0.4mm (8A/mm2) and 0.55mm (12A/mm2) diameter wires are selected for primary and secondary windings, respectively. [STEP-9] Choose the Rectifier Diode in the SecondarySide Based on the Voltage and Current Ratings. The maximum reverse voltage and the RMS current of the rectifier diode are obtained as: VDO = VO + VIN MAX n I DO RMS = n ⋅ I DS RMS (21) 1 − DMAX DMAX (22) Figure 8. Peak Current Mode Circuit Figure 9 is a typical feedback circuit mainly consisting of a shunt regulator and a photo-coupler. R1 and R2 form a voltage divider for output voltage regulation. RF and CF are adjusted for control-loop compensation. A small-value RC filter (e.g. RFB= 100Ω, CFB= 1nF) placed from the FB pin to GND can increase stability substantially. The maximum source current of the FB pin is about 325μA. The phototransistor must be capable of sinking this current to pull the FB level down at no load. The value of the biasing resistor, RBIAS, is determined as: The typical voltage and current margins for the rectifier diode are as: (23) VRRM > 1.3 ⋅ VDO I F > 1.5 ⋅ I DO RMS (24) where VRRM is the maximum reverse voltage and IF is the current rating of the diode. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 6/9/09 www.fairchildsemi.com 6 AN-6861 APPLICATION NOTE VO − VOPD − VKA ⋅ CTR > 325 × 10 −6 RBIAS [STEP-11] Design the Startup Circuit (26) Figure 10 shows the typical startup circuit for FAN6861. Connecting startup resistor to AC line allows the reset of latch protection by unplugging the AC line from the power supply. Two-stage hold-up capacitor configuration (CDD1 and CDD2) is typically used to increase the hold-up time while minimizing the startup time. where VOPD is the drop voltage of photodiode, about 1.2V: VKA is the minimum cathode to anode voltage of shunt regulator (2.5V); and CTR is the current transfer rate of the opto-coupler. Initially, FAN6861 consumes only startup current (maximum 15μA) before it begins normal switching operation. Therefore, the current supplied through the startup resistor (RSTART) can charge capacitor CDD1 while supplying the startup current to FAN6861. When VDD reaches turn-on voltage of 17.5V (VDD-ON), FAN6861 begins switching operation and the current consumed by FAN6861 increases to normal operating current (typical 3mA). Then, the current required by FAN6861 is supplied from the auxiliary winding of transformer. The average current supplied through the startup resistor for minimum line voltage condition is 2VLINE MIN VDD −ON 1 (28) I RST = ( ) − > I DD − ST π 2 RSTART Figure 9. Feedback Circuit TSTART MAX = C DD1 The feedback compensation network transfer function of Figure 9 is obtained as: vˆFB ω 1 + s / ω ZC =− I ⋅ vˆo s 1 + s / ω PC RB where ω I = R1 RDB C F 1 : ω pc = RB C FB ω ZC = 1 ( RF + R1 )CO (29) The maximum power dissipation of RSTART is: PRST ≅ (27) , I RST VDD −ON − I DD − ST MAX (VLINE MAX ) 2 2 RSTART (30) , RB is the internal feedback bias resistor of FAN6861; and R1, RD, RF, CF, and CFB are shown in Figure 9. (Design Example) Assuming CTR is 100%; VO − VOPD − VKA ⋅ CTR > 325 × 10 −6 RBIAS RBIAS < VO − VOPD − VKA 32 − 1.2 − 2.5 = = 87 k Ω 325 × 10 −6 325 × 10 −6 3kΩ resistor is selected for RDB. The voltage divider resistors for VO sensing are selected as 120kΩ and 10kΩ. Figure 10. Startup Circuit © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 6/9/09 www.fairchildsemi.com 7 AN-6861 APPLICATION NOTE (Design Example) 510kΩ resistor and 10μF capacitor Thermal Protection are selected for RSTART and CDD1, respectively. Then, the current through the startup resistor for minimum line voltage is: 2VLINE MIN VDD −ON 1 − I RST = ( ) π 2 RSTART =( Figure 12 shows the internal blocks for thermal protection. A constant current, IRT, of 99μA is provided from the RT pin. For over-temperature protection, an NTC thermistor in series with a resistor can be connected between the RT and GND pins. As temperature increases, the impedance of NTC thermister decreases and RT pin voltage drops. When the voltage of the RT pin is less than 1V longer than 17ms (tDOTP-LATCH), OTP is triggered. When RT pin voltage is less than 0.7V, OTP is triggered after the 100μs debounce time. 2 ⋅ 90 17.5 1 − = 62 μ A ) π 2 510 × 103 Then, the maximum startup time is obtained as TSTART MAX = CDD1 I RST = 10 × 10 −6 If the thermal protection is not used, connect a small capacitor (around 0.47nF is recommended) from the RT pin to the GND pin to prevent noise interference. This RT capacitor should not be larger than 1nF; otherwise, the thermal protection is triggered before a successful build-up of output voltage. VDD −ON − I DD − ST MAX 17.5 = 3.7 sec (62 − 15) × 10 −6 The maximum power dissipation of RSTART is: PRST ≅ (VLINE MAX ) 2 2652 = = 68mW 2 RSTART 2 ⋅ 510 × 103 Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs across the sense resistor, caused by primaryside capacitance and secondary-side rectifier reverse recovery. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period (360ns), the PWM comparator is disabled and cannot switch off the gate driver. Thus, an RC filter with a small RC time constant is enough for current sensing (e.g. 200Ω + 470pF). A non-inductive resistor is recommended for RCS. Figure 12. Thermal Protection Circuit Figure 11. Current sensing © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 6/9/09 www.fairchildsemi.com 8 AN-6861 APPLICATION NOTE Printed Circuit Board (PCB) Layout Two suggestions with different pro and cons for ground connections are offered: PCB layout is a very important design issue for highfrequency switching current/voltage application. Good PCB layout minimizes excessive EMI and helps the power supply survive during surge/ESD tests. Guidelines: To get better EMI performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitor C1 first, then to the switching circuits. The high-frequency current loop is in C1 – transformer – MOSFET – RS – C1. The area enclosed by this current loop should be as small as possible. Keep the traces (especially 4 → 1) short, direct, and wide. High-voltage traces related to the drain of MOSFET and RCD snubber should be kept far way from control circuits to prevent unnecessary interference. If a heatsink is used for the MOSFET, connect this heatsink to ground. As indicated by 3, the ground of control circuits should be connected first, then to other circuitry. As indicated by 2, the area enclosed by transformer auxiliary winding, D1, C2, D2, and C3 should also be kept small. Place C3 close to the FAN6861 for good decoupling. GND3 → 2 → 4 → 1: This could avoid common impedance interference for sense signal. GND3 → 2 → 1 → 4: This could be better for ESD testing where the earth ground is not available on the power supply. Regarding the ESD discharge path, the charges go from secondary through the transformer stray capacitance to GND2 first. The charges then go from GND2 to GND1 and back to the mains. Note that control circuits should not be placed on the discharge path. Point discharge for common choke can decrease high-frequency impedance and increase ESD immunity. Should a Y-cap between primary and secondary be required, connect this Y-cap to the positive terminal of C1. If this Y-cap is connected to the primary GND, it should be connected to the negative terminal of C1 (GND1) directly. Point discharge of this Y-cap also helps for ESD. However, the creepage between these two pointed ends should be large enough to satisfy the requirements of applicable standards. L VDC AC Input + C1 N Common-Mode Choke D2 + D1 + C3 C2 5 VDD RA 3 GATE 6 RT RG RT RFB 2 FB SENSE 4 GND CFB RF CF RS 1 Y-cap FAN6861 Figure 13. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 6/9/09 Layout Considerations www.fairchildsemi.com 9 AN-6861 APPLICATION NOTE Design Summary Figure 1 shows the final schematic of the 20W (50W peak) power supply of the design example. 470pF L R S N2 C SN2 50 EMI AC inpu t R SN1 Filter + C IN N C DD 1 10µ F 10A/200 V 10nF R DAMP + D DD 2 + VO + + C O UT 1 470µ F DS N C O UT 2 VO - 220µ F 5 C DD 2 100µ F 5 V DD 82k D O UT 100k VIN 510k + 1.6µH 100µ F D DD1 R S T A RT C SN1 RG 3 RT GA TE 6 2 FB SE NSE 4 4N60 50 300 C FB 1nF R CSF G ND 1 FAN 6861 C CSF R CS 3k 0.39 R BIA S 120 k 470pF R1 R DB 2.2k RF 4.7k CF 10nF R2 KA431 10k Figure 14. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 6/9/09 Final Schematic of Design Example www.fairchildsemi.com 10 AN-6861 APPLICATION NOTE Figure 14. Figure 15. Transformer Specification Winding Specification Pin Diameter / Thickness Turns N1 5Æ3 Insulation Tape Shielding lead to Pin 2 Insulation Tape 0.4mm 31 1 1 3 6, 7 Æ 8, 9 Insulation Tape Shielding lead to Pin 2 Insulation Tape N3 3Æ4 Insulation Tape N4 1Æ2 Insulation Tape 0.55mm 20 3 1 1 30 3 8 N2 0.4mm 0.2mm 3 Core: EF25/13/11 (Ae=78 mm2) Bobbin: EF25/13/11 Inductance: 500μH © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 6/9/09 www.fairchildsemi.com 11 AN-6861 APPLICATION NOTE Related Datasheets FAN6861 — Low Cost and Highly Integrated Green-Mode PWM Controller for Peak Power Management DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 6/9/09 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 12