ICS AV9154A

Integrated
Circuit
Systems, Inc.
AV9154A
Low-Cost 16-Pin Frequency Generator
General Description
Features
.The AV9154A is a 0.8mm version of the industry leading AV9154.
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Like the AV9154, the AV9154A is a low-cost frequency generator
designed for general purpose PC and disk drive applications. However,
because the AV9154A uses 0.8mm technology and the latest phaselocked loop architecture, it offers performance advantages that
enable the device to be sold into Pentium™ systems.
The AV9154A guarantees a 45/55 duty cycle over all frequencies. In
addition, a worst case jitter of ±250ps is specified at Pentium
frequencies.
The CPU clock offers the unique feature of smooth, glitch-free
transitions from one frequency to the next, making this the ideal
device to use when slowing the CPU speed. The AV9154A makes a
gradual transition between frequencies so that it obeys the Intel
cycle-to-cycle timing specifications for 486 and Pentium systems.
The AV9154A-42 and AV9154A-43 devices offer features specifically
for green PCs. The AV9154A-42 and -43 have a single pin that,
when pulled low, will smoothly slow the 2XCPU clock to 8 MHz.
This is ideal for dynamic DX microprocessors. The AV9154A-43
not only has the slow clock feature, but also offers a glitch-free stop
clock for static SX microprocessors. The STOPCLK# pin, when
pulled low, enables the 2XCPU clock to go low only after completing
its last full cycle. The clock continues to run internally, and will be
output again on the first full cycle immediately following stop clock
disable.
The simultaneous 2X and 1X CPU clocks offer controlled skew to
within 500ps of each other (-42 only).
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Compatible with 386, 486 and Pentium CPUs
45/55 Duty cycle
Runs up to 66 MHz at 3.3V
Single pin can slow clock to 8 MHz (on -42 and -43)
Single pin can stop the CPU clock glitch-free (on -43)
Very low jitter, ±250ps for Pentium frequencies
1X and 2X CPU clocks skew controlled to ±250ps (-42
only)
Smooth transitions between all CPU frequencies
Slow frequency ramp at power-on avoids CPU lock-up
16-pin PDIP or 150-mil skinny SOIC packages
0.8µm CMOS technology
Applications
Computer motherboards: The AV9154A-ST replaces crystals
and oscillators, saving board space, component cost, part
count and inventory costs. It produces a switchable CPU clock
and up to four fixed clocks to drive floppy disk, communications,
super I/O, Bus, and/or keyboard devices. The small package
and 3.3V operation is perfect for handheld computers.
ICS has been shipping motherboard frequency generators since
April 1990, and is the leader in the area of multiple output clocks on
a single chip. Consult ICS for all your clock generation needs.
Block Diagram
Pentium is a trademark of Intel Corporation
9154 Rev B 04/17/97
AV9154A
Pin Configuration
16-Pin PDIP or SOIC
AV9154A-27
16-Pin PDIP or SOIC
AV9154A-42
16-Pin PDIP or SOIC
AV9154A-43
Description of new pin:
Description of new pis:
SLOWCLK# forces 2XCPUCLK
output to ramp smoothly to
8MHz and CPUCLK output to 4
MHz when pulled low.
SLOWCLK# forces 2XCPUCLK
output to ramp smoothly to
8MHz when pulled low.
STOPCLK# provides gilitchfree stop of the 2XCPUCLK
output when pulled low. When
raised
back
high,
the
2XCPUCLK output clock
resumes full speed operation
(no clock frequency ramp up
since the internal VCO is not
stopped).
16-Pin PDIP or SOIC
9154-04
16-Pin PDIP or SOIC
9154-10
16-Pin PDIP or SOIC
9154-26
2
AV9154A
Stop Clock Feature
The ICS9154A-43 incorporates a unique stop clock
feature compatible with static logic processors. When
the stop clock pin goes low, the 2XCPUCLK will go
low after the next occurring falling edge. When
STOPCLK again goes high, 2XCPUCLK resumes on
the next rising edge of the internal clock. This feature
enables fast, glitch-free starts and stops of the
2XCPUCLK and is guaranteed that the CPU does not
receive any short period clocks.
3
AV9154A
Pin Descriptions
Frequencies based upon 14.318 MHz input)
PIN NUMBER
PIN NAME
TYPE
-4
4
13
5
12
8
-10
4
13
5
12
8
-26
4
13
5
12
8
-27
4
13
5
12
8
-42
4
13
5
12
8
-43
4
13
5
12
8
VDD
VDD
GND
GDD
AGND
P
P
P
P
P
1
16
1
16
1
1
FS0
I
16
15
16
15
16
16
FS1
I
10
-
10
10
9
10
FS2
I
-
-
9
9
-
-
OE
I
-
-
-
-
15
15
SLOWCLK#
I
-
-
-
-
-
9
STOPCLK#
I
3
2
11
3
2
10
3
2
11
3
2
11
3
2
10
3
2
11
X1
X2
14.318 MHz
I
O
O
Digital power (3.3 or 5V).
Digital power (3.3 or 5V).
Digital ground.
Digital ground.
Analog ground.
Frequency select 0 for CPU clock
(has internal pull-up).*
Frequency select 1 for CPU clock
(has internal pull-up).*
Frequency select 2 for CPU clock
(has internal pull-up).*
Tristates outputs when low (has internal pull-up).*
Slows 2XCPU clock to 8 MHz (active low)
(has internal pull-up).
Stops 2XCPU clock glitch-free (active low)
(has internal pull-up).
Crystal In.
Crystal Out.
14.318 MHz reference clock output.
-
7
1
-
-
1.84 MHz
O
1.84 MHz (comm) clock output.
6
-
11
6
6
-
6
-
6
-
6
-
24 MHz
16 MHz
O
O
24 MHz (floppy disk) clock output.
16 MHz clock output.
-
-
7
7
-
-
12 MHz
O
12 MHz keyboard clock output.
7
1
-
-
7
7
8 MHz
O
8 MHz keyboard clock output.
14
14
14
-
11
-
CPUCLK
O
15
-
15
14
14
14
2XCPUCLK
O
2X CPU clock output.
9
-
-
-
-
-
PD#
I
-
9
-
-
-
-
PDFCLK#
I
Power-Down All (active low) (has internal pull-up).
Power-Down Fixed Clock
(1.84, 8, 16, 24) (active low).**
Note:
Internal Pull-up Resistors.
* -04 and -10 have no pull-ups or frequency select pins
** -10 has no pull-up or Pin 9 PDFCLK
4
DESCRIPTION
CPU clock output.
AV9154A
Clock Tables
(using 14.318 MHz input, all frequencies in MHz)
FS2
FS1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CPUCLK
8
20
16.67
12.50
30
10
33.33
25
-43
2XCPUCLK
^
16
40
33.33
25
60
20
66.66
50
CPUCLK
8.00
20.05
16.71
12.55
-43
2XCPUCLK
16.00
40.09
33.41
25.06
30.07
10.03
33.24
25.06
60.14
20.05
66.48
50.11
-42
-27
2XCPUCLK
FS0
2XCPUCLK
16
40
33.33
25
60
20
66.66
50
75*
32
60
40
50
66.66
80*
52
Actual Frequencies
(using 14.318 MHz input, all frequencies in MHz)
-42
-27
2CPUCLK
FS2
FS1
FS0
0
0
0
0
0
0
1
1
0
1
0
1
75.17*
31.94
60.14
40.09
2XCPUCLK
16.00
40.09
33.41
25.06
1
1
1
1
0
0
1
1
0
1
0
1
50.11
66.48
80.18*
51.90
60.14
20.05
66.48
50.11
Fixed Clock Output
Actual Frequencies
(using 14.318 MHz input,
all freqencies in MHz)
14.318
1.84
24.0
12.0
Clock Tables in MHz
for -04 and -10
(using 14.318 MHz input ,
all frequencies in MHz)
-04
-10
FS(3:0)
CPUCL2XCPU
CPU
K
0
100*
50*
PDCPU
1
80*
40*
40
2
66.6
33.3
50
3
50
25
66.6
8.0
4
5
6
7
-
40
32
24
16
20
16
12
8
-
* These selections only operate at 5 V.
5
Clock Table for AV9154A-26
(using 14.318 MHz input all frequencies in
MHz)
FS(2:0)
2XCPU
CPUCLK
(MHz)
(MHz)
0
100.23*
50.11
1
80.18*
40.09
2
66.48*
33.24
3
50.11
25.06
4
40.09
20.05
5
32.22
16.11
6
24.23
12.12
7
15.75
7.88
AV9154A
Absolute Maximum Ratings
VDD referenced to GND ........................................................................... 7.0 V
Voltage on I/O pins referenced to GND ..... GND - 0.5 V to VDD + 0.5 V
Operating Temperature under bias .............................................. 0 to +70 ºC
Power Dissipation ................................................................................... 0.5 W
Storage Temperature ............................................................... -40 to +150 ºC
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stess
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Electrical Characteristics at 3.3 V
VDD = 3.3 V ± 10%, TA = 0 - 70 oC unless otherwise stated
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage1
Output Low Current1
Output High Current1
Supply Current
Outp ut Frequ ency
C ha ng e o ve r Su p pl y
and Temperature1
Short circuit current1
Input Capacitance1
Load Capacitance1
Pull-up Resistor1
SYMBOL
VIL
VIH
IIL
IIH
VOL
VOH
IOL
IOH
IDD
TEST CONDITIONS
VIN = 0V (pull-up pin)
VIN = VDD
IOL = 6mA
IOH = -4mA
VOL = 0.2VDD
VOH = 0.7VDD
unloaded, 60 MHz
FD
With respect to typical frequency
ISC
CI
CL
Rpu
each output clock
except X1, X2
pins X1, X2
at VDD - 0.5V
Notes:
1. Parameter is guaranteed by design and characterization.
6
MIN
0.7 V
-5.0
0.85 VDD
15.0
-
TYP
2.5
0.05 VDD
0.94 VDD
24
-13
16
MAX
0.2 VDD
7.0
5.0
0.1 VDD
-8.0
34
UNITS
V
V
A
A
V
V
mA
mA
mA
-
0.002
0.01
%
20
-
30
20
620
10
900
mA
pF
pF
k ohm
AV9154A
Electrical Characteristics at 3.3 V
VDD = 3.3 V ± 10%, TA = 0 - 70 oC unless otherwise stated
AC Characteristics
PARAMETER
Input Clock Rise Time
SYMBOL
1
Input Clock Fall Time1
Rise time, 20% to 80%
VDD1
Fall time, 80% to 20%
VDD1
Duty cycle at 50% VDD1
Duty cycle, reference
clocks1
Jitter, one sigma, 20-66
MHz clocks1
Jitter, one sigma, clocks
below 20 MHz1
Jitter, absolute, 20-66
MHz clocks1
Jitter, absolute, clocks
below 20 MHz1
Input Frequency1
Maximum Output
Frequency1
Clock skew between CPU
and 2XCPU outputs1
Power-up Time1
Frequency Transition
Time1
TEST CONDITIONS
MIN
TYP
MAX
UNITS
tICr
-
-
20
ns
tICf
-
-
20
ns
tr
15pF load
-
2.2
3.5
ns
tf
15pF load
-
1.2
2.5
ns
dt
15pF load
40/60
48/52
60/40
%
dt
15pF load
50/65
43/57
65/50
%
tj1s
10,000 cycles
-
100
200
ps
tjls
10,000 cycles
-
1.0
2.0
%
tjab
10,000 cycles
-350
-
350
ps
tjab
10,000 cycles
-
1.5
4.0
%
fin
2
14.318
32
MHz
fout
70
-
-
MHz
T sk
AV9154A-42
-
220
500
ps
ttPO
off to 50 MHz
-
6
12
ms
from 8 to 50 MHz
-
4.5
10
ms
tft
Notes:
1. Parameter is guaranteed by design and characterization. Not subject to production testing.
7
AV9154A
Electrical Characteristics at 5.0 V
VDD = +5 ± 10% V, T A = 0 - 70oC unless otherwise stated
DC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage
VIL
VDD=5 V
-
-
0.8
V
Input High Voltage
VIH
VDD=5 V
2.0
-
-
V
Input Low Current
IIL
VIN=0 V (pull-up pin)
-
6
15
A
Input High Current
IIH
VIN = VDD
-5
-
5
A
Output Low Voltage
VOL
IOL = 10 mA
-
0.15
0.4
V
Output High Voltage1
VOH
IOH = -30 mA
2.4
3.7
-
V
Output Low Current1
IOL
VOL = 0.8 V
25
45
-
mA
Output High Current1
IOH
VOH = 2.4 V
-
-53
-35
mA
Supply Current
IDD
unloaded, 66 MHz
-
25
50
mA
Output Frequency Change
over Supply and Temperature1
FD
with respect to typical
frequency
-
0.002
0.01
%
Short circuit current1
ISC
each output clock
25
40
-
mA
Input Capacitance1
CI
except X1, X2
-
-
10
pF
Load Capacitance1
CL
pins X1, X2
-
20
-
pF
Pull-up Resistor1
Rpu
A + VDD -1 V
-
400
700
k ohm
Notes:
1. Parameter is guaranteed by design and characterization. Not subject to production testing.
8
AV9154A
Electrical Characteristics at 5.0 V
VDD = +5 ±10% V, T A = 0 - 70oC unless otherwise stated
AC Characteristics
PARAMETER
SYMBOL
1
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Clock Rise Time
tICr
-
-
20
ns
Time1
Input Clock Fall
Output Rise time, 0.8 to
2.0V1
Rise time, 20% to 80% V1
Output Fall time, 2.0 to
0.8V1
tICf
-
-
20
ns
tr
15pF load
-
1.5
2
ns
tr
15pF load
-
2.0
3
ns
tf
15pF load
-
0.5
1.5
ns
Fall time, 80% to 20% V1
tf
15pF load
-
2.0
3.0
ns
Duty cycle at 1.4V1
Duty cycle, reference
clocks1
Jitter, one sigma, 20 MHz80 MHz clocks1
Jitter, one sigma, clocks
below 20 MHz1
Jitter, absolute, 20 MHz80 MHz clocks1
Jitter, absolute, clocks
below 20 MHz1
dt
15pF load, VDD = 5V±5%
45/55
48/52
55/45
%
dt
15 pF load
40/65
43/57
65/40
%
tj1s
10,000 cycles
-
70
140
ps
tjls
10,000 cycles
-
0.8
2.0
%
tjab
10,000 cycles
-250
-
250
ps
tjab
10,000 cycles
-
1.0
3.0
%
fin
2
14.318
32
MHz
fout
140
-
-
MHz
Input Frequency
Maximum Output
Frequency1
Clock skew between CPU
and 2XCPU outputs1
Tsk
AV9154A-42
-
140
400
ps
Power-up Time1
ttPO
to 80 MHz
-
8
15
ms
Frequency Transition
Time1
tft
from 8 to 66.66 MHz
-
6.5
12
ms
Notes:
1. Parameter is guaranteed by design and characterization. Not subject to production testing.
9
AV9154A
0.260
0.765
0.325
0.130
0.015min
0.010
0 ~ 5º
0.060
0.130
0.360
0.100
0.018
16-Pin PDIP Package
0.031
0.063
0.390
0.238
0.015
0.154
0.008
0.050
0.024
0.006±0.004
0.016
0.025
16-Pin SOIC Package
Ordering Information
AV9154A-04CN16
AV9154A-10CN16
AV9154A-26CN16
AV9154A-27CN16
AV9154A-42CN16
AV9154A-43CN16
AV9154A-04CS16
AV9154A-10CS16
AV9154A-26CS16
AV9154A-27CS16
AV9154A-42CS16
AV9154A-43CS16
Example:
ICS XXXX-PPP M X#W
Lead Count & Package Width
Lead Count=1,2, or 3 digits
W=0.3" SOIC or 0.6" DIP; None=Standard Width
Package Type
N=DIP (Plastic),
S=SOIC
Pattern Number (2 or 3-digit number for parts with ROM-code patterns)
Device Type (consists of 3 or 4-digit numbers)
Prefix
ICS, AV=Standard Device; GSP=Genlock device
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