APLUS AVXX32E-A

A
PLUS MAKE YOUR PRODUCTION A-PLUS
AVXX32E -A SERIES
DATA SHEET
APLUS
INTEGRATED CIRCUITS INC.
Address:
3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,
Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.
Sales E-mail:
[email protected]
TEL: 886-2-2782-9266
Technology E-mail:
[email protected]
FAX: 886-2-2782-9255
WEBSITE : http: //www.aplusinc.com.tw
AVXX32E -A SERIES
3, 7, 14 Seconds Complicate Pure Speech
Features
y Operating voltage: 2.4V~5.0V
y One single-key can implement play-all,
play-next and random function.
y Maximum play count is 16.
y Each input can implement looping function.
y Single-key input can be last-key priority for
stand-alone input or first-key priority.
y Each input trigger can select trigger mode: (For
OKY, TG0, TG1, TG3) Edge/Level, Hold/Unhold,
Retrigger/Irretrigger.
y Each input trigger can select its own debounce
time:
Fast debounce: < 200us;
Slow debounce: ~16ms (S.R.=6.0kHz)
y Support bouncing trigger solution for retrigger
application. (Second trigger force to retrigger
and slow debounce.)
y Maximum table entries are 204*4.
y Word count is only limited by ROM capacity.
y 3 output ports for Status or LED application:
Ϋʳ OP_A Status:
Busy_high, DC_low, Stop_high,DC_high
LED: +Fast,+Slow, Dyn(7/10), Off
Ϋʳ OP_B Status:
Busy_high, DC_low, Stop_high, DC_high
LED: -Fast, -Slow, Dyn(9/10), On
OP_C Status: Busy_high, DC_low,
Busy_low, DC_high
LED: +Fast, +Slow, On, Off
Each output can specify its initial state (High or
Low)
Outputs can be set as constant current
regardless of the supply voltage varied.
Two PWM playing ports. Drive speaker or
buzzer directly.
Body define: 3, 7, 14 seconds. (Total ROM size :
18k,42k,84k)
voice length(3s body:16384*5,7s
body:40960*5,14s body:83968*5)
Voice algorithm: 5-bits LOG_PCM
External resister for system frequency
Sixteen default sampling frequencies are
supported. The default frequencies can be
changed by applying an external resistor.
Support single key play on/off. (For OKY, TG0,
TG1)
Programmable only pull-low input. (For
OKY,TG3)
Programmable pull-high, pull-low or floating
input. (For TG0,TG1)
TG3_OPC pin can option as input or output by
mask option
Ϋʳ
y
y
y
y
y
y
y
y
y
y
y
y
General Description
The AVXX32E -A are series of single-chip
synthesizing CMOS VLSI IC which synthesizes
voice by LOG_PCM algorithm. Table programming
and shared multiple I/O pins make the applications
flexible.
Powerful functions and pure speech architecture
make the AVXX32E -A series are able to best fit
most speech applications and a best
cost/performance ratio as a result.
The programming of the AVXX32E -A series is
first to define words. Each word contains voice data
(or mute length), output method, assemble the
words into sentences first, and then the programmer
can assign the sentences to the keys corresponding
to the user inputs.
The TG3_OPC pin of the AVXX32E -A series is
multiplexed. This means it can option as input pin or
output pin.
Body Option Table
Body
ROM
Table
KEY
OUT
AV0332E
84K
D0 – 3FF
OKY, TG0 – TG1 & TG3
OPA, OPB, OPC
AV0732E
42K
D0 – 2FF
OKY, TG0 – TG1 & TG3
OPA, OPB, OPC
AV1432E
18K
D0 – 1FF
OKY, TG0, TG3
OPA, OPC
Preliminary
9-1
Ver. 0.1
AVXX32E -A SERIES
Pin Description
Pin Name
VDD
TEST
OSC
I/O
Power
In
In
In
OKY
TG0, TG1
TG3_OPC
OPB
OPA
PWM1,
PWM2
VSS
Description
Positive power supply
Test enable pad, high-active, pull-low
With resister connected to VDD for system clock generating
In
In
Out
Out
Trigger input, active-high, with internal pull_low resistor. Can define
as sequential key or random key.
Trigger input, active-high with internal pull_low resistor.
Trigger input, active-high
Status output
Status output
Out
Status output
Out
Voltage output to drive speaker or buzzer
Power
Negative power supply
Absolute Maximum Rating
Symbol
VDD~VSS
VIN (for input)
VOUT (for all outputs)
T (operating)
T (storage)
Rating
-0.5 ~ +0.5
VSS-0.3 < VIN < VDD+0.3
VSS < VOUT < VDD
-10 ~ +60
-55 ~ +125
Unit
V
V
V
к
к
DC Characteristics
Symbol
VDD
Isb
Iop
IOL
Ioh
d F/F
Parameter
Operating Voltage
Standby
Supply
Current
Operating
OPA, OPB source Current
OPA, OPB sink Current
Frequency Variation by diff.
lot
Min Typ. Max
2.4 3.0 5.0
Ϋ
Ϋ
1
Ϋ
Ϋ 400
Ϋ –20 Ϋ
Ϋ
Ϋ
20
Ϋ
Ϋ
r10
Unit
V
ӴA
ӴA
mA
mA
%
Condition
VDD=3.0V, I/O open
VDD=3.0V, No loading
VDD=3.0V, VIP=2.7V
VDD=3.0V, VOP=0.3V
VDD=4.5V
fOSC =384kHz
Function Diagram
1. OPA/B/C (1:0) are the output options.
Output
Option
0(00)
1(01)
2(10)
3(11)
OPA
Status
BH
DL
SH
DH
LED
+Fast
+Slow
Dy07
OFF
Status
BH
DL
SH
DH
LED
-Fast
-Slow
Dy09
ON
Status
BH
DL
BL
DH
LED
+Fast
+Slow
ON
OFF
OPB
OPC
Status output mode:
SH: Single pulse output, hi-level output
BH: Busy output, hi-level output
Preliminary
9-2
Ver. 0.1
AVXX32E -A SERIES
BL: Busy output, lo-level output
DH: Always Hi-level output
DL: Always Lo-level output
LED output mode:
+Fast, -Fast: High frequency alternate output
+Slow, -Slow: Low frequency alternate output
Dy09: Volume level (9/10)output control. If code > 9/10(FFh), then output “Lo”. Otherwise output “Hi”
Dy07: Volume level (7/10)output control. If code > 7/10(FFh), then output “Lo”. Otherwise output “Hi”
ON : Always Lo-level output
OFF: Always Hi-level output
Note: The Status and LED mode is optioned by mask option.
Edge/Level mode (If sentence = word1+word2)
y Edge mode
Trigger length > Voice length
TG
Audio
word1 word2
debounce time
Trigger length < Voice length
TG
word1 word2
debounce time
y Level mode
Trigger length > Voice length (if sentence=word1+word2)
TG
Audio
word1 word2 word3 word4
debounce time
Trigger length < Voice length (if sentence = word1+word2)
TG
Audio
word1 word2
debounce time
Preliminary
9-3
Ver. 0.1
AVXX32E -A SERIES
Hold/Unhold mode (If sentence = word1+word2)
y Hold mode
TG
word2
Audio
word1
debounce time
y Unhold mode
TG
Audio
word1 word2
debounce time
Retrigger/Irretrigger mode (If sentence = word1+word2)
y Retrigger mode (Edge Unhold mode)
TG
Audio
word1
word2
word3 word4
debounce time
y Irretrigger mode (Edge, Unhold mode)
TG
Audio
word1 word2
debounce time
Last key priority
y If TG1, TG3 are retrigger mode
˧˚ ˄
˧˚ ˆ
˔̈˷˼̂
˧˚ ˄ʺ̆ ˧˚ ˆʺ̆
˧˚ ˄ʺ̆
˧˚ ˆʺ̆
Looping function
If sentence is set to looping mode (sentence1_sentence2)
Preliminary
9-4
Ver. 0.1
AVXX32E -A SERIES
y Unhold mode
TG
Audio
sentence1 sentence2 sentence2 sentence2
y Hold mode
TG
sentence2
Audio
sentence1 sentence2
Force to retrigger and slow debounce option
(Trigger mode set to Fast debounce and Irretrigger mode)
1st TG
FRSB
Don't care
Audio
W11
W12
W13
W14
This word must be larger than glitch period.
(A mute word can be used berhaps.)
2nd TG
FRSB
Audio
W21
Slow debounce,
Retrigger mode
W22
W23
W24
Slow debounce,
Retrigger mode
Fast debounce,
Irretrigger mode
Fast debounce,
Irretrigger mode
Busy=0, FRSB set to high;
Busy=1, depending on FRSB setting.
If FRSB=0, force to slow debounce and retrigger mode;
If FRSB=1, no change (fast debounce and irretrigger mode).
Stand-alone trigger inputs are enabled at the same time
OKY
TG0
TG1
TG3
Audio
This voice is enabled by TG3
Preliminary
9-5
Ver. 0.1
AVXX32E -A SERIES
Trigger input priority is TG3 > TG1 > TG0 > OKY
Application circuit
y External resister, Driver speaker by PWM, driver LED
9''
5RVF
26&
2.<
-$
23B$
-$
-$
3:0
3:0
966
ROSC=200k: for frequency option 8
y Direct Keys
526&
26&
9''
23B$
2.<
23B%
7*
3:0
3:0
7*
23B&
966
Preliminary
-$
-$
-$
9-6
Ver. 0.1
AVXX32E -A SERIES
y Pad Diagram & Pad Location
(1) AV0332E
<
-$
;
Note: The IC substrate should be connect to VSS
Pad No.
Pad Name
X(um)
Y(um)
Pad No.
Pad Name
X(um)
Y(um)
1
PAD_OSC
108.75
214.05
6
PAD_TG0
1281.1
94.05
2
PAD_OKY
356.2
94.05
7
VDD
1302.8
595.6
3
PAD_OPA
586.1
94.05
8
PAD_PWM2
1101.9
595.6
4
PAD_TG3OPC
777.4
94.05
9
PAD_PWM1
681.1
595.6
5
PAD_TEST
1007.3
94.05
10
Preliminary
9-7
VSS
480.2
595.6
Chip size : 1387.9 x 696.6 (Pm)2
Ver. 0.1
AVXX32E -A SERIES
(2) AV0732E
<
-$
;
Note: The IC substrate should be connect to VSS
Pad No.
Pad Name
X(um)
Y(um)
Pad No.
Pad Name
X(um)
Y(um)
1
PAD_OSC
108.75
214.05
7
PAD_TG1
1279.15
94.05
2
PAD_OKY
108.75
94.05
8
PAD_TG0
1279.15
214.05
3
PAD_OPA
291.65
94.05
9
VDD
1302.8
722.3
4
PAD_OPB
573.45
94.05
10
PAD_PWM2
1101.9
722.3
5
PAD_TG3OPC
764.75
94.05
11
PAD_PWM1
681.1
722.3
6
PAD_TEST
994.65
94.05
12
Preliminary
9-8
VSS
480.2
722.3
Chip size : 1387.9 x 823.3 (Pm)2
Ver. 0.1
AVXX32E -A SERIES
(3)AV1432E
<
-$
;
Note: The IC substrate should be connect to VSS
Pad No.
Pad Name
X(um)
Y(um)
Pad No.
Pad Name
X(um)
Y(um)
1
PAD_OSC
108.75
214.1
7
PAD_TG1
1279.2
94.05
2
PAD_OKY
108.75
94.05
8
PAD_TG0
1279.2
214.1
3
PAD_OPA
291.65
94.05
9
VDD
1302.8
867
4
PAD_OPB
573.45
94.05
10
PAD_PWM2
1101.9
867
5
PAD_TG3OPC
764.75
94.05
11
PAD_PWM1
681.1
867
6
PAD_TEST
994.65
94.05
12
VSS
Preliminary
9-9
480.2
867
Chip size : 1387.9 x 968 (Pm)2
Ver. 0.1